aboutsummaryrefslogtreecommitdiff
path: root/opcodes
AgeCommit message (Collapse)AuthorFilesLines
2000-05-12Fix disassembly of DLRS{H|B} instructionNick Clifton2-1/+6
2000-05-11Don't mask top 32 bits of 64-bit address.Alan Modra2-2/+9
2000-05-10* ppc-opc.c (powerpc_opcodes): Make the predicted-branch opcodesGeoffrey Keating2-363/+368
also available in common mode when powerpc syntax is being used.
2000-05-08Kill compiler warnings with ATTRIBUTE_UNUSED.Alan Modra2-5/+11
2000-05-06Support for tic54x target.Timothy Wall8-0/+1140
2000-05-03* ppc-opc.c (VA, VB, VC, VD, VS, SIMM, UIMM, SHB): New macros, forJ.T. Conklin3-4/+247
vector unit operands. (VX, VX_MASK, VXA, VXA_MASK, VXR, VXR_MASK): New macros, for vector unit instruction formats. (PPCVEC): New macro, mask for vector instructions. (powerpc_operands): Add table entries for above operand types. (powerpc_opcodes): Add table entries for vector instructions. * ppc-dis.c (print_insn_big_powerpc): Add PPC_OPCODE_ALTIVEC to mask. (print_insn_little_powerpc): Likewise. (print_insn_powerpc): Prepend 'v' when printing vector registers.
2000-05-01 * avr-dis.c (reg_fmul_d): New. Extract destination register fromDenis Chertykov2-3/+130
FMUL instruction. (reg_fmul_r): New. Extract source register from FMUL instruction. (reg_muls_d): New. Extract destination register from MULS instruction. (reg_muls_r): New. Extract source register from MULS instruction. (reg_movw_d): New. Extract destination register from MOVW instruction. (reg_movw_r): New. Extract source register from MOVW instruction. (print_insn_avr): Handle MOVW, MULS, MULSU, FMUL, FMULS, FMULSU, EICALL, EIJMP, LPM r,Z, ELPM r,Z, SPM, ESPM instructions.
2000-04-26 Add XCOFF64 support.Clinton Popetz4-166/+166
bfd: * Makefile.am (coff64-rs6000.lo): New rule. * Makefile.in: Regenerate. * coff-rs6000.c (xcoff_mkobject, xcoff_copy_private_bfd_data, xcoff_is_local_label_name, xcoff_rtype2howto, xcoff_reloc_type_lookup, xcoff_slurp_armap, xcoff_archive_p, xcoff_read_ar_hdr, xcoff_openr_next_archived_file, xcoff_write_armap, xcoff_write_archive_contents): No longer static, and prefix with _bfd_. (NO_COFF_SYMBOLS): Define. (xcoff64_swap_sym_in, xcoff64_swap_sym_out, xcoff64_swap_aux_in, xcoff64_swap_aux_out): New functions; handle xcoff symbol tables internally. (MINUS_ONE): New macro. (xcoff_howto_tabl, xcoff_reloc_type_lookup): Add 64 bit POS relocation. (coff_SWAP_sym_in, coff_SWAP_sym_out, coff_SWAP_aux_in, coff_SWAP_aux_out): Map to the new functions. * coff64-rs6000.c: New file. * libcoff.h (bfd_coff_backend_data): Add new fields _bfd_coff_force_symnames_in_strings and _bfd_coff_debug_string_prefix_length. (bfd_coff_force_symnames_in_strings, bfd_coff_debug_string_prefix_length): New macros for above fields. * coffcode.h (coff_set_arch_mach_hook): Handle XCOFF64 magic. Set machine to 620 for XCOFF64. Use bfd_coff_swap_sym_in instead of using coff_swap_sym_in directly. (FORCE_SYMNAMES_IN_STRINGS): New macro, defined for XCOFF64. (coff_set_flags) Set magic for XCOFF64. (coff_compute_section_file_positions): Add symbol name length to string section length if bfd_coff_debug_string_prefix_length is true. (coff_write_object_contents): Don't do reloc overflow for XCOFF64. (coff_slurp_line_table): Use bfd_coff_swap_lineno_in instead of using coff_swap_lineno_in directly. (bfd_coff_backend_data): Add _bfd_coff_force_symnames_in_strings and _bfd_coff_debug_string_prefix_length fields. * coffgen.c (coff_fix_symbol_name, coff_write_symbols): Force symbol names into strings table when bfd_coff_force_symnames_in_strings is true. * coffswap.h (MAX_SCNHDR_NRELOC, MAX_SCNHDR_NLNNO, GET_RELOC_VADDR, SET_RELOC_VADDR): New macros. (coff_swap_reloc_in, coff_swap_reloc_out): Use above macros. (coff_swap_aux_in, coff_swap_aux_out): Remove RS6000COFF_C code. (coff_swap_aouthdr_in, coff_swap_aouthdr_out): Handle XCOFF64 changes within RS6000COFF_C specific code. (coff_swap_scnhdr_out): Use PUT_SCNHDR_NLNNO, PUT_SCNHDR_NRELOC, MAX_SCNHDR_NRELOC, and MAX_SCNHDR_NLNNO. * reloc.c (bfd_perform_relocation, bfd_install_relocation): Extend existing hack on target name. * xcofflink.c (XCOFF_XVECP): Extend existing hack on target name. * coff-tic54x.c (ticof): Keep up to date with new fields in bfd_coff_backend_data. * config.bfd: Add bfd_powerpc_64_arch to targ_arch and define targ_selvecs to include rs6000coff64_vec for rs6000. * configure.in: Add rs6000coff64_vec case. * cpu-powerpc.c: New bfd_arch_info_type. gas: * as.c (parse_args): Allow md_parse_option to override -a listing option. * config/obj-coff.c (add_lineno): Change type of offset parameter from "int" to "bfd_vma." * config/tc-ppc.c (md_pseudo_table): Add "llong" and "machine." (ppc_mach, ppc_subseg_align, ppc_target_format): New. (ppc_change_csect): Align correctly for XCOFF64. (ppc_machine): New function, which discards "ppc_machine" line. (ppc_tc): Cons for 8 when code is 64 bit. (md_apply_fix3): Don't check operand->insert. Handle 64 bit relocations. (md_parse_option): Handle -a64 and -a32. (ppc_xcoff64): New. * config/tc-ppc.h (TARGET_MACH): Define. (TARGET_FORMAT): Move to function. (SUB_SEGMENT_ALIGN): Use ppc_subseg_align. include: * include/coff/rs6k64.h: New file. opcodes: * configure.in: Add bfd_powerpc_64_arch. * disassemble.c (disassembler): Use print_insn_big_powerpc for 64 bit code.
2000-04-24Initialise signed_overflow fieldNick Clifton2-0/+8
2000-04-23Misc assembly/disassembly fixes.Timothy Wall7-3944/+5686
2000-04-21 * hppa-dis.c (extract_16): New function.Jeff Law2-19/+77
(print_insn_hppa): Fix incorrect handling of 'fe'. Added handling of new operand types l,y,&,fe,fE,fx.
2000-04-21IA-64 ELF support.Jim Wilson23-0/+13187
2000-04-20* m10300-dis.c (HAVE_AM30, HAVE_AM33): Define.Alexandre Oliva2-1/+10
(disassemble): Use them.
2000-04-14More portability patches. Include sysdep.h everywhere.Alan Modra47-256/+317
2000-04-09Remove ``-W -Wall'' from top-level Makefile/configure.Andrew Cagney5-513/+463
Add ``-W -Wall'' to sub-directories bfd, binutils, gas gprof, ld and opcodes by the addition of WARN_CFLAGS to Makefile.am and configury to set it. Add configure option --enable-build-warnings. Re-generate all and sundry using auto*-000227.
2000-04-05opcodes:Joern Rennecke2-11/+18
* sh-opc.c (sh_table): Use A_DISP_PC / PCRELIMM_8BY2 for ldre & ldrs. stc GBR,@-<REG_N> is available for arch_sh1_up. Group parallel processing insn with identical mnemonics together. Make three-operand psha / pshl come first. gas: * config/tc-sh.c (get_operands): There's no third operand if the first operand is an immediate.
2000-04-05sh-dsp REPEAT support:Joern Rennecke3-48/+68
opcodes: * sh-opc.h (sh_nibble_type): Remove DISP_8 and DISP_4. Split IMM_[48]{,BY[24]} into IMM[01]_[48]{,BY[24]}. Add REPEAT. (sh_arg_type): Add A_PC. (sh_table): Update entries using immediates. Add repeat. * sh-dis.c (print_insn_shx): Remove DISP_8 and DISP_4. Split IMM_[48]{,BY[24]} into IMM[01]_[48]{,BY[24]}. Add REPEAT. gas: * config/tc-sh.c (immediate): Delete. (sh_operand_info): Add immediate member. (parse_reg): Use A_PC for pc. (parse_exp): Add second argument 'op'. All callers changed. (parse_at): Expect pc to be coded as A_PC. Use immediate field in *op. (insert): Add fourth argument 'op'. All callers changed. (build_relax): Add second argument 'op'. All callers changed. (insert_loop_bounds): New function. (build_Mytes): Remove DISP_4. Split IMM_[48]{,BY[24]} into IMM[01]_[48]{,BY[24]}. Add REPEAT. (assemble_ppi): Use immediate field in *operand. (sh_force_relocation): Handle BFD_RELOC_SH_LOOP_{START,END}. (md_apply_fix): Likewise. (tc_gen_reloc): Likewise. Check for a pcrel BFD_RELOC_SH_LABEL. include/coff: * sh.h (R_SH_LOOP_START, R_SH_LOOP_END): Define. include/elf: * sh.h (R_SH_LOOP_START, R_SH_LOOP_END): New RELOC_NUMBERs. bfd: * reloc.c (_bfd_relocate_contents): Add BFD_RELOC_SH_LOOP_START and BFD_RELOC_SH_LOOP_END. * elf32-sh.c (sh_elf_howto_tab): Change special_func to sh_elf_ignore_reloc for all entries that sh_elf_reloc used to ignore. Add entries for R_SH_LOOP_START and R_SH_LOOP_END. (sh_elf_reloc_loop): New function. (sh_elf_reloc): No need to test for always-to-be-ignored relocs any more. (sh_rel): Add entries for BFD_RELOC_SH_LOOP_{START,END}. (sh_elf_relocate_section): Handle BFD_RELOC_SH_LOOP_{START,END}. * bfd-in2.h, libbfd.h: Regenerate.
2000-04-04Move translated part of bug report string back into .c files soAlan Modra2-1/+3
xgettext can find it. Regnerate .pot files.
2000-04-04Use "gcc -MM" for dependencies, and update them.Alan Modra3-111/+146
2000-04-03Tidy some code. Print pc rel addresses as signed.Alan Modra2-60/+29
2000-04-02 * disassemble.c (disassembler_usage): Don't use a prototype. MarkIan Lance Taylor3-24/+31
the parameter ATTRIBUTE_UNUSED. * ppc-opc.c: Add ATTRIBUTE_UNUSED as needed.
2000-04-01* m10300-opc.c: SP-based offsets are always unsigned.Alexandre Oliva2-12/+16
2000-03-31Reverted the comment about inc/inc4, that was already implied by RN02.Alexandre Oliva1-1/+0
2000-03-31Fix typos. Add FIXME for 2-reg inc and inc4.Alexandre Oliva1-9/+10
2000-03-29Disassemble 0xde.. to "bal" [branch always] instead of "undefined".Nick Clifton2-3/+10
2000-03-27Fix value of SHORT_A1.Nick Clifton2-1/+6
Move SHORT_AR to end of list of short instructions.
2000-03-27 * Makefile.am (CFILES): Add avr-dis.c.Ian Lance Taylor3-0/+9
(ALL_MACHINES): Add avr-dis.lo.
2000-03-27ATMEL AVR microcontroller support.Alan Modra5-322/+1015
2000-03-06 * sh-opc.h (sh_table): ldre and ldrs have a *signed* displacement.Joern Rennecke2-2/+6
2000-03-02Apply patch for 100679Nick Clifton3-69/+104
2000-02-28Replace 'flags' with 'signed_overflow_ok_p'Nick Clifton2-1/+6
2000-02-272000-02-27 Eli Zaretskii <eliz@is.elta.co.il>Ian Lance Taylor3-4/+12
* Makefile.am (stamp-lib): Use $(LIBTOOL) --config to get the name of the libtool directory. * Makefile.in: Rebuild.
2000-02-27rebuild with current toolsIan Lance Taylor5-1084/+469
2000-02-24Add functions to modify/examine the signed_overflow_ok_p field in cpu_desc.Nick Clifton2-1/+31
2000-02-242000-02-23 Andrew Haley <aph@cygnus.com>Andrew Haley7-24/+54
* m32r-asm.c, m32r-desc.c, m32r-desc.h, m32r-dis.c, m32r-ibld.c,m32r-opc.h: Rebuild.
2000-02-23Add IBM 370 support.Alan Modra8-340/+1587
2000-02-22 * d30v-opc.c (d30v_opcode_tab) : Added FLAG_NOT_WITH_ADDSUBppp toChandra Chavva2-10/+15
ST2H, STB, STH, STHH, STW and ST2H opcodes to prohibit parallel procedure.
2000-02-221999-12-30 Andrew Haley <aph@cygnus.com>Andrew Haley3-1/+11
* mips-dis.c (_print_insn_mips): New arg for OPCODE_IS_MEMBER: force gp32 to zero. * mips-opc.c (G6): New define. (mips_builtin_op): Add "move" definition for -gp32.
2000-02-22 From Grant Erickson <gerickso@Brocade.COM>:Ian Lance Taylor2-2/+7
* ppc-opc.c: Correct dcread--it takes 3 arguments, not 2.
2000-02-21This lot mainly cleans up `comparison between signed and unsigned' gccAlan Modra2-5/+10
warnings. One usused var, and a macro parenthesis fix too. Also check input sections are elf when doing gc in elflink.h.
2000-02-17bfd:Joern Rennecke3-242/+860
Reinstate bits of sh4 support that got accidentally deleted. Add sh-dsp support. bfd: * archures.c (bfd_mach_sh2, bfd_mach_sh_dsp): New macros. (bfd_mach_sh3_dsp): Likewise. (bfd_mach_sh4): Reinstate. (bfd_default_scan): Recognize 7410, 7708, 7729 and 7750. * bfd-in2.h: Regenerate. * coff-sh.c (struct sh_opcode): flags is no longer short. (USESAS, USESAS_REG, USESR8, SETSAS, SETSAS_REG): New macros. (sh_opcode41, sh_opcode42): Integrate as sh_opcode41. (sh_opcode01, sh_opcode02, sh_opcode40): Add sh-dsp opcodes. (sh_opcode41, sh_opcode4, sh_opcode80): Likewise. (sh_opcodes): No longer const. (sh_dsp_opcodef0, sh_dsp_opcodef): New arrays. (sh_insn_uses_reg): Check for USESAS and USESR8. (sh_insn_sets_reg, sh_insns_conflict): Check for SETSAS. (_bfd_sh_align_load_span): Return early for SH4. Modify sh_opcodes lookup table for sh-dsp / sh3-dsp. Take into account that field b of a parallel processing insn could be mistaken for a separate insn. * cpu-sh.c (arch_info_struct): New array elements for sh2, sh-dsp and sh3-dsp. Reinstate element for sh4. (SH2_NEXT, SH_DSP_NEXT, SH3_DSP_NEXT): New macros. (SH4_NEXT): Reinstate. (SH3_NEXT, SH3E_NEXT): Adjust. * elf-bfd.h (_sh_elf_set_mach_from_flags): Declare. * elf32-sh.c (sh_elf_set_private_flags): New function. (sh_elf_copy_private_data, sh_elf_set_mach_from_flags): Likewise. (sh_elf_merge_private_data): New function. (elf_backend_object_p, bfd_elf32_bfd_set_private_bfd_flags): Define. (bfd_elf32_bfd_copy_private_bfd_data): Define. (bfd_elf32_bfd_merge_private_bfd_data): Change to sh_elf_merge_private_data. gas: * config/tc-sh.c ("elf/sh.h"): Include. (sh_dsp, valid_arch, reg_x, reg_y, reg_efg): New static variables. (md.begin): Initialize target_arch. Only include opcodes in has table that match selected architecture. (parse_reg): Recognize register names for sh-dsp. (parse_at): Recognize post-modify addressing. (get_operands): The leading space is now optional. (get_specific): Remove FDREG_N support. Add support for sh-dsp arguments. Update valid_arch. (build_Mytes): Add support for SDT_REG_N. (find_cooked_opcode): New function, broken out of md_assemble. (assemble_ppi, sh_elf_final_processing): New functions. (md_assemble): Use find_cooked_opcode and assemble_ppi. (md_longopts, md_parse_option): New option: -dsp. * config/tc-sh.h (elf_tc_final_processing): Define. (sh_elf_final_processing): Declare. include/elf: * sh.h: (EF_SH_MACH_MASK, EF_SH_UNKNOWN, EF_SH1, EF_SH2): New macros. (EF_SH3, EF_SH_HAS_DSP, EF_SH_DSP, EF_SH3_DSP): Likewise. (EF_SH_HAS_FP, EF_SH3E, EF_SH4, EF_SH_MERGE_MACH): Likewise. opcodes: * sh-dis.c (print_movxy, print_insn_ddt, print_dsp_reg): New functions. (print_insn_ppi): Likewise. (print_insn_shx): Use info->mach to select appropriate insn set. Add support for sh-dsp. Remove FD_REG_N support. * sh-opc.h (sh_nibble_type): Add new values for sh-dsp support. (sh_arg_type): Likewise. Remove FD_REG_N. (sh_dsp_reg_nums): New enum. (arch_sh1, arch_sh2, arch_sh3, arch_sh3e, arch_sh4): New macros. (arch_sh_dsp, arch_sh3_dsp, arch_sh1_up, arch_sh2_up): Likewise. (arch_sh3_up, arch_sh3e_up, arch_sh4_up, arch_sh_dsp_up): Likewise. (arch_sh3_dsp_up): Likewise. (sh_opcode_info): New field: arch. (sh_table): Split up insn with FD_REG_N into ones with F_REG_N and D_REG_N. Fill in arch field. Add sh-dsp insns.
2000-02-142000-02-14 Fernando Nasser <fnasser@totem.to.cygnus.com>Fernando Nasser2-3/+43
* arm-dis.c: Change flavor name from atpcs-special to special-atpcs to prevent name conflict in gdb. (get_arm_regname_num_options, set_arm_regname_option, get_arm_regnames): New functions. API to access the several flavor of register names. Note: Used by gdb. (print_insn_thumb): Use the register name entry from the currently selected flavor for LR and PC.
2000-02-10Add support for M340 part.Nick Clifton3-2/+48
2000-02-07Rename parse_disassembler_option (again)Nick Clifton2-5/+11
2000-02-03octets vs bytes changes for binutilsTimothy Wall2-2/+14
2000-01-28Rename parse_disassembler_option to parse_arm_disassembler_option and allow itNick Clifton2-1/+3
to be exported.
2000-01-27Add ATPCS support to ARM disassembler.Nick Clifton3-156/+190
Document ARM disassembler options.
2000-01-27Add support for documenting target specific disassembler optionsNick Clifton2-0/+11
2000-01-27Apply Thoams de Lellis's patch to fic disassembly of Thumb instructions whenNick Clifton2-10/+21
bounded by non-function labels.
2000-01-25Prevent double dumping of raw thumb instructions.Nick Clifton2-3/+7
generated by cgit v1.1 at 2024-12-24 16:29:42 +0000