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For gathers with indices larger than elements (e. g.)
vpgatherqd ymm6{k1}, ZMMWORD PTR [ebp+zmm7*8-123]
We currently treat memory size as a size of index register, while it is
actually should be size of destination register:
vpgatherqd ymm6{k1}, YMMWORD PTR [ebp+zmm7*8-123]
This patch fixes it.
opcodes/
* i386-opc.tbl: Change memory size for vgatherpf0qps, vgatherpf1qps,
vscatterpf0qps, vscatterpf1qps, vgatherqps, vpgatherqd, vpscatterqd,
vscatterqps.
* i386-tbl.h: Regenerate.
gas/testsuite/
* gas/i386/avx512pf-intel.d: Change memory size for vgatherpf0qps,
vgatherpf1qps, vscatterpf0qps, vscatterpf1qps.
* gas/i386/avx512pf.s: Ditto.
* gas/i386/x86-64-avx512pf-intel.d: Ditto.
* gas/i386/x86-64-avx512pf.s: Ditto.
* gas/i386/avx512f-intel.d: Change memory size for vgatherqps,
vpgatherqd, vpscatterqd, vscatterqps.
* gas/i386/avx512f.s: Ditto.
* gas/i386/x86-64-avx512f-intel.d: Ditto.
* gas/i386/x86-64-avx512f.s: Ditto.
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and %hstick_enable to the Sparc assembler.
* config/tc-sparc.c (hpriv_reg_table): Added entries for
%hstick_offset and %hstick_enable.
* doc/c-sparc.texi (Sparc-Regs): Document the %hstick_offset and
%hstick_enable hyperprivileged registers.
* sparc-dis.c (v9_hpriv_reg_names): Names for %hstick_offset and
%hstick_enable added.
* gas/sparc/rdhpr.s: Test rd %hstick_offset and %hstick_enable.
* gas/sparc/rdhpr.d: Likewise.
* gas/sparc/wrhpr.s: Test wr %hstick_offset and %hstick_enable.
* gas/sparc/wrhpr.d: Likewise.
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disassembler's output.
* rx-decode.opc (bwl): Allow for bogus instructions with a size
field of 3.
(sbwl, ubwl, SCALE): Likewise.
* rx-decode.c: Regenerate.
* gas/rx/mov.d: Update expected disassembly.
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Regenerate Makefile.in in bfd, binutils, gas, gold, gprof, ld, opcodes.
Regenerate gas/config.in.
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2014-02-04 Heiher <r@hev.cc>
* elfxx-mips.c (mips_set_isa_flags): Use E_MIPS_ARCH_64R2 for
Loongson-3A.
(mips_mach_extensions): Make bfd_mach_mips_loongson_3a an
extension of bfd_mach_mipsisa64r2.
opcodes/
2014-02-04 Heiher <r@hev.cc>
* mips-dis.c (mips_arch_choices): Usee ISA_MIPS64R2 for Loongson-3A.
gas/
2014-02-04 Heiher <r@hev.cc>
* config/tc-mips.c (mips_cpu_info_table): Use ISA_MIPS64R2 for
Loongson-3A.
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* mips-opc.c (mips_builtin_opcodes): Move the udi* instructions
so that they come after the Loongson extensions.
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binutils/
* README: Add "Copyright Notices" paragraph.
gas/
* config/bfin-lex-wrapper.c: Correct copyright date.
* config/tc-frv.c: Correct copyright punctuation.
* config/tc-ip2k.c: Likewise.
* config/tc-iq2000.c: Likewise.
* config/tc-mep.c: Likewise.
* config/tc-tic4x.c: Likewise.
* config/tc-tic4x.h: Likewise.
ld/testsuite/
* ld-scripts/phdrs2.exp: Correct copyright punctuation.
* ld-v850/v850.exp: Correct copyright typo.
opcodes/
* i386-gen.c (process_copyright): Emit copyright notice on one line.
gold/
* dwp.cc (print_version): Update copyright year to current.
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Cosmetic changes.
* msp430-decode.c: Regenerate.
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* aarch64-tbl.h (aarch64_opcode_table): Replace IMM0 with
FPIMM0 for fcmeq, fcmgt, fcmge, fcmlt and fcmle.
gas/testsuite/
* gas/aarch64/fp-const0-parsing.s: New test.
* gas/aarch64/fp-const0-parsing.d: Likewise.
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* aarch64-opc.c (print_register_offset_address): Call
get_int_reg_name to prepare the register name.
gas/testsuite/
* gas/aarch64/ldst-reg-reg-offset.s: Add tests.
* gas/aarch64/ldst-reg-reg-offset.d: Update.
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We currently support version of vcvtps2ph with sae and only 1 register operand.
This version is encoded as if missing operand was equal to ymm0.
I didn't found any references to this variant in
http://download-software.intel.com/sites/default/files/managed/50/1a/319433-018.pdf
This patch removes it.
opcodes/
* i386-opc.tbl: Remove wrong variant of vcvtps2ph
* i386-tbl.h: Regenerate.
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Latest AVX512 spec
http://download-software.intel.com/sites/default/files/managed/50/1a/319433-018.pdf
Has CPUID PREFETCHWT1 for prefetchwt1 instruction, which we list as AVX512PF.
This patch introduces CPUID PREFETCHWT1.
gas/
* config/tc-i386.c (cpu_arch): Add .prefetchwt1.
* doc/c-i386.texi: Document .prefetchwt1/prefetchwt1.
opcodes/
* i386-gen.c (cpu_flag_init): Add CPU_PREFETCHWT1_FLAGS/
(cpu_flags): Add CpuPREFETCHWT1.
* i386-init.h: Regenerate.
* i386-opc.h (CpuPREFETCHWT1): New.
(i386_cpu_flags): Add cpuprefetchwt1.
* i386-opc.tbl: Cahnge CPU of prefetchwt1 from CpuAVX512PF to CpuPREFETCHWT1.
* i386-tbl.h: Regenerate.
gas/testsuite
* gas/i386/avx512pf-intel.d: Remove prefetchwt1.
* gas/i386/avx512pf.s: Ditto.
* gas/i386/avx512pf.d: Ditto.
* gas/i386/x86-64-avx512pf-intel.d: Ditto.
* gas/i386/x86-64-avx512pf.s: Ditto.
* gas/i386/x86-64-avx512pf.d: Ditto.
* gas/i386/prefetchwt1-intel.d: New file.
* gas/i386/prefetchwt1.s: Ditto.
* gas/i386/prefetchwt1.d: Ditto.
* gas/i386/x86-64-prefetchwt1-intel.d: Ditto.
* gas/i386/x86-64-prefetchwt1.s: Ditto.
* gas/i386/x86-64-prefetchwt1.d: Ditto.
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In latest release of AVX512 spec
http://download-software.intel.com/sites/default/files/managed/50/1a/319433-018.pdf
Vptestnmq and vptestnmq instructions have CPUID AVX512F, not AVX512CD.
This patch fixes it.
opcodes/
* i386-opc.tbl: Change CPU of vptestnmq, vptestnmd from CpuAVX512CD,
to CpuAVX512F.
* i386-tbl.h: Regenerate.
gas/testsuite/
* gas/i386/avx512cd-intel.d: Remove vptestnmq, vptestnmd.
* gas/i386/avx512cd.s: Ditto.
* gas/i386/avx512cd.d: Ditto.
* gas/i386/x86-64-avx512cd-intel.d: Ditto.
* gas/i386/x86-64-avx512cd.s: Ditto.
* gas/i386/x86-64-avx512cd.d: Ditto.
* gas/i386/avx512f-intel.d: Add vptestnmq, vptestnmd.
* gas/i386/avx512f.s: Ditto.
* gas/i386/avx512f.d: Ditto.
* gas/i386/x86-64-avx512f-intel.d: Ditto.
* gas/i386/x86-64-avx512f.s: Ditto.
* gas/i386/x86-64-avx512f.d: Ditto.
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* i386-gen.c (output_cpu_flags): Don't output trailing space.
(output_opcode_modifier): Likewise.
(output_operand_type): Likewise.
* i386-init.h: Regenerated.
* i386-tbl.h: Likewise.
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gas/
2014-02-12 Ilya Tocar <ilya.tocar@intel.com>
* config/tc-i386.c (cpu_arch): Add .clflushopt, .xsavec, .xsaves.
* doc/c-i386.texi: Document .xsavec/xsavec/.xsaves/xsaves/
clflushopt/.clfushopt.
gas/testsuite/
2014-02-12 Ilya Tocar <ilya.tocar@intel.com>
* gas/i386/clflushopt-intel.d: New.
* gas/i386/clflushopt.d: Ditto.
* gas/i386/clflushopt.s: Ditto.
* gas/i386/i386.exp: Run new tests.
* gas/i386/x86-64-clflushopt-intel.d: New.
* gas/i386/x86-64-clflushopt.d: Ditto.
* gas/i386/x86-64-clflushopt.s: Ditto.
* gas/i386/x86-64-xsavec-intel.d: Ditto.
* gas/i386/x86-64-xsavec.d: Ditto.
* gas/i386/x86-64-xsavec.s: Ditto.
* gas/i386/x86-64-xsaves-intel.d: Ditto.
* gas/i386/x86-64-xsaves.d: Ditto.
* gas/i386/x86-64-xsaves.s: Ditto.
* gas/i386/xsavec-intel.d: Ditto.
* gas/i386/xsavec.d: Ditto.
* gas/i386/xsavec.s: Ditto.
* gas/i386/xsaves-intel.d: Ditto.
* gas/i386/xsaves.d: Ditto.
* gas/i386/xsaves.s: Ditto.
opcodes/
2014-02-12 Ilya Tocar <ilya.tocar@intel.com>
* i386-dis.c (MOD enum): Add MOD_0FC7_REG_3, MOD_0FC7_REG_4,
MOD_0FC7_REG_5.
(PREFIX enum): Add PREFIX_0FAE_REG_7.
(reg_table): Add MOD_0FC7_REG_3, MOD_0FC7_REG_4 MOD_0FC7_REG_5.
(prefix_table): Add clflusopt.
(mod_table): Add xrstors, xsavec, xsaves.
* i386-gen.c (cpu_flag_init): Add CPU_CLFLUSHOPT_FLAGS,
CPU_XSAVES_FLAGS, CPU_XSAVEC_FLAGS.
(cpu_flags): Add CpuClflushOpt, CpuXSAVES, CpuXSAVEC.
* i386-init.h: Regenerate.
* i386-opc.tbl: Add clflushopt, xrstors, xrstors64, xsaves,
xsaves64, xsavec, xsavec64.
* i386-tbl.h: Regenerate.
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Adds nds32 files to POTFILES.in
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opcodes/
2014-01-30 Michael Zolotukhin <michael.v.zolotukhin@gmail.com>
Jan Beulich <jbeulich@suse.com>
PR binutils/16490
* i386-dis.c (OP_E_memory): Fix shift computation for
vex_vsib_q_w_dq_mode.
gas/testsuite/
2014-01-30 Michael Zolotukhin <michael.v.zolotukhin@gmail.com>
Jan Beulich <jbeulich@suse.com>
PR binutils/16490
* gas/i386/avx512f.d: Fix test output.
* gas/i386/avx512f-intel.d: Likewise.
* gas/i386/x86-64-avx512f.d: Likewise.
* gas/i386/x86-64-avx512f-intel.d: Likewise.
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opcodes/
* i386-dis.c (print_insn): Do not touch all_prefixes[-1] when
last_rex_prefix is -1.
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binutils/
* version.c (print_version): Update copyright year to 2014.
gas/
* as.c (parse_args): Update copyright year to 2014.
gold/
* version.cc (print_version): Update copyright year to 2014.
ld/
* ldver.c (ldversion): Update copyright year to 2014.
opcodes/
* i386-gen.c (process_copyright): Update copyright year to 2014.
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Add two more as test files for user special and system register.
Fix typo.
2013-12-17 Kuan-Lin Chen <kuanlinchentw@gmail.com>
* gas/nds32/nds32.exp: Add system and user special register tests.
* gas/nds32/sys-reg.s: New test.
* gas/nds32/sys-reg.d: Likewise.
* gas/nds32/usr-spe-reg.s: Likewise.
* gas/nds32/usr-spe-reg.d: Likewise.
* gas/nds32/alu-2.d: Delete the new blank line at EOF.
* gas/nds32/br-1.d: Likewise.
* gas/nds32/br-2.d: Likewise.
* gas/nds32/ji-jr.d: Likewise.
* gas/nds32/lsi.d: Likewise.
* nds32-dis.c (sr_map): Add system register table for disassembling.
(usr_map): Fix typo.
* nds32-asm.c (keyword_sr): Add embedded debug registers.
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gas/testsuite/
2013-12-17 Michael Zolotukhin <michael.v.zolotukhin@gmail.com>
* gas/i386/disassem.s: New.
* gas/i386/disassem.d: Likewise.
* gas/i386/x86-64-disassem.s: Likewise.
* gas/i386/x86-64-disassem.d: Likewise.
* gas/i386/i386.exp: Run disassem and x86-64-disassem.
opcodes/
2013-12-17 Michael Zolotukhin <michael.v.zolotukhin@gmail.com>
* i386-dis.c (MOD_FF_REG_3): New.
(MOD_FF_REG_5): Likewise.
(mod_table): Add MOD_FF_REG_3 and MOD_FF_REG_5.
(reg_table): Use MOD_FF_REG_3 and MOD_FF_REG_5.
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2013-12-16 Andrew Bennett <andrew.bennett@imgtec.com>
gas/testsuite/gas/mips/
* mips.exp: Add CP1 register name tests.
* cp1-names-mips32.d: New test.
* cp1-names-mips32r2.d: New test.
* cp1-names-mips64.d: New test.
* cp1-names-mips64r2.d: New test.
* cp1-names-numeric.d: New test.
* cp1-names-r3000.d: New test.
* cp1-names-r4000.d: New test.
* cp1-names-sb1.d: New test.
* cp1-names.s: New test.
* micromips-insn32.d: Add the correct symbolic names for the CP1
registers.
* micromips-noinsn32.d: Likewise.
* micromips-trap.d: Likewise.
* micromips.d: Likewise.
opcodes/
* mips-dis.c: Add mips_cp1_names pointer.
(mips_cp1_names_numeric): New array.
(mips_cp1_names_mips3264): New array.
(mips_arch_choice): Add cp1_names.
(mips_arch_choices): Add relevant cp1 register name array to each of
the elements.
(set_default_mips_dis_options): Add support for setting up the
mips_cp1_names pointer.
(parse_mips_dis_option): Add support for the cp1-names command line
variable. Also setup the mips_cp1_names pointer.
(print_reg): Print out name of the cp1 register.
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The element index range for the following MIPS MSA instructions: sldi, splati,
copy_s, copy_u, insert and insve is 1 bit too large. This patch fixes this issue.
ChangeLog:
gas/testsuite/gas/mips/
* msa.s: Reduced maximum element index range for sldi, splati,
copy_s, copy_u, insert and insve instructions.
* msa64.s: Likewise.
* micromips@msa.d: Likewise.
* micromips@msa64.d: Likewise.
* msa.d: Likewise.
* msa64.d: Likewise.
include/opcode/
* mips.h: Updated description of +o, +u, +v and +w for MIPS and
microMIPS.
opcodes/
* micromips-opc.c (decode_micromips_operand): Reduced range of +o, +u,
+v and +w.
(micromips_opcodes): Reduced element index range for sldi, splati,
copy_s, copy_u, insert and insve instructions.
* opcodes/mips-opc.c (decode_mips_operand): Reduced range of +o, +u,
+v and +w.
(mips_builtin_opcodes): Reduced element index range for sldi, splati,
copy_s, copy_u, insert and insve instructions.
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* nds32-dis.c (mnemonic_96): Fix typo.
[BR]: https://sourceware.org/ml/binutils/2013-12/msg00184.html
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BFD:
* Makefile.am (BFD32_BACKENDS, BFD32_BACKENDS_CFILES): Add nds32
files.
* Makefile.in: Regenerate.
* archures.c (bfd_nds32_arch): Add nds32 target.
* bfd-in2.h: Regenerate.
* config.bfd (nds32*le-*-linux): Add bfd_elf32_nds32lelin_vec
and bfd_elf32_nds32belin_vec.
(nds32*be-*-linux*): Likewise.
(nds32*le-*-*): Add bfd_elf32_nds32le_vec and bfd_elf32_nds32be_vec.
(nds32*be-*-*): Likewise.
* configure.in (bfd_elf32_nds32be_vec): Add elf32-nds32.lo.
(bfd_elf32_nds32le_vec): Likewise.
(bfd_elf32_nds32belin_vec): Likewise.
(bfd_elf32_nds32lelin_vec): Likewise.
* configure: Regenerate.
* cpu-nds32.c: New file for nds32.
* elf-bfd.h: Add NDS32_ELF_DATA.
* elf32-nds32.c: New file for nds32.
* elf32-nds32.h: New file for nds32.
* libbfd.h: Regenerate.
* reloc.c: Add relocations for nds32.
* targets.c (bfd_elf32_nds32be_vec): New declaration for nds32.
(bfd_elf32_nds32le_vec): Likewise.
(bfd_elf32_nds32belin_vec): Likewise.
(bfd_elf32_nds32lelin_vec): Likewise.
BINUTILS:
* readelf.c: Include elf/nds32.h
(guess_is_rela): Add case for EM_NDS32.
(dump_relocations): Add case for EM_NDS32.
(decode_NDS32_machine_flags): New.
(get_machine_flags): Add case for EM_NDS32.
(is_32bit_abs_reloc): Likewise.
(is_16bit_abs_reloc): Likewise.
(process_nds32_specific): New.
(process_arch_specific): Add case for EM_NDS32.
* NEWS: Announce Andes nds32 support.
* MAINTAINERS: Add nds32 maintainers.
TESTSUITE:
* binutils-all/objdump.exp: Add NDS32 cpu.
* binutils-all/readelf.r: Skip extra reloc created by NDS32.
GAS:
* Makefile.am (TARGET_CPU_CFILES): Add config/tc-nds32.c.
(TARGET_CPU_HFILES): Add config/tc-nds32.h.
* Makefile.in: Regenerate.
* configure.in (nds32): Add nds32 target extension config support.
* configure.tgt : Add case for nds32-*-elf* and nds32-*-linux*.
* configure: Regenerate.
* config/tc-nds32.c: New file for nds32.
* config/tc-nds32.h: New file for nds32.
* doc/Makefile.am (CPU_DOCS): Add c-nds32.texi.
* doc/Makefile.in: Regenerate.
* doc/as.texinfo: Add nds32 options.
* doc/all.texi: Set NDS32.
* doc/c-nds32.texi: New file dor nds32 document.
* NEWS: Announce Andes nds32 support.
TESTSUITE:
* gas/all/gas.exp: Add expected failures for NDS32.
* gas/elf/elf.exp: Likewise.
* gas/lns/lns.exp: Use alternate test.
* gas/macros/irp.d: Skip for NDS32.
* gas/macros/macros.exp: Skip some tests for the NDS32.
* gas/macros/rept.d: Skip for NDS32.
* gas/macros/test3.d: Skip for NDS32.
* gas/nds32: New directory.
* gas/nds32/alu-1.s: New test.
* gas/nds32/alu-1.d: Likewise.
* gas/nds32/alu-2.s: Likewise.
* gas/nds32/alu-2.d: Likewise.
* gas/nds32/br-1.d: Likewise.
* gas/nds32/br-1.s: Likewise.
* gas/nds32/br-2.d: Likewise.
* gas/nds32/br-2.s: Likewise.
* gas/nds32/ji-jr.d: Likewise.
* gas/nds32/ji-jr.s: Likewise.
* gas/nds32/ls.d: Likewise.
* gas/nds32/ls.s: Likewise.
* gas/nds32/lsi.d: Likewise.
* gas/nds32/lsi.s: Likewise.
* gas/nds32/to-16bit-v1.d: Likewise.
* gas/nds32/to-16bit-v1.s: Likewise.
* gas/nds32/to-16bit-v2.d: Likewise.
* gas/nds32/to-16bit-v2.s: Likewise.
* gas/nds32/to-16bit-v3.d: Likewise.
* gas/nds32/to-16bit-v3.s: Likewise.
* gas/nds32/nds32.exp: New test driver.
LD:
* Makefile.am (ALL_EMULATION_SOURCES): Add nds32 target.
* Makefile.in: Regenerate.
* configure.tgt: Add case for nds32*le-*-elf*, nds32*be-*-elf*,
nds32*le-*-linux-gnu*, and nds32*be-*-linux-gnu*.
* emulparams/nds32belf.sh: New file for nds32.
* emulparams/nds32belf_linux.sh: Likewise.
* emulparams/nds32belf16m.sh: Likewise.
* emulparams/nds32elf.sh: Likewise.
* emulparams/nds32elf_linux.sh: Likewise.
* emulparams/nds32elf16m.sh: Likewise.
* emultempl/nds32elf.em: Likewise.
* scripttempl/nds32elf.sc}: Likewise.
* gen-doc.texi: Set NDS32.
* ld.texinfo: Set NDS32.
* NEWS: Announce Andes nds32 support.
TESTSUITE:
* lib/ld-lib.exp: Add NDS32 to list of targets that do not support
shared library generation.
* ld-nds32: New directory.
* ld-nds32/branch.d: New test.
* ld-nds32/branch.ld: New test.
* ld-nds32/branch.s: New test.
* ld-nds32/diff.d: New test.
* ld-nds32/diff.ld: New test.
* ld-nds32/diff.s: New test.
* ld-nds32/gp.d: New test.
* ld-nds32/gp.ld: New test.
* ld-nds32/gp.s: New test.
* ld-nds32/imm.d: New test.
* ld-nds32/imm.ld: New test.
* ld-nds32/imm.s: New test.
* ld-nds32/imm_symbol.s: New test.
* ld-nds32/relax_jmp.d: New test.
* ld-nds32/relax_jmp.ld: New test.
* ld-nds32/relax_jmp.s: New test.
* ld-nds32/relax_load_store.d: New test.
* ld-nds32/relax_load_store.ld: New test.
* ld-nds32/relax_load_store.s: New test.
* ld-nds32/nds32.exp: New file.
OPCODES:
* Makefile.am (TARGET_LIBOPCODES_CFILES): Add nds32-asm.c
and nds32-dis.c.
* Makefile.in: Regenerate.
* configure.in: Add case for bfd_nds32_arch.
* configure: Regenerate.
* disassemble.c (ARCH_nds32): Define.
* nds32-asm.c: New file for nds32.
* nds32-asm.h: New file for nds32.
* nds32-dis.c: New file for nds32.
* nds32-opc.h: New file for nds32.
INCLUDE:
* dis-asm.h (print_insn_nds32): Add nds32 target.
* elf/nds32.h: New file for nds32.
* opcode/nds32.h: New file for nds32.
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that compiling with -Werror=format-security does not produce an
error.
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* gas/aarch64/msr.s: Add tests.
* gas/aarch64/msr.d: Update.
include/opcode
* aarch64.h (aarch64_pstatefields): Change element type to
aarch64_sys_reg.
opcodes/
* aarch64-opc.c (aarch64_pstatefields): Update.
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* micromips-opc.c (LM): Define.
(micromips_opcodes): Add LM to load instructions.
* mips-opc.c (prefe): Add LM attribute.
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This reverts commit 75468c93c14e9f14dd9020712538c5303a455876.
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* config/tc-aarch64.c (set_other_error): New function.
(parse_sys_reg): Add new parameter 'sys_reg' and if non-NULL set
the variable to which it points with 'o'.
(parse_operands): Update; check for write to read-only system
registers or read from write-only ones.
gas/testsuite/
* gas/aarch64/diagnostic.s: Add tests.
* gas/aarch64/diagnostic.l: Update.
* gas/aarch64/tracereg-illegal.d: New file.
* gas/aarch64/tracereg-illegal.l: Ditto.
* gas/aarch64/tracereg-illegal.s: Ditto.
* gas/aarch64/tracereg.d: Ditto.
* gas/aarch64/tracereg.s: Ditto.
include/opcode
* aarch64.h (aarch64_sys_reg_readonly_p): New declaration.
(aarch64_sys_reg_writeonly_p): Ditto.
opcodes/
* aarch64-opc.c (CPENT): New define.
(F_READONLY, F_WRITEONLY): Likewise.
(aarch64_sys_regs): Add trace unit registers.
(aarch64_sys_reg_readonly_p): New function.
(aarch64_sys_reg_writeonly_p): Ditto.
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* mips-opc.c (mips_builtin_opcodes): Add RD_2 to "mfcr" and
"mtcr".
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gas/
* config/mips/tc-mips.c (convert_reg_type): Use
INSN_LOAD_MEMORY instead of INSN_LOAD_MEMORY_DELAY.
(reg_needs_delay): Likewise.
(insns_between): Likewise.
include/
* opcode/mips.h (INSN_LOAD_MEMORY_DELAY): Rename to...
(INSN_LOAD_MEMORY): ...this.
opcodes/
* mips-dis.c (print_insn_mips): Use
INSN_LOAD_MEMORY instead of INSN_LOAD_MEMORY_DELAY.
(print_insn_micromips): Likewise.
* mips-opc.c (LDD): Remove.
(CLD): Include INSN_LOAD_MEMORY.
(LM): New.
(mips_builtin_opcodes): Use LM instead of LDD.
Add LM to load instructions.
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PR gas/16140
* i386-gen.c (cpu_flag_init): Remove CpuNop from CPU_K6_2_FLAGS.
* i386-init.h: Regenerated.
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* config/tc-aarch64.c (parse_sys_reg): Update to use aarch64_sys_reg;
call aarch64_sys_reg_deprecated_p and warn about the deprecated
system registers.
gas/testsuite/
* gas/aarch64/deprecated.d: New file.
* gas/aarch64/deprecated.l: New file.
* gas/aarch64/deprecated.s: New file.
* gas/aarch64/sysreg-1.s: Add tests.
* gas/aarch64/sysreg-1.d: Add tests.
include/opcode/
* aarch64.h (aarch64_sys_reg): New typedef.
(aarch64_sys_regs): Change to define with the new type.
(aarch64_sys_reg_deprecated_p): Declare.
opcodes/
* aarch64-opc.c (F_DEPRECATED): New macro.
(aarch64_sys_regs): Update; flag "spsr_svc" and "spsr_hyp" with
F_DEPRECATED.
(aarch64_print_operand): Call aarch64_sys_reg_deprecated_p on
AARCH64_OPND_SYSREG.
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* config/tc-aarch64.c (parse_operands): Handle AARCH64_OPND_COND1.
gas/testsuite/
* gas/aarch64/alias.s: Add tests.
* gas/aarch64/alias.d: Update.
* gas/aarch64/no-aliases.d: Update.
* gas/aarch64/diagnostic.s: Add tests.
* gas/aarch64/diagnostic.l: Update.
* gas/aarch64/illegal.s: Add tests.
* gas/aarch64/illegal.l: Update.
include/opcode/
* aarch64.h (enum aarch64_operand_class): Add AARCH64_OPND_CLASS_COND.
(enum aarch64_opnd): Add AARCH64_OPND_COND1.
opcodes/
* aarch64-dis.c (convert_ubfm_to_lsl): Check for cond != '111x'.
(convert_from_csel): Likewise.
* aarch64-opc.c (operand_general_constraint_met_p): Handle
AARCH64_OPND_CLASS_COND and AARCH64_OPND_COND1.
(aarch64_print_operand): Handle AARCH64_OPND_COND1.
* aarch64-tbl.h (aarch64_opcode_table): Use COND1 instead of
COND for cinc, cset, cinv, csetm and cneg.
(AARCH64_OPERANDS): Add entry for AARCH64_OPND_COND1.
* aarch64-asm-2.c: Re-generated.
* aarch64-dis-2.c: Ditto.
* aarch64-opc-2.c: Ditto.
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* aarch64-opc.c (set_syntax_error): New function.
(operand_general_constraint_met_p): Replace set_other_error
with set_syntax_error.
gas/testsuite/
* gas/aarch64/diagnostic.s: Add tests of ldp/stp.
* gas/aarch64/diagnostic.l: Update.
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Currently the disassembler for s390 (by default) assumes that a 31-bit
binary was compiled in "ESA" mode -- and then only disassembles a
limited opcode set. The change upgrades the default to the full "zarch"
opcode set even for 31-bit binaries.
opcodes/
* s390-dis.c (init_disasm): Default to full 'zarch' opcode
availability even for 31-bit programs.
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opcodes/
2013-10-15 Ramana Radhakrishnan <ramana.radhakrishnan@arm.com>
* arm-dis.c (neon_opcodes): Adjust print string for vshll.
gas/testsuite/
2013-10-15 Ramana Radhakrishnan <ramana.radhakrishnan@arm.com>
* gas/arm/neon-cov.d: Adjust output.
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* micromips-opc.c (decode_micromips_operand): Add +T, +U, +V, +W,
+d, +e, +h, +k, +l, +n, +o, +u, +v, +w, +x,
+~, +!, +@, +#, +$, +%, +^, +&, +*, +|.
(MSA): New define.
(MSA64): New define.
(micromips_opcodes): Add MSA instructions.
* mips-dis.c (msa_control_names): New array.
(mips_abi_choice): Add ASE_MSA to mips32r2.
Remove ASE_MDMX from mips64r2.
Add ASE_MSA and ASE_MSA64 to mips64r2.
(parse_mips_dis_option): Handle -Mmsa.
(print_reg): Handle cases for OP_REG_MSA and OP_REG_MSA_CTRL.
(print_insn_arg): Handle cases for OP_IMM_INDEX and OP_REG_INDEX.
(print_mips_disassembler_options): Print -Mmsa.
* mips-opc.c (decode_mips_operand): Add +T, +U, +V, +W, +d, +e, +h, +k,
+l, +n, +o, +u, +v, +w, +~, +!, +@, +#, +$, +%, +^, +&, +*, +|.
(MSA): New define.
(MSA64): New define.
(mips_builtin_op): Add MSA instructions.
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opcodes/
* nios2-opc.c (nios2_builtin_reg): Use "sstatus" rather than "ba"
as the primary name of r30.
gas/
* config/tc-nios2.c (nios2_consume_arg): Make the "ba" warning
also test/refer to "sstatus". Reformat the warning message.
gas/testsuite/
* gas/nios2/warn_nobreak.l: Update text of warning messages.
* gas/nios2/registers.s: Use "sstatus" rather than "ba"
as the primary name of r30.
* gas/nios2/registers.d: Likewise.
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gas/testsuite/
* gas/i386/mpx.s: Remove bndcl/bndcu/bndcn tests with AX.
* gas/i386/x86-64-mpx.s: Likwise.
* gas/i386/mpx.d: Updated.
* gas/i386/x86-64-mpx.d: Likewise.
opcodes/
* i386-dis.c (intel_operand_size): Move v_bnd_mode alongside the
default case.
(OP_E_register): Move v_bnd_mode alongside m_mode.
* i386-opc.tbl (bndcl, bndcu, bndcn): Split 32- and 64-bit variants.
Drop Reg16 and Disp16. Add NoRex64.
(bndmk, bndmov, bndldx, bndstx): Drop Disp16.
* i386-tbl.h: Re-generate.
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refactored assembler/disassember accordingly.
Testsuite checkout OK.
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* i386-dis.c (oappend_maybe_intel): New function.
(OP_ST, OP_STi, append_seg, OP_I, OP_I64, OP_sI, OP_ESreg): Use it.
(OP_C, OP_T, CMP_Fixup, OP_EX_VexImmW): Likewise.
(VCMP_Fixup, VPCMP_Fixup, PCLMUL_Fixup): Likewise.
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* cr16-opc.c (REG): Cast NAME to 'reg' enum type to suppress
possible compiler warnings when the union's initializer is
actually meant for the 'preg' enum typed member.
* crx-opc.c (REG): Likewise.
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