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2017-02-15Add SFENCE.VMA instructionAndrew Waterman2-0/+8
include/ChangeLog: 2017-02-14 Andrew Waterman <andrew@sifive.com> * opcode/riscv-opc.h (MATCH_SFENCE_VMA): New define. (MASK_SFENCE_VMA): Likewise. (sfence_vma): Declare instruction. opcodes/ChangeLog: 2017-02-14 Andrew Waterman <andrew@sifive.com> * riscv-opc.c (riscv_opcodes): Add sfence.vma instruction and pseudoinstructions.
2017-02-15[AArch64] Add SVE system registersRichard Sandiford2-0/+21
This patch adds the SVE-specific system registers. opcodes/ * aarch64-opc.c (aarch64_sys_regs): Add SVE registers. (aarch64_sys_reg_supported_p): Handle them. gas/ * testsuite/gas/aarch64/sve-sysreg.s, testsuite/gas/aarch64/sve-sysreg.d, testsuite/gas/aarch64/sve-sysreg-invalid.d, testsuite/gas/aarch64/sve-sysreg-invalid.l: New tests.
2017-02-15[ARC] Fix assembler relaxation.Claudiu Zissulescu2-34/+75
Fix assembler relaxation step for add, ld, mov, mpy and sub instructions. Add tests to it. gas/ 2017-02-15 Claudiu Zissulescu <claziss@synopsys.com> * config/tc-arc.c (md_convert_frag): Remove @pcl relocation information from input expression. (assemble_insn): Make sure pcrel is correctly set. (arc_pcrel_adjust): Compensate for PCL rounding. * testsuite/gas/arc/relax-add01.d: New file. * testsuite/gas/arc/relax-add01.s: Likewise. * testsuite/gas/arc/relax-add02.d: Likewise. * testsuite/gas/arc/relax-add02.s: Likewise. * testsuite/gas/arc/relax-add03.d: Likewise. * testsuite/gas/arc/relax-add03.s: Likewise. * testsuite/gas/arc/relax-add04.d: Likewise. * testsuite/gas/arc/relax-add04.s: Likewise. * testsuite/gas/arc/relax-ld01.d: Likewise. * testsuite/gas/arc/relax-ld01.s: Likewise. * testsuite/gas/arc/relax-ld02.d: Likewise. * testsuite/gas/arc/relax-ld02.s: Likewise. * testsuite/gas/arc/relax-mov01.d: Likewise. * testsuite/gas/arc/relax-mov01.s: Likewise. * testsuite/gas/arc/relax-mov02.d: Likewise. * testsuite/gas/arc/relax-mov02.s: Likewise. * testsuite/gas/arc/relax-mpy01.d: Likewise. * testsuite/gas/arc/relax-mpy01.s: Likewise. * testsuite/gas/arc/relax-sub01.d: Likewise. * testsuite/gas/arc/relax-sub01.s: Likewise. * testsuite/gas/arc/relax-sub02.d: Likewise. * testsuite/gas/arc/relax-sub02.s: Likewise. * testsuite/gas/arc/relax-sub03.d: Likewise. * testsuite/gas/arc/relax-sub03.s: Likewise. * testsuite/gas/arc/relax-sub04.d: Likewise. * testsuite/gas/arc/relax-sub04.s: Likewise. opcodes/ 2017-02-15 Claudiu Zissulescu <claziss@synopsys.com> * arc-opc.c (UIMM6_20R): Define. (SIMM12_20): Use above. (SIMM12_20R): Define. (SIMM3_5_S): Use above. (UIMM7_A32_11R_S): Define. (UIMM7_9_S): Use above. (UIMM3_13R_S): Define. (SIMM11_A32_7_S): Use above. (SIMM9_8R): Define. (UIMM10_A32_8_S): Use above. (UIMM8_8R_S): Define. (W6): Use above. (arc_relax_opcodes): Use all above defines.
2017-02-15Distinguish some of the registers different on ARC700 and HS38 cpusVineet Gupta2-12/+41
opcodes * arc-regs.h: Distinguish some of the registers different on ARC700 and HS38 cpus. gas * testsuite/gas/arc/st.d: Update for 0xe having a name now
2017-02-14PowerPC register expression checksAlan Modra2-5/+11
This stops powerpc gas blithely accepting such nonsense as "addi %f4,%cr3,%r31". PR 21118 gas/ * NEWS: Mention powerpc register checks. * config/tc-ppc.c (struct pd_reg): Make value a short. Add flags. (pre_defined_registers): Delete fpscr and pmr entries. Set register type in flags. (cr_names): Set type in flags. (reg_name_search): Return pointer to struct pd_reg rather than value. (register_name): Adjust to suit. Set X_md from flags. (ppc_parse_name): Likewise. (ppc_optimize_expr): New function. (md_assemble): Verify expresion reg flags match operand. * config/tc-ppc.h (md_optimize_expr): Define. (ppc_optimize_expr): Declare. include/ * opcode/ppc.h (PPC_OPERAND_*): Reassign values, regs first. (PPC_OPERAND_SPR, PPC_OPERAND_GQR): Define. opcodes/ * ppc-opc.c (powerpc_operands): Flag SPR, SPRG and TBR entries with PPC_OPERAND_SPR. Flag PSQ and PSQM with PPC_OPERAND_GQR.
2017-02-11Fix use after free in cgen instruction lookupAlan Modra2-15/+20
* cgen-opc.c (cgen_lookup_insn): Delete buf and base_insn temps. Use insn_bytes_value and insn_int_value directly instead. Don't free allocated memory until function exit.
2017-02-10POWER9 add scv/rfscv instruction supportNicholas Piggin2-1/+7
opcodes/ * ppc-opc.c (powerpc_opcodes) <scv, rfscv>: New mnemonics. gas/ * testsuite/gas/ppc/power9.d <scv, rfscv>: New tests.
2017-02-06[ARC] Provide an interface to decode ARC instructions.Claudiu Zissulescu4-363/+609
gas/ 2017-02-06 Claudiu Zissulescu <claziss@synopsys.com> * config/tc-arc.c (parse_opcode_flags): Ignore implicit flags. include/ 2017-02-06 Claudiu Zissulescu <claziss@synopsys.com> Anton Kolesov <anton.kolesov@synopsys.com> * opcode/arc.h (insn_class_t): Add ENTER, LEAVE, POP, PUSH, BBIT0, BBIT1, BI, BIH, BRCC, EI, JLI, and SUB instruction classes. (flag_class_t): Add F_CLASS_WB, F_CLASS_ZZ, and F_CLASS_IMPLICIT flag classes. opcode/ 2017-02-06 Claudiu Zissulescu <claziss@synopsys.com> Anton Kolesov <anton.kolesov@synopsys.com> * arc-dis.c (arc_disassemble_info): New structure. (init_arc_disasm_info): New function. (find_format_from_table): Ignore implicit flags. (find_format): Update dissassembler private data. (print_flags): Likewise. (print_insn_arc): Likewise. (arc_opcode_to_insn_type): Consider the new added instruction classes. (arcAnalyzeInstr): Remove. (arc_insn_decode): New function. * arc-dis.h (arc_ldst_writeback_mode): New enum. (arc_ldst_data_size): Likewise. (arc_condition_code): Likewise. (arc_operand_kind): Likewise. (arc_insn_kind): New struct. (arc_instruction): Likewise. (arc_insn_decode): Declare function. (ARC_Debugger_OperandType): Deleted. (Flow): Likewise. (NullifyMode): Likewise. (allOperandsSize): Likewise. (arcDisState): Likewise. (arcAnalyzeInstr): Likewise. * arc-dis.c (arc_opcode_to_insn_type): Handle newly introduced insn_class_t enums. * arc-opc.c (F_SIZED): New define. (C_CC_EQ, C_CC_GE, C_CC_GT, C_CC_HI, C_CC_HS): Likewise. (C_CC_LE, C_CC_LO, C_CC_LS, C_CC_LT, C_CC_NE): Likewise. (C_CC_NE, C_AA_AB, C_AA_AW, C_ZZ_D, C_ZZ_H, C_ZZ_B): Likewise. (arc_flag_classes): Add F_CLASS_COND/F_CLASS_IMPLICIT flags. * opcodes/arc-tbl.h: Update instructions to include new F_CLASS_IMPLICIT flags. (bbit0, lp): Change class. (bbit1, bi, bih, br*, ei_s, jli_s): Likewsie
2017-02-03Fix compile time warning messages when compiling binutils with gcc 7.0.1.Nick Clifton3-5/+16
PR 21096 bfd * coffcode.h (coff_write_object_contents): Enlarge size of s_name_buf in order to avoid compile time warning about possible integer truncation. * elf32-nds32.c (nds32_elf_ex9_import_table): Mask off lower 32-bits of insn value before printing into buffer. opcodes * aarch64-opc.c (print_register_list): Ensure that the register list index will fir into the tb buffer. (print_register_offset_address): Likewise. * tic6x-dis.c (print_insn_tic6x): Increase size of func_unit_buf.
2017-01-27Fix disassembling of TIC6X parallel instructions where the previous fetch ↵Alexis Deruell2-2/+18
packet ended with a 32-bit insn. PR 21056 opcodes * tic6x-dis.c (print_insn_tic6x): Correct displaying of parallel instructions when the previous fetch packet ends with a 32-bit instruction. gas * testsuite/gas/tic6x/insns16-parallel.s: New test case. * testsuite/gas/tic6x/insns16-parallel.d: New test driver.
2017-01-25Clarify that include/opcode/ files are part of GNU opcodesDimitar Dimitrov2-2/+5
include/ChangeLog: 2017-01-25 Dimitar Dimitrov <dimitar@dinux.eu> * opcode/hppa.h: Clarify that file is part of GNU opcodes. * opcode/i860.h: Ditto. * opcode/nios2.h: Ditto. * opcode/nios2r1.h: Ditto. * opcode/nios2r2.h: Ditto. * opcode/pru.h: Ditto. opcodes/ChangeLog: 2017-01-25 Dimitar Dimitrov <dimitar@dinux.eu> * pru-opc.c: Remove vague reference to a future GDB port.
2017-01-20Updated Irish translation for the opcodes library.Nick Clifton2-458/+813
* po/ga.po: Updated Irish translation.
2017-01-18[ARM] Fix the decoding of indexed element VCMLA instructionSzabolcs Nagy2-4/+8
Bit 24 of the indexed element vcmla decode mask was incorrectly left unset. This could cause incorrect disassembly of some currently undefined instructions as vcmla. Rotatation immediates were not printed correctly in the disassembly (could print 170 and 280 instead of 180 and 270). opcodes/ * arm-dis.c (coprocessor_opcodes): Fix vcmla mask and disassembly. gas/ * testsuite/gas/arm/armv8_3-a-simd.s: Add vcmla tests. * testsuite/gas/arm/armv8_3-a-simd.d: Update.
2017-01-13Return -1 on memory error in print_insn_m68kYao Qi2-7/+19
m68k-dis.c:print_insn_m68k doesn't return -1 on memory error, but GDB expects it returning -1 on memory error. opcodes: 2017-01-13 Yao Qi <yao.qi@linaro.org> * m68k-dis.c (match_insn_m68k): Extend comments. Return -1 if FETCH_DATA returns 0. (m68k_scan_mask): Likewise. (print_insn_m68k): Update code to handle -1 return value.
2017-01-13Remove magic numbers in m68k-dis.c:print_insn_argYao Qi2-41/+72
When I inspect the return values of disassmblers, I happen to see various -1/-2/-3 magic numbers are used in m68k-dis.c. This patch is to replace them with enum. -1 and -2 is "clearly documented" in print_ins_arg's comments, but -3 isn't. In fact, -3 is returned when FETCH_DATA returns false, which means memory error (because fetch_data return 0 on memory error). So I name enum PRINT_INSN_ARG_MEMORY_ERROR for -3. This patch is a refactor patch, doesn't affect any functionality. opcodes: 2017-01-13 Yao Qi <yao.qi@linaro.org> * m68k-dis.c (enum print_insn_arg_error): New. (NEXTBYTE): Replace -3 with PRINT_INSN_ARG_MEMORY_ERROR. (NEXTULONG): Likewise. (NEXTSINGLE): Likewise. (NEXTDOUBLE): Likewise. (NEXTDOUBLE): Likewise. (NEXTPACKED): Likewise. (FETCH_ARG): Likewise. (FETCH_DATA): Update comments. (print_insn_arg): Update comments. Replace magic numbers with enum. (match_insn_m68k): Likewise.
2017-01-12Enable Intel AVX512_VPOPCNTDQ instructionsIgor Tsimbalist8-5344/+5432
gas/ 2017-01-12 Igor Tsimbalist <igor.v.tsimbalist@intel.com> * config/tc-i386.c (cpu_arch): Add .avx512_vpopcntdq. (cpu_noarch): Add noavx512_vpopcntdq. * doc/c-i386.texi: Document avx512_vpopcntdq, noavx512_vpopcntdq. * testsuite/gas/i386/i386.exp: Run AVX512_VPOPCNTDQ tests. * testsuite/gas/i386/avx512_vpopcntdqd-intel.d: New file. * testsuite/gas/i386/avx512_vpopcntdqd.d: Ditto. * testsuite/gas/i386/avx512_vpopcntdqd.s: Ditto. * testsuite/gas/i386/x86-64-avx512_vpopcntdqd-intel.d: Ditto. * testsuite/gas/i386/x86-64-avx512_vpopcntdqd.d: Ditto. * testsuite/gas/i386/x86-64-avx512_vpopcntdqd.s: Ditto. opcodes/ 2017-01-12 Igor Tsimbalist <igor.v.tsimbalist@intel.com> * i386-dis.c (enum): Add PREFIX_EVEX_0F3855, EVEX_W_0F3855_P_2. * i386-dis-evex.h (evex_table): Updated. * i386-gen.c (cpu_flag_init): Add CPU_AVX512_VPOPCNTDQ_FLAGS, CPU_ANY_AVX512_VPOPCNTDQ_FLAGS. Update CPU_ANY_AVX512F_FLAGS. (cpu_flags): Add CpuAVX512_VPOPCNTDQ. * i386-opc.h (enum): (AVX512_VPOPCNTDQ): New. (i386_cpu_flags): Add cpuavx512_vpopcntdq. * i386-opc.tbl: Add Intel AVX512_VPOPCNTDQ instructions. * i386-init.h: Regenerate. * i386-tbl.h: Ditto.
2017-01-12Return -1 on memory error in print_insn_msp430Yao Qi2-14/+99
Disassemblers in opcodes return -1 on memory error, but msp430 doesn't follow this convention. If I change GDB not to throw exception in disassemble_info.memory_error_func and rely on the return value of disassembler, I'll get the following output. (gdb) disassemble 0x0,+8 Dump of assembler code from 0x0 to 0x8: 0x00000000: .word 0xffff; ???? 0x00000002: .word 0xffff; ???? 0x00000004: .word 0xffff; ???? 0x00000006: .word 0xffff; ???? End of assembler dump. This patch teaches print_insn_msp430 and its callees to return -1 on memory error. opcodes: 2017-01-12 Yao Qi <yao.qi@linaro.org> * msp430-dis.c (msp430_singleoperand): Return -1 if msp430dis_opcode_signed returns false. (msp430_doubleoperand): Likewise. (msp430_branchinstr): Return -1 if msp430dis_opcode_unsigned returns false. (msp430x_calla_instr): Likewise. (print_insn_msp430): Likewise.
2017-01-05Prevent an abort in the FRV disassembler if the target bfd name is unknown.Nick Clifton2-3/+11
PR 20946 * frv-desc.c (lookup_mach_via_bfd_name): Return NULL if the name could not be matched. (frv_cgen_cpu_open): Allow for lookup_mach_via_bfd_name returning NULL.
2017-01-04[AArch64] Add separate feature flag for weaker release consistent load insnsSzabolcs Nagy2-3/+13
The weaker release consistency support of ARMv8.3-A is allowed as an optional extension for ARMv8.2-A, so separate command line option and feature flag is added: -march=armv8.2-a+rcpc turns LDAPR, LDAPRB, LDAPRH instructions on. opcodes/ * aarch64-tbl.h (RCPC, RCPC_INSN): Define. (aarch64_opcode_table): Use RCPC_INSN. include/ * opcode/aarch64.h (AARCH64_FEATURE_RCPC): Define. (AARCH64_ARCH_V8_3): Update. gas/ * config/tc-aarch64.c (aarch64_features): Add rcpc. * doc/c-aarch64.texi (AArch64 Extensions): Document rcpc. * testsuite/gas/aarch64/ldst-exclusive-armv8_3.d: Rename to ... * testsuite/gas/aarch64/ldst-rcpc.d: This. * testsuite/gas/aarch64/ldst-exclusive-armv8_3.s: Rename to ... * testsuite/gas/aarch64/ldst-rcpc.s: This. * testsuite/gas/aarch64/ldst-rcpc-armv8_2.d: New test.
2017-01-03Add support for the Q extension to the RISCV ISA.Kito Cheng2-0/+66
gas * config/tc-riscv.c (riscv_set_arch): Whitelist the "q" ISA extension. (riscv_after_parse_args): Set FLOAT_ABI_QUAD when the Q ISA is enabled and no other ABI is specified. include * opcode/riscv-opc.h: Add support for the "q" ISA extension. opcodes * riscv-opc.c (riscv-opcodes): Add support for the "q" ISA extension. * riscv-opcodes/all-opcodes: Likewise.
2017-01-03Add fall through comment.Dilyan Palauzov2-0/+5
* riscv-dis.c (print_insn_args): Add fall through comment.
2017-01-03Add new Serbian translation for the opcodes library.Nick Clifton4-2/+1515
* po/sr.po: New Serbian translation. * configure.ac (ALL_LINGUAS): Add sr. * configure: Regenerate.
2017-01-02Regen opcodes cgen filesAlan Modra27-0/+237
* epiphany-desc.h: Regenerate. * epiphany-opc.h: Regenerate. * fr30-desc.h: Regenerate. * fr30-opc.h: Regenerate. * frv-desc.h: Regenerate. * frv-opc.h: Regenerate. * ip2k-desc.h: Regenerate. * ip2k-opc.h: Regenerate. * iq2000-desc.h: Regenerate. * iq2000-opc.h: Regenerate. * lm32-desc.h: Regenerate. * lm32-opc.h: Regenerate. * m32c-desc.h: Regenerate. * m32c-opc.h: Regenerate. * m32r-desc.h: Regenerate. * m32r-opc.h: Regenerate. * mep-desc.h: Regenerate. * mep-opc.h: Regenerate. * mt-desc.h: Regenerate. * mt-opc.h: Regenerate. * or1k-desc.h: Regenerate. * or1k-opc.h: Regenerate. * xc16x-desc.h: Regenerate. * xc16x-opc.h: Regenerate. * xstormy16-desc.h: Regenerate. * xstormy16-opc.h: Regenerate.
2017-01-02Update year range in copyright notice of all files.Alan Modra275-278/+282
2017-01-02ChangeLog rotationAlan Modra2-2167/+2181
2016-12-31Fix riscv breakageAlan Modra2-0/+6
* disassemble.c (disassembler): Add break accidentally removed by PRU patch.
2016-12-31PRU Opcode PortDimitar Dimitrov9-1/+548
opcodes/ * Makefile.am: Add PRU source files. * configure.ac: Add PRU target. * disassemble.c (disassembler): Register PRU arch. * pru-dis.c: New file. * pru-opc.c: New file. * Makefile.in: Regenerate. * configure: Regenerate. Signed-off-by: Dimitar Dimitrov <dimitar@dinux.eu>
2016-12-29Return 'int' rather than 'unsigned short' in avrdis_opcodeYao Qi2-6/+23
avrdis_opcode return type is unsigned short, but -1 at the end of this function is returned. Additionally, print_insn_avr doesn't handle when -1 (in case of memory error) is returned from avrdis_opcode. This patch changes avrdis_opcode returning int indicating the error, and adds a new argument for instruction we got on success. The opcode is 16-bit, so I change local variables type to uint16_t, and include "bfd_stdint.h" as a result. On memory error, print_insn_avr returns -1, which is a common convention among most of print_insn_$ARCH functions. opcodes: 2016-12-29 Yao Qi <yao.qi@linaro.org> * avr-dis.c: Include "bfd_stdint.h" (avrdis_opcode): Change return type to int, add argument insn. Set *INSN on success. (print_insn_avr): Check return value of avrdis_opcode, and return -1 on error.
2016-12-28Check bfd support for bfd_mips_elf_get_abiflags in mips make ruleAlan Modra7-132/+38
The previous scheme with a dependency in opcodes on libbfd.la broke "make distclean". * configure.ac: Revert 2016-12-23. * Makefile.am: Likewise. (MIPS_DEFS): Define. (mips-dis.lo): Add rule. * Makefile.in: Regenerate. * aclocal.m4: Regenerate. * config.in: Regenerate. * configure: Regenerate.
2016-12-23MIPS16: Add ASMACRO instruction supportMaciej W. Rozycki2-0/+15
Add ASMACRO instruction support as per the MIPS16e ASE architecture specifications [1][2], completing MIPS16e instruction set support. [1] "MIPS32 Architecture for Programmers, Volume IV-a: The MIPS16e Application-Specific Extension to the MIPS32 Architecture", MIPS Technologies, Inc., Document Number: MD00076, Revision 2.63, July 16, 2013, Section 4.1 "MIPS16e Instruction Descriptions", p. 65 [2] "MIPS64 Architecture for Programmers, Volume IV-a: The MIPS16e Application-Specific Extension to the MIPS64 Architecture", MIPS Technologies, Inc., Document Number: MD00077, Revision 2.60, June 25, 2008, Section 1.1 "MIPS16e Instruction Descriptions", p. 66 include/ * opcode/mips.h: Document `0', `1', `2', `3', `4' and `s' operand codes. opcodes/ * mips16-opc.c (decode_mips16_operand): Add `0', `1', `2', `3', `4' and `s' operand codes. (mips16_opcodes): Add "asmacro" entry. binutils/ * testsuite/binutils-all/mips/mips16-extend-insn.d: Update for ASMACRO support. gas/ * testsuite/gas/mips/mips16-asmacro.d: New test. * testsuite/gas/mips/mips16-32@mips16-asmacro.d: New test. * testsuite/gas/mips/mips16-64@mips16-asmacro.d: New test. * testsuite/gas/mips/mips16-asmacro.s: New test source. * testsuite/gas/mips/mips.exp: Run the new tests.
2016-12-23MIPS16: Simplify extended operand handlingMaciej W. Rozycki3-20/+25
Simplify extended operand handling and only specially process immediates which require bit shuffling, using the generic operand insertion and extraction handlers for the '<' (5-bit shift amount) operand code in particular. Require the least significant bit of all extended operand forms to be (artificially) set to 0 for their special processing to trigger. gas/ * config/tc-mips.c (mips16_immed): Limit `mips16_immed_extend' use to operands whose LSB position is zero. opcodes/ * mips-dis.c (print_mips16_insn_arg): Simplify processing of extended operands. * mips16-opc.c (decode_mips16_operand): Switch the extended form of the `<' operand type to LSB position 22.
2016-12-23MIPS16: Reassign `0' and `4' operand codesMaciej W. Rozycki2-15/+22
Replace `0' and `4' operand codes with `.' and `F' respectively to free up the `0'-`4' consecutive range. No functional change. gas/ * config/tc-mips.c (mips16_macro_build): Replace `0' and `4' operand codes with `.' and `F' respectively. (mips16_macro): Likewise. include/ * opcode/mips.h: Replace `0' and `4' operand codes with `.' and `F' respectively. opcodes/ * mips16-opc.c (decode_mips16_operand): Replace `0' and `4' operand codes with `.' and `F' respectively. (mips16_opcodes): Likewise.
2016-12-23MIPS16: Handle non-extensible instructions correctlyMaciej W. Rozycki3-68/+86
Identify non-extensible instructions in the MIPS16 opcode table and disallow their use with the `.e' instruction size suffix in assembly and do not interpret any EXTEND prefix present as a part of the instruction in disassembly. According to all versions of the MIPS16 ASE specifications the following instructions encodings are not extensible [1][2][3][4][5][6]: I8/MOV32R, I8/MOVR32, all RRR minor opcodes, all RR minor opcodes except from DSRA and DSRL, and EXTEND itself, and as from revision 2.50 of the MIPS16e ASE specifications it has been further clarified what was previously implied, that non-extesiable instructions when preceded with an EXTEND prefix must cause a Reserved Instruction exception [3][5]. Therefore in the presence of an EXTEND prefix none of these instructions are supposed to be handled as extended instructions and supporting these forms in disassembly causes confusion, and in the case of the RRR major opcode it also clashes with the ASMACRO encoding. References: [1] "Product Description, MIPS16 Application-Specific Extension", Version 1.3, MIPS Technologies, Inc., 970130, Table 3. "MIPS16 Instruction Set Summary", p. 5 [2] same, Table 5 "RR Minor Opcodes (RR-type instructions)", p.10 [3] "MIPS32 Architecture for Programmers, Volume IV-a: The MIPS16e Application-Specific Extension to the MIPS32 Architecture", MIPS Technologies, Inc., Document Number: MD00076, Revision 2.63, July 16, 2013, Section 3.9 "MIPS16e Instruction Summaries", pp. 37-39 [4] same, Section 3.15 "Instruction Bit Encoding", pp. 46-49 [5] "MIPS64 Architecture for Programmers, Volume IV-a: The MIPS16e Application-Specific Extension to the MIPS64 Architecture", MIPS Technologies, Inc., Document Number: MD00077, Revision 2.60, June 25, 2008, Section 1.9 "MIPS16e Instruction Summaries", pp. 38-41 [6] same, Section 1.15 "Instruction Bit Encoding", pp. 48-51 include/ * opcode/mips.h (INSN2_SHORT_ONLY): New macro. gas/ * config/tc-mips.c (is_size_valid_16): Disallow a `.e' suffix instruction size override for INSN2_SHORT_ONLY opcode table entries. * testsuite/gas/mips/mips16-extend-swap.d: Adjust output. * testsuite/gas/mips/mips16-macro-e.l: Adjust error messages. * testsuite/gas/mips/mips16-32@mips16-macro-e.l: Adjust error messages. * testsuite/gas/mips/mips16e-32@mips16-macro-e.l: Adjust error messages. * testsuite/gas/mips/mips16-insn-e.d: New test. * testsuite/gas/mips/mips16-insn-t.d: New test. * testsuite/gas/mips/mips16-32@mips16-insn-e.d: New test. * testsuite/gas/mips/mips16-64@mips16-insn-e.d: New test. * testsuite/gas/mips/mips16e-32@mips16-insn-e.d: New test. * testsuite/gas/mips/mips16-32@mips16-insn-t.d: New test. * testsuite/gas/mips/mips16-64@mips16-insn-t.d: New test. * testsuite/gas/mips/mips16e-32@mips16-insn-t.d: New test. * testsuite/gas/mips/mips16-insn-e.l: New stderr output. * testsuite/gas/mips/mips16-insn-t.l: New stderr output. * testsuite/gas/mips/mips16-32@mips16-insn-e.l: New stderr output. * testsuite/gas/mips/mips16-64@mips16-insn-e.l: New stderr output. * testsuite/gas/mips/mips16e-32@mips16-insn-e.l: New stderr output. * testsuite/gas/mips/mips16-32@mips16-insn-t.l: New stderr output. * testsuite/gas/mips/mips16-64@mips16-insn-t.l: New stderr output. * testsuite/gas/mips/mips16e-32@mips16-insn-t.l: New stderr output. * testsuite/gas/mips/mips16-insn-e.s: New test source. * testsuite/gas/mips/mips16-insn-t.s: New test source. * testsuite/gas/mips/mips.exp: Run the new tests. opcodes/ * mips-dis.c (print_insn_mips16): Disallow EXTEND prefix matching for INSN2_SHORT_ONLY opcode table entries. * mips16-opc.c (SH): New macro. (mips16_opcodes): Set SH in `pinfo2' for non-extensible instruction entries: "nop", "addu", "and", "break", "cmp", "daddu", "ddiv", "ddivu", "div", "divu", "dmult", "dmultu", "drem", "dremu", "dsllv", "dsll", "dsrav", "dsra", "dsrlv", "dsrl", "dsubu", "exit", "entry", "jalr", "jal", "jr", "j", "jalrc", "jrc", "mfhi", "mflo", "move", "mult", "multu", "neg", "not", "or", "rem", "remu", "sllv", "sll", "slt", "sltu", "srav", "sra", "srlv", "srl", "subu", "xor", "sdbbp", "seb", "seh", "sew", "zeb", "zeh", "zew" and "extend". binutils/ * testsuite/binutils-all/mips/mips16-extend-insn.d: New test. * testsuite/binutils-all/mips/mips16-extend-insn.s: New test source. * testsuite/binutils-all/mips/mips.exp: Run the new tests.
2016-12-23MIPS16: Remove "extended" BREAK/SDBBP handlingMaciej W. Rozycki2-2/+6
Remove special casing for the `6' operand code used for the embedded trap code of the BREAK and the SDBBP instructions to support supposedly extended forms of these instructions. According to all versions of the MIPS16 ASE specifications these instructions are not extensible [1][2][3][4][5][7][8][10][11], and as from revision 2.50 of the MIPS16e ASE specifications it has been further clarified what was previously implied, that non-extesiable instructions when preceded with an EXTEND prefix must cause a Reserved Instruction exception [5][6][9][10]. Therefore supposedly extended BREAK and SDBBP instructions do not serve their purpose anymore as they do not cause a Bp and a Debug exception respectively and supporting these forms in disassembly only causes confusion. References: [1] "Product Description, MIPS16 Application-Specific Extension", Version 1.3, MIPS Technologies, Inc., 970130, Table 3. "MIPS16 Instruction Set Summary", p. 5 [2] same, Table 5 "RR Minor Opcodes (RR-type instructions)", p.10 [3] same, Table 18. "Extendable MIPS16 Instructions", p. 24 [4] "MIPS32 Architecture for Programmers, Volume IV-a: The MIPS16e Application-Specific Extension to the MIPS32 Architecture", MIPS Technologies, Inc., Document Number: MD00076, Revision 2.63, July 16, 2013, Table 3.8 "MIPS16e Special Instructions", p. 38 [5] same, Section 3.11 "MIPS16e Extensible Instructions, p. 41 [6] same, Table 3.15 "MIPS16e Extensible Instructions", p. 41 [7] same, Table 3.24 "MIPS16e RR Encoding of the Funct Field", p. 49 [8] "MIPS64 Architecture for Programmers, Volume IV-a: The MIPS16e Application-Specific Extension to the MIPS64 Architecture", MIPS Technologies, Inc., Document Number: MD00077, Revision 2.60, June 25, 2008, Table 1.8 "MIPS16e Special Instructions", p. 39 [9] same, Section 1.11 "MIPS16e Extensible Instructions", p. 42 [10] same, Table 1.15 "MIPS16e Extensible Instructions", pp. 42-43 [11] same, Table 1.24 "MIPS16e RR Encoding of the Funct Field", p. 50 gas/ * config/tc-mips.c (match_mips16_insn): Remove the `6' operand code special case and its associated comment. opcodes/ * mips16-opc.c (decode_mips16_operand) <'6'>: Remove extended encoding support.
2016-12-23MIPS16/GAS: Disallow EXTEND delay-slot schedulingMaciej W. Rozycki2-1/+6
Do not allow any explicitly coded EXTEND instruction to be automatically scheduled into a jump delay slot, as an EXTEND prefix is coupled with the next regular MIPS16 instruction and therefore swapping it with a jump would change program's semantics; EXTEND is not architecturally allowed to be present in a jump delay slot anyway. opcodes/ * mips16-opc.c (mips16_opcodes): Set NODS in `pinfo' for "extend". gas/ * testsuite/gas/mips/mips16-extend-swap.d: New test. * testsuite/gas/mips/mips16-extend-swap.s: New test source. * testsuite/gas/mips/mips.exp: Run the new test.
2016-12-23opcodes: Use autoconf to check for `bfd_mips_elf_get_abiflags' in BFDMaciej W. Rozycki8-12/+150
Fix a regression introduced with commit 5e7fc731f80e ("MIPS/opcodes: Also set disassembler's ASE flags from ELF structures"), further updated with commit 4df995c77118 ("MIPS/opcodes: Also set disassembler's ASE flags from ELF structures"), and use autoconf to check for the presence of `bfd_mips_elf_get_abiflags' in BFD. opcodes/ * mips-dis.c (set_default_mips_dis_options): Use HAVE_BFD_MIPS_ELF_GET_ABIFLAGS rather than BFD64 to guard the call to `bfd_mips_elf_get_abiflags'. * configure.ac: Check for `bfd_mips_elf_get_abiflags' in BFD. * Makefile.am (CONFIG_STATUS_DEPENDENCIES): Add `libbfd.la'. * aclocal.m4: Regenerate. * configure: Regenerate. * config.in: Regenerate. * Makefile.in: Regenerate.
2016-12-23Bump version to 2.28.51Tristan Gingold2-10/+14
bfd/ 2016-12-23 Tristan Gingold <gingold@adacore.com> * version.m4: Bump version to 2.28.51 * configure: Regenerate. binutils/ 2016-12-23 Tristan Gingold <gingold@adacore.com> * configure: Regenerate. gas/ 2016-12-23 Tristan Gingold <gingold@adacore.com> * configure: Regenerate. gprof/ 2016-12-23 Tristan Gingold <gingold@adacore.com> * configure: Regenerate. ld/ 2016-12-23 Tristan Gingold <gingold@adacore.com> * configure: Regenerate. opcodes/ 2016-12-23 Tristan Gingold <gingold@adacore.com> * configure: Regenerate.
2016-12-23Regenerate pot files.Tristan Gingold2-372/+640
2016-12-22ChangeLog formatting fixesAlan Modra1-1/+1
2016-12-22Avoid creating symbol table entries for registersAndrew Waterman2-2/+6
Instructions like "jal t0, foo" were erroneously creating symbol table entries for t0 as well as foo, which causes linking problems. Fix by reordering instruction alternatives so that t0 is first attempted to be parsed as a register, rather than as a symbol. * riscv-opc.c (riscv_opcodes): Reorder jal and call entries.
2016-12-20MIPS16/opcodes: Respect ISA and ASE in disassemblyMaciej W. Rozycki2-1/+11
Limit MIPS16 instruction disassembly according to the ISA level and ASE set selected, as with the regular MIPS and microMIPS instruction sets. Retain the property of `objdump -m mips:16' disassembling all MIPS16 instructions however, regardless of any ISA level recorded in the binary examined. To validate the disassembler use the GAS test suite for its convenience of running tests across multiple ISAs, even though placing the tests in the binutils test suite would be more appropriate. Adjust the single binutils test which depends on 64-bit instruction disassembly to have the ISA level required actually recorded in the binary examined. opcodes/ * mips-dis.c (mips_arch_choices): Use ISA_MIPS64 rather than ISA_MIPS3 as the `isa' selection in the `bfd_mach_mips16' entry. (print_insn_mips16): Check opcode entries for validity against the ISA level and ASE set selected. binutils/ * testsuite/binutils-all/mips/mips16-undecoded.s: Use `.module' rather than `.set' to set the ISA level. gas/ * testsuite/gas/mips/mips16-sub.d: New test. * testsuite/gas/mips/mips16-32@mips16-sub.d: New test. * testsuite/gas/mips/mips16e-32@mips16-sub.d: New test. * testsuite/gas/mips/mips16e-sub.d: New test. * testsuite/gas/mips/mips16-32@mips16e-sub.d: New test. * testsuite/gas/mips/mips16-64@mips16e-sub.d: New test. * testsuite/gas/mips/mips16e-64-sub.d: New test. * testsuite/gas/mips/mips16-32@mips16e-64-sub.d: New test. * testsuite/gas/mips/mips16-64@mips16e-64-sub.d: New test. * testsuite/gas/mips/mips16e-32@mips16e-64-sub.d: New test. * testsuite/gas/mips/mips16-sub.s: New test source. * testsuite/gas/mips/mips16e-sub.s: New test source. * testsuite/gas/mips/mips16e-64-sub.s: New test source. * testsuite/gas/mips/mips.exp: Run the new tests.
2016-12-20MIPS16: Switch to 32-bit opcode table interpretationMaciej W. Rozycki3-81/+90
Switch to 32-bit MIPS16 opcode table entry interpretation, similar to how the microMIPS opcode table is handled, for both the `match' and `mask' fields, removing special casing for JAL and JALX instructions and their `a' and `i' operand codes throughout, while retaining automatic processing of extendable opcodes in assembly and disassembly. In assembly disallow size enforcement suffixes as appropriate: `.t' for both 32-bit instructions and macros and `.e' for macros only, making macro handling consistent with the microMIPS instruction set. In disassembly fully decode EXTEND prefixes prepended to unsupported instruction encodings (according to the ISA selection) rather than dumping them as hexadecimal data along with the following instruction, removing all special casing for the EXTEND prefix and making its handling rely on its opcode table entry, except where it is considered a part of an extendable instruction. include/ * opcode/mips.h (mips_opcode_32bit_p): New inline function. gas/ * config/tc-mips.c (micromips_insn_length): Use `mips_opcode_32bit_p'. (is_size_valid): Adjust description. (is_size_valid_16): New function. (validate_mips_insn): Use `mips_opcode_32bit_p' in MIPS16 operand decoding. (validate_mips16_insn): Remove `a' and `i' operand code special casing, use `mips_opcode_32bit_p' to determine instruction width. (append_insn): Adjust forced MIPS16 instruction size determination. (match_mips16_insn): Likewise. Don't shift the instruction's opcode with the `a' and `i' operand codes. Use `mips_opcode_32bit_p' in operand decoding. (match_mips16_insns): Check for forced instruction size's validity. (mips16_ip): Don't force instruction size in the `noautoextend' mode. * testsuite/gas/mips/mips16-jal-e.d: New test. * testsuite/gas/mips/mips16-jal-t.d: New test. * testsuite/gas/mips/mips16-macro-e.d: New test. * testsuite/gas/mips/mips16-macro-t.d: New test. * testsuite/gas/mips/mips16-jal-t.l: New stderr output. * testsuite/gas/mips/mips16-macro-e.l: New stderr output. * testsuite/gas/mips/mips16-macro-t.l: New stderr output. * testsuite/gas/mips/mips16-jal-e.s: New test source. * testsuite/gas/mips/mips16-jal-t.s: New test source. * testsuite/gas/mips/mips16-macro-e.s: New test source. * testsuite/gas/mips/mips16-macro-t.s: New test source. * testsuite/gas/mips/mips.exp: Run the new tests. opcodes/ * mips-dis.c (print_mips16_insn_arg): Always handle `extend' and `insn' together, with `extend' as the high-order 16 bits. (match_kind): New enum. (print_insn_mips16): Rework for 32-bit instruction matching. Do not dump EXTEND prefixes here. * mips16-opc.c (mips16_opcodes): Move "extend" entry to the end. Recode `match' and `mask' fields as 32-bit in absolute "jal" and "jalx" entries. binutils/ * testsuite/binutils-all/mips/mips16-extend-noinsn.d: Adjust test for separate EXTEND prefix disassembly.
2016-12-20MIPS16/opcodes: Correct 64-bit macros' ISA membershipMaciej W. Rozycki2-6/+12
Limit the DDIV, DDIVU, DREM, DREMU and DSUBU macros to the MIPS III rather than MIPS I ISA. These macros expand to machine code sequences including 64-bit instructions which require a 64-bit ISA. Entries for those instructions are already correctly marked, however the marking is ignored if entries are used in the process of macro expansion rather than directly, making it possible to indirectly produce 64-bit machine code even when output requested has been limited to a 32-bit ISA. opcodes/ * mips16-opc.c (mips16_opcodes): Set membership to I3 rather than I1 for the "ddiv", "ddivu", "drem", "dremu" and "dsubu" INSN_MACRO entries. gas/ * testsuite/gas/mips/mips16-macro.l: New list test. * testsuite/gas/mips/mips.exp: Run the new test.
2016-12-20MIPS16/opcodes: Correct I64/SDRASP opcode's ISA membershipMaciej W. Rozycki2-1/+7
Limit the `SD ra, offset(sp)' instruction (I64/SDRASP major/minor opcode) to the MIPS III rather than MIPS I ISA. This is a 64-bit instruction requiring a 64-bit ISA. This bug has been there since forever. opcodes/ * mips16-opc.c (mips16_opcodes): Set membership to I3 rather than I1 for the SP-relative "sd"/$ra entry (SDRASP minor opcode). gas/ * testsuite/gas/mips/mips16-sdrasp.d: New test. * testsuite/gas/mips/mips16-sdrasp.l: New stderr output. * testsuite/gas/mips/mips16-sdrasp.s: New test source. * testsuite/gas/mips/mips.exp: Run the new test.
2016-12-20Correct assembler mnemonic for RISC-V aqrl AMOsAndrew Waterman2-22/+27
sc is a misnomer, because they aren't inherently sc. * riscv-opc.c (riscv_opcodes): Rename the "*.sc" instructions to "*.aqrl".
2016-12-20Fix disassembly of RISC-V CSR instructions under -Mno-aliasesAndrew Waterman2-22/+27
This fixes https://github.com/riscv/riscv-binutils-gdb/issues/36. * riscv-opc.c (riscv_opcodes): Mark the rd* and csr* aliases as INSN_ALIAS.
2016-12-20Add canonical JALR for RISC-VAndrew Waterman2-0/+8
jalr rd,offset(rs1) rather than jalr rd,rs1,offset This matches the format of other instructions. * riscv-opc.c (riscv_opcodes): Change jr and jalr to "o(s)" format.
2016-12-20Re-work RISC-V gas flags: now we just support -mabi and -marchAndrew Waterman2-2/+11
We've decided to standardize on two flags for RISC-V: "-march" sets the target architecture (which determines which instructions can be generated), and "-mabi" sets the target ABI. We needed to rework this because the old flag set didn't support soft-float or single-float ABIs, and didn't support an x32-style ABI on RISC-V. Additionally, we've changed the behavior of the -march flag: it's now a lot stricter and only parses things we can actually understand. Additionally, it's now lowercase-only: the rationale is that while the RISC-V ISA manual specifies that ISA strings are case-insensitive, in Linux-land things are usually case-sensitive. Since this flag can be used to determine library paths, we didn't want to bake some case-insensitivity in there that would case trouble later. This patch implements these two new flags and removes the old flags that could conflict with these. There wasn't a RISC-V release before, so we want to just support a clean flag set. include/ * elf/riscv.h (EF_RISCV_SOFT_FLOAT): Don't define. (EF_RISCV_FLOAT_ABI, EF_RISCV_FLOAT_ABI_SOFT): Define. (EF_RISCV_FLOAT_ABI_SINGLE, EF_RISCV_FLOAT_ABI_DOUBLE): Define. (EF_RISCV_FLOAT_ABI_QUAD): Define. bfd/ * elfnn-riscv.c (_bfd_riscv_elf_merge_private_bfd_data): Use EF_RISCV_FLOAT_ABI_SOFT instead of EF_RISCV_SOFT_FLOAT. binutils/ * readelf.c (get_machine_flags): Use EF_RISCV_FLOAT_ABI_{SOFT,SINGLE,DOBULE,QUAD) instead of EF_RISCV_{SOFT,HARD}_FLOAT. gas/ * config/tc-riscv.h (xlen): Delete. * config/tc-riscv.c (xlen): Make static. (abi_xlen): New variable. (options): Replace OPTION_{M32,M64,MSOFT_FLOAT,MHARD_FLOAT,MRVC} with OPTION_MABI. (md_longopts): Likewise. (md_parse_option): Likewise. (riscv_elf_final_processing): Likewise. * doc/as.texinfo (Target RISC-V options): Likewise. * doc/c-riscv.texi (OPTIONS): Likewise. * config/tc-riscv.c (float_mode): Removed. (float_abi): New type, specifies the floating-point ABI. (riscv_set_abi): New function. (riscv_add_subset): Only allow lower-case ISA names and require them to start with "rv". (riscv_after_parse_args): Likewise. opcodes/ * riscv-dis.c (riscv_disassemble_insn): Default to the ELF's XLEN when none is provided.
2016-12-20Formatting changes for RISC-VAndrew Waterman2-8/+10
This is a mixed bag of format changes: * Replacing constants with macros (0xffffffff with MINUS_ONE, for example). There's one technically functional change in here (some MINUS_ONEs are changed to 0), but it only changes the behavior of an otherwise-unused field. * Using 0 instead of 0x0 in the relocation table. * There were some missing spaces before parens, the spaces have been added. * A handful of comments are now more descriptive. * A bunch of whitespace-only changes, mostly alignment and brace newlines. bfd/ * elfnn-riscv.c: Formatting and comment fixes throughout. * elfxx-riscv.c: Likewise. (howto_table): Change the src_mask field from MINUS_ONE to 0 for R_RISCV_TLS_DTPMOD32, R_RISCV_TLS_DTPMOD64, R_RISCV_TLS_DTPREL32, R_RISCV_TLS_DTPREL64, R_RISCV_TLS_TPREL32, R_RISCV_TLS_TPREL64. opcodes/ * riscv-opc.c: Formatting fixes. gas/ * config/tc-riscv.c: Formatting and comment fixes throughout.
2016-12-20Add opcodes RISC-V dependenciesAlan Modra4-0/+14
* Makefile.am (TARGET_LIBOPCODES_CFILES): Add riscv files. * Makefile.in: Regenerate. * po/POTFILES.in: Regenerate.
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