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2015-12-14[AArch64][PATCH 2/14] Support ARMv8.2 FP16 Vector Three Same instructions.Matthew Wahab5-1363/+1693
2015-12-14[AArch64][PATCH 1/14] Support ARMv8.2 FP16 Adv.SIMD instructions.Matthew Wahab2-0/+8
2015-12-14[AArch64] Fix errors rebasing the ARMv8.2 AT and system registers patchMatthew Wahab2-6/+15
2015-12-12Enable 2 operand form of powerpc mfcr with -manyAlan Modra2-3/+8
2015-12-11[AArch64][Patch 5/5] Add instruction PSB CSYNCMatthew Wahab5-25/+44
2015-12-11[AArch64][Patch 4/5] Support HINT aliases taking operands.Matthew Wahab8-4/+68
2015-12-11[AArch64][Patch 3/5] Adjust maximum number of instruction aliases.Matthew Wahab2-2/+6
2015-12-11[AArch64][Patch 2/5] Add Statistical Profiling Extension system registers.Matthew Wahab2-1/+39
2015-12-10[Aarch64] Support ARMv8.2 AT instructionsMatthew Wahab2-0/+14
2015-12-10[AArch64][PATCH 2/2] Support ARMv8.2 DC CVAP instruction.Matthew Wahab2-0/+21
2015-12-10[AArch64][PATCH 1/2] Add support for ARMv8.2 DC CVAP instruction.Matthew Wahab3-47/+74
2015-12-10[AArch64][binutils] Add support for ARMv8.2 PSTATE.UAO.Matthew Wahab2-0/+21
2015-12-10[AArch64][PATCH 2/2] Add RAS system registers.Matthew Wahab2-0/+45
2015-12-10[AArch64][PATCH 1/2] Add support for RAS instruction ESB.Matthew Wahab4-24/+38
2015-12-09Implement Intel OSPKE instructionsH.J. Lu7-5305/+5384
2015-12-08rl78: Enable MULU for all ISAs.DJ Delorie3-162/+165
2015-12-07Reorder some power9 insnsAlan Modra2-11/+16
2015-12-04Fix failures in the GAS testsuite for the ARC architecture.Claudiu Zissulescu4-106/+162
2015-12-02Fix ldah being disassembled as ldaexhAndre Vieira2-1/+6
2015-11-27[AArch64][PATCH 3/3] Add floating-point FP16 instructionsMatthew Wahab5-682/+964
2015-11-27[AArch64][PATCH 2/3] Adjust a utility function for floating point values.Matthew Wahab2-7/+37
2015-11-27[AArch64][PATCH 1/3] Support ARMv8.2 FP16 floating point instructions.Matthew Wahab2-0/+8
2015-11-27[AArch64] Add ARMv8.2 instruction alias REV64.Matthew Wahab5-768/+785
2015-11-27[AArch64] Add ARMv8.2 instructions BFC and REV64.Matthew Wahab8-861/+967
2015-11-27[AArch64] Let aliased instructions be their preferred form.Matthew Wahab5-2/+202
2015-11-27[Aarch64] Support an ARMv8.2 system register.Matthew Wahab2-0/+11
2015-11-23opcodes: handle mach-o for thumb/arm disambiguation.Tristan Gingold2-0/+12
2015-11-20[AArch64] Add support for ARMv8.1 Virtulization Host Extensions.Matthew Wahab2-0/+78
2015-11-20Remove a if-clause that is redundant because the same test has been performed...Nick Clifton2-4/+5
2015-11-20Update translations.Nick Clifton2-317/+1153
2015-11-19[AArch64] Reject invalid immediate operands to MSR PANMatthew Wahab2-0/+13
2015-11-17Fix the disassembly of conditional instructions will illegal condition select...Nick Clifton2-1/+6
2015-11-14Bump version to 2.26.51Tristan Gingold2-10/+14
2015-11-11Add assembler, disassembler and linker support for power9.Peter Bergner3-107/+686
2015-11-09Move copy_u.w to MSA64 ASE, remove copy_u.d.Robert Suchanek1-2/+1
2015-11-02Disassemble RX NOP instructions as such.Nick Clifton3-18/+98
2015-11-02Fix disassembly of RX zero-offset register indirect instructions.Nick Clifton4-7/+14
2015-10-28Pass noaliases_p to aarch64_decode_insnYao Qi2-5/+15
2015-10-27Fix RL78 disassembly of DE+offset addressing to always show the offset, even ...Vinay Kumar3-24/+31
2015-10-27Display system registers by their names when disassembling RL78 instructions.Vinay Kumar4-13/+34
2015-10-27Fix RL78 disassembly so that SP+OFFSET addressing always shows the offset, ev...Vinay Kumar3-20/+27
2015-10-14Add missing changelog entriesAndreas Krebbel1-0/+7
2015-10-14S/390: Fix instruction type of troo, trot, trto, and trtt.Andreas Krebbel2-5/+5
2015-10-08Fix compile time warning compiling ARC port.Nick Clifton2-1/+6
2015-10-07Avoid using 'template' C++ keywordYao Qi3-3/+9
2015-10-07New ARC implementation.Nick Clifton9-2824/+21958
2015-10-02[aarch64] expose disas_aarch64_insn and rename it to aarch64_decode_insnYao Qi2-4/+12
2015-10-02[aarch64] Remove argument pc from disas_aarch64_insnYao Qi2-3/+7
2015-09-29Add support for extensions in the .machine pseudoop on S/390, e.g. ".machine ...Dominik Vogt3-508/+522
2015-09-28Updare French translation for binutils and German translation for opcodes.Nick Clifton2-3/+7
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