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2013-06-20bfd/Yufeng Zhang2-5/+6
2013-06-172013-06-17 Catherine Moore <clm@codesourcery.com>Catherine Moore4-4/+141
2013-06-17 * Makefile.am (mips-opc.lo): Add rules to create automaticAlan Modra3-6/+58
2013-06-14* rx-decode.opc (rx_decode_opcode): Bit operations onDJ Delorie3-81/+103
2013-06-132013-06-13 Chao-ying Fu <Chao-ying.Fu@imgtec.com>Chao-ying Fu3-0/+38
2013-06-102013-06-09 Sandra Loosemore <sandra@codesourcery.com>Sandra Loosemore2-1/+6
2013-06-08gas/Richard Sandiford4-938/+957
2013-05-24opcodes/Richard Sandiford2-1/+5
2013-05-232013-05-23 Andreas Krebbel <Andreas.Krebbel@de.ibm.com>Andreas Krebbel2-2/+7
2013-05-22include/opcode/Richard Sandiford2-7/+24
2013-05-21opcodes/Peter Bergner3-7/+200
2013-05-17 * ia64-raw.tbl: Replace non-ASCII char.Alan Modra4-10/+16
2013-05-15gas/Saravanan Ekanathan3-2/+7
2013-05-13gas/Yufeng Zhang3-4/+9
2013-05-10binutils/ChangeLog:Andrew Pinski3-3/+55
2013-05-09 * ppc-opc.c (extract_vlesi): Properly sign extend.Alan Modra2-6/+8
2013-05-02 * archures.c: Add some more MSP430 machine numbers.Nick Clifton2-135/+581
2013-04-242013-04-24 Sandra Loosemore <sandra@codesourcery.com>Sandra Loosemore2-1/+6
2013-04-17 PR binutils/15369Nick Clifton2-4/+10
2013-04-10opcodes/Jan Kratochvil2-1/+6
2013-04-08gas/testsuite/Jan Beulich3-15/+8
2013-04-06Increase the accuracy of sparc instruction aliases.David S. Miller3-134/+219
2013-04-03 * elf32-v850.c (v850_elf_is_target_special_symbol): New function.Nick Clifton3-9/+40
2013-03-27Properly check address mode for SIBH.J. Lu2-4/+10
2013-03-27 PR binutils/15068Nick Clifton2-62/+455
2013-03-20* include/opcode/tic6x.h: add tic6x_coding_dreg_(msb|lsb) field coding type inNick Clifton2-3/+20
2013-03-12Eliminate warning message.Michael Eager2-1/+7
2013-03-122013-03-11 Sebastian Huber <sebastian.huber@embedded-brains.de>Sandra Loosemore2-0/+6
2013-03-122013-03-11 Sebastian Huber <sebastian.huber@embedded-brains.de>Sandra Loosemore2-0/+6
2013-03-122013-03-11 Sebastian Huber <sebastian.huber@embedded-brains.de>Sandra Loosemore2-0/+5
2013-03-11Add support for AArch32 CRC instruction in ARMv8.Kyrylo Tkachov2-1/+27
2013-03-08 PR binutils/15241Nick Clifton2-2/+11
2013-03-02Add RegRex64 to rizH.J. Lu3-5/+10
2013-02-28include/opcode/Yufeng Zhang5-390/+513
2013-02-27 * rl78-decode.opc (rl78_decode_opcode): Fix typo.Alan Modra3-202/+208
2013-02-25 * rl78-decode.opc: Fix encoding of DIVWU insn.Nick Clifton3-6/+16
2013-02-19Implement Intel SMAP instructionsH.J. Lu7-2762/+2818
2013-02-15 * metag-dis.c: Initialize outf->bytes_per_chunk to 4Nick Clifton2-0/+7
2013-02-14opcodes/Yufeng Zhang2-15/+24
2013-02-13Correct ChangeLog dates.Maciej W. Rozycki1-1/+1
2013-02-13 opcodes/Maciej W. Rozycki2-0/+8
2013-02-112013-02-11 Kyrylo Tkachov <kyrylo.tkachov@arm.com>Richard Earnshaw2-2/+6
2013-02-09gas/Richard Sandiford2-13/+19
2013-02-062013-02-06 Sandra Loosemore <sandra@codesourcery.com>Sandra Loosemore8-0/+865
2013-02-04 * po/POTFILES.in: Regenerate.Alan Modra4-1013/+1020
2013-01-30include/opcode/Yufeng Zhang8-659/+732
2013-01-24Add support for V850E3V5 architectureNick Clifton3-197/+955
2013-01-17include/opcode/Yufeng Zhang5-10/+28
2013-01-16Add OPERAND_TYPE_IMM32_64H.J. Lu4-2/+16
2013-01-15 * config/tc-v850.c (md_assemble): Allow signed values forNick Clifton3-2/+10
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