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1997-01-30 * tic80-opc.c (tic80_predefined_symbols): Table of name/valueFred Fish3-90/+269
pairs for all predefined symbols recognized by the assembler. Also used by the disassembling routines. (tic80_symbol_to_value): New function. (tic80_value_to_symbol): New function. * tic80-dis.c (print_operand_control_register, print_operand_condition_code, print_operand_bitnum): Remove private tables and use tic80_value_to_symbol function.
1997-01-30Thu Jan 30 11:30:45 1997 Martin M. Hunt <hunt@pizza.cygnus.com>Martin Hunt1-0/+7
* d10v-dis.c (print_operand): Change address printing to correctly handle PC wrapping. Fixes PR11490.
1997-01-29 * mn10200-opc.c (mn10200_operands): Make 8 and 16 bit pc-relativeJeff Law2-2/+7
branchs relaxable.
1997-01-28 * mips-dis.c (print_insn_mips16): Set insn_info information.Ian Lance Taylor2-0/+49
(print_mips16_insn_arg): Likewise.
1997-01-28 * mips-dis.c (print_insn_mips16): Better handling of an extendIan Lance Taylor2-7/+66
opcode followed by an instruction which can not be extended.
1997-01-24* m68k-opc.c (m68k_opcodes): Changed operand specifier for theJ.T. Conklin2-1/+27
coldfire moveb instruction to not allow an address register as destination. Although the documentation does not indicate that this is invalid, experiments uncovered unexpected behavior. Added a comment explaining the situation. Thanks to Andreas Schwab for pointing this out to me.
1997-01-23 * tic80-opc.c (tic80_opcodes): Expand comment to note that theFred Fish2-332/+311
entries are presorted so that entries with the same mnemonic are adjacent to each other in the table. Sort the entries for each instruction so that this is true.
1997-01-20Mon Jan 20 12:48:57 1997 Andreas Schwab ↵Ian Lance Taylor2-7/+72
<schwab@issan.informatik.uni-dortmund.de> * m68k-dis.c: Include <libiberty.h>. (print_insn_m68k): Sort the opcode table on the most significant nibble of the opcode.
1997-01-19 * tic80-dis.c (tic80_opcodes): Add "wrcr", "vmpy", "vrnd",Fred Fish2-16/+86
"vsub", "vst", "xnor", and "xor" instructions. (V_a1): Renamed from V_a, msb of accumulator reg number. (V_a0): Add macro, lsb of accumulator reg number.
1997-01-19 * tic80-dis.c (print_insn_tic80): Broke excessively longFred Fish3-254/+419
function up into several smaller ones and arranged for the instruction printing function to be callable recursively to print vector instructions that have both a load and a math instruction packed into a single opcode. * tic80-opc.c (tic80_opcodes): Expand comment for vld opcode to explain why it comes after the other vector opcodes.
1997-01-18fix operand mask in the "moveml" entries for the coldfire.J.T. Conklin2-8/+9
1997-01-18From the coldfire branch:J.T. Conklin2-21/+39
* m68k-opc.c (m68k_opcodes): add b, w, or l specifier to coldfire move insns to handle immediate operands. From Andreas Schwab: * m68k-opc.c (m68k_opcodes): Delete duplicate entry for "cmpil".
1997-01-17 * tic80-opc.c (V_a, V_m, V_S, V_Z, V_p, OP_V, MASK_V):Fred Fish2-358/+423
New macros for building vector instruction opcodes. (tic80_opcodes): Remove all uses of FMT_SI, FMT_REG, and FMT_LI, which were unused. The field is now a flags field. Remove some opcodes that are possible, but illegal, such as long immediate instructions with doubles for immediate values. Add "vadd" and "vld" instructions.
1997-01-16 * tic80-opc.c (tic80_operands): Reorder some table entries to makeFred Fish2-160/+435
the order more logical. Move the shift alias instructions ("rotl", "shl", "ins", "rotr", "extu", "exts", "srl", and "sra" to be interspersed with the regular sr.x and sl.x instructions. Add and test new instruction opcodes for "sl", "sli", "sr", "sri", "st", "sub", "subu", "swcr", and "trap".
1997-01-13 * tic80-dis.c (print_insn_tic80): Print floating point operandsFred Fish3-1/+108
as floats. * tic80-opc.c (SPFI): Add single precision floating point immediate operand type. (ROTATE): Add rotate operand type for shifts. (ENDMASK): Add for shifts. (n): Macro for the 'n' bit. (i): Macro for the 'i' bit. (PD): Macro for the 'PD' field. (P2): Macro for the 'P2' field. (P1): Macro for the 'P1' field. (tic80_operands): Add entries for "exts", "extu", "fadd", "fcmp", and "fdiv".
1997-01-06Fix copyright.Jeff Law1-1/+1
1997-01-06 * mn10200-dis.c (disassemble): Mask off unwanted bits afterJeff Law2-1/+6
adding in current address for pc-relative operands. Fixes disassembly of backwards 24bit pc-relative addressese.
1997-01-06 * tic80-dis.c (R_SCALED): Add macro to test for ":s" modifier bit.Fred Fish3-78/+159
(print_insn_tic80): If R_SCALED then print ":s" modifier for operand. * tic80-opc.c (REG0, REG22, REG27, SSOFF, LSOFF): Names changed to REG_0, REG_22, REG_DEST, OFF_SS, OFF_SL respectively. (SICR, LICR, REGM_SI, REGM_LI): Names changed to CR_SI, CR_LI, REG_BASE_M_SI, REG_BASE_M_LI respectively. (REG_SCALED, LSI_SCALED): New operand types. (E): New macro for 'E' bit at bit 27. (tic80_opcodes): Add and test dld, dld.u, dst, estop, and etrap opcodes, including the various size flavors (b,h,w,d) for the direct load and store instructions.
1997-01-05 * tic80-dis.c (M_SI, M_LI): Add macros to test for ":m" modifier bitFred Fish3-65/+155
in an instruction. * tic80-dis.c (print_insn_tic80): Change comma and paren handling. Use M_SI and M_LI macros to check for ":m" modifier for GPR operands. * tic80-opc.c (tic80_operands): Add REGM_SI and REGM_LI operands. (F, M_REG, M_LI, M_SI, SZ_REG, SZ_LI, SZ_SI, D, S): New bit-twiddlers. (MASK_LI_M, MASK_SI_M, MASK_REG_M): Remove and replace in opcode masks with "MASK_* & ~M_*" to get the M bit reset. (tic80_opcodes): Add bsr, bsr.a, cmnd, cmp, dcachec, and dcachef.
1997-01-05 * tic80-dis.c (print_insn_tic80): Print TIC80_OPERAND_RELATIVEFred Fish3-23/+214
correctly. Add support for printing TIC80_OPERAND_BITNUM and TIC80_OPERAND_CC, and TIC80_OPERAND_CR operands in symbolic form. * tic80-opc.c (tic80_operands): Add SSOFF, LSOFF, BITNUM, CC, SICR, and LICR table entries. (tic80_opcodes): Add and test "nop", "br", "bbo", "bbz", "bcnd", and "brcr" opcodes.
1997-01-04 * ppc-opc.c (powerpc_operands): Make comment match theFred Fish3-1/+422
actual fields (no shift field). * sparc-opc.c (sparc_opcodes): Document why this cannot be "const". * tic80-dis.c (print_insn_tic80): Replace abort stub with a partial implementation, work in progress. * tic80-opc.c (tic80_operands): Begin construction operands table. (tic80_opcodes): Continue populating opcodes table and start filling in the operand indices. (tic80_num_opcodes): Add this.
1997-01-03 * m68k-opc.c: Add #B case for moveq.Ian Lance Taylor1-0/+4
1997-01-02 * mn10300-dis.c (disassemble): Make sure all variables are initializedJeff Law2-6/+11
before they are used. Fixes various weird disassembly problems.
1996-12-31 * v850-opc.c (v850_opcodes): Put curly-braces around operandsJeff Law1-0/+7
for "breakpoint" instruction. Fixes random assembler failures for hp-x-v850 toolchain.
1996-12-31 * Makefile.in (ALL_CFLAGS): Add -D_GNU_SOURCE.Ian Lance Taylor1-0/+5
(dep): Use ALL_CFLAGS rather than CFLAGS.
1996-12-31Set V850_OPERAND_ADJUST_SHORT_MEMORY flag on sst.{h,w}/sld.{h,w} instructionsMichael Meissner2-2/+10
1996-12-31End tic80 sanitization regions with "end-sanitize-tic80", notKen Raeburn2-2/+2
with "start-sanitize-tic80".
1996-12-31 * Makefile.in (m68k-opc.o, alpha-opc.o): Remove dis-asm.h dependency.Fred Fish2-2/+14
(tic80-dis.o, tic80-opc.o): Add rules per comment in Makefile.in.
1996-12-30 * mips16-opc.c: Add "abs".Ian Lance Taylor1-0/+4
1996-12-29 * Makefile.in (ALL_MACHINES): Add tic80-dis.o and tic80-opc.o.Fred Fish4-3/+36
* disassemble.c (ARCH_tic80): Define if ARCH_all is defined. (disassembler): Add bfd_arch_tic80 support to set disassemble to print_insn_tic80. * tic80-dis.c (print_insn_tic80): Add stub.
1996-12-28(Laying groundwork (that will be incrementally fleshed out) for TIc80 support)Fred Fish4-0/+82
* configure.in (arch in $selarchs): Add bfd_tic80_arch entry. * configure: Regenerate with autoconf. * tic80-dis.c: Add file. * tic80-opc.c: Add file.
1996-12-20Fri Dec 20 14:30:19 1996 Martin M. Hunt <hunt@pizza.cygnus.com>Martin Hunt1-0/+6
* d10v-opc.c (pre_defined_registers): Add cr[0-15], dpc, dpsw, link.
1996-12-18 * mn10200-opc.c (mn10200_operands): Add SIMM16N.Jeff Law2-7/+28
(mn10200_opcodes): Use it for some logicals and btst insns. Add "break" and "trap" instructions.
1996-12-16 * mn10300-opc.c (mn10300_opcodes): Add "break" instruction.Jeff Law2-0/+10
For gdb.
1996-12-16 * mn10200-opc.c: Add pseudo-ops for "mov (an),am" and "mov an,(am)".Jeff Law2-0/+6
1996-12-15 * mips-dis.c (print_mips16_insn_arg): The base address of a PCIan Lance Taylor1-0/+6
relative load or add now depends upon whether the instruction is in a delay slot.
1996-12-12 * mn10200-dis.c: Finish writing disassembler.Jeff Law3-134/+95
* mn10200-opc.c (mn10200_opcodes): Fix mask for "mov imm8,dn". Fix mask for "jmp (an)". mn10200 disassembler works!
1996-12-11 * mn10300-dis.c (disassemble, print_insn_mn10300): CorrentlyJeff Law1-50/+158
handle endianness issues for mn10300.
1996-12-11 * mn10200-opc.c (mn10200_opcodes): Fix operands for "movb dm,(an)".Jeff Law2-1/+5
Yoshihiro Adachi sez the manual was wrong for this insn.
1996-12-10 * mn10200-opc.c (mn10200_opcodes): "mov imm8,d0" is a format 2Jeff Law2-2/+5
instruction. Fix opcode field for "movb (imm24),dn". Stuff found by the testsuite.
1996-12-10 * mn10200-opc.c (mn10200_operands): Fix insertion positionJeff Law2-1/+6
for DI operand. Found by gas testsuite.
1996-12-09 * mn10200-opc.c: Create mn10200 opcode table.Jeff Law3-5/+647
* mn10200-dis.c: Flesh out mn10200 disassembler. Not ready, but moving along nicely. Checkpointing today's mn10200 work.
1996-12-08 * Makefile.in (ALL_MACHINES): Add mips16-opc.o.Peter Schauer1-0/+4
1996-12-07* m68k-opc.c (m68k_opcodes): Revert change to use < and >J.T. Conklin1-0/+5
specifiers for fmovem* instructions.
1996-12-06 * mn10300-dis.c (disassemble): Remove '$' register prefixing.Jeff Law2-10/+14
1996-12-06 * mips16-opc.c: Change opcode for entry/exit to avoid conflictingIan Lance Taylor1-0/+5
with dsrl.
1996-12-06 * mn10300-opc.c: Add some comments explaining the variousJeff Law3-3/+51
operands and such. * mn10300-dis.c (disassemble): Fix minor gcc -Wall warnings.
1996-12-05* m68k-dis.c (print_insn_arg): Handle new < and > operandJ.T. Conklin2-47/+36
specifiers. * m68k-opc.c (m68k_opcodes): Simplify table by using < and > operand specifiers in fmovm* instructions.
1996-12-04 * ppc-opc.c (insert_li): Give an error if the offset has the twoIan Lance Taylor1-0/+10
least significant bits set. PR 11201.
1996-11-26 * mn10300-dis.c (disasemble): Finish conversion to '$' asJeff Law2-5/+8
register prefix. Fixes improper disassembly of movm instructions.
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