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2015-06-02[AArch64] Support for ARMv8.1a Adv.SIMD instructionsMatthew Wahab5-1249/+1359
2015-06-02 Matthew Wahab <matthew.wahab@arm.com> gas/ * config/tc-aarch64.c (aarch64_features): Add "rdma". * doc/c-aarch64.texi (AArch64 Extensions): Add "rdma". gas/testsuite/ * rdma-directive.d: New. * rdma.d: New. * rdma.s: New. include/opcode/ * aarch64.h (AARCH64_FEATURE_RDMA): New. opcode/ * aarch64-tbl.h (aarch64_feature_rdma): New. (RDMA): New. (aarch64_opcode_table): Add "sqrmlah" and "sqrdmlsh" instructions. * aarch64-asm-2.c: Regenerate. * aarch64-dis-2.c: Regenerate. * aarch64-opc-2.c: Regenerate.
2015-06-02[AArch64] Support for ARMv8.1a Limited Ordering Regions extensionMatthew Wahab5-401/+478
2015-06-02 Matthew Wahab <matthew.wahab@arm.com> include/ * aarch64.h (AARCH64_FEATURE_LOR): New. opcodes/ * aarch64-tbl.h (aarch64_feature_lor): New. (LOR): New. (aarch64_opdocde_table): Add "ldlar", "ldlarb", "ldlarh", "stllr", "stllrb", "stllrh". * aarch64-asm-2.c: Regenerate. * aarch64-dis-2.c: Regenerate. * aarch64-opc-2.c: Regenerate. gas/ * config/tc-aarch64.c (aarch64_features): Add "lor". * doc/c-aarch64.c (Aarch64 Extensions): Add "lor" to list of architecture extensions. gas/testsuite/ * lor-directive.d: New. * lor.d: New. * lor.s: New.
2015-06-01[AArch64][libopcode] Add support for PAN architecture extensionMatthew Wahab2-0/+46
The ARMv8.1 architecture introduced the Privileged Access Never extension. This adds a processor state field PSTATE.PAN which can be accessed using the MRS/MSR instructions. This patch adds support for the PAN architecture feature and processor state field to libopcode. include/opcode 2015-06-01 Matthew Wahab <matthew.wahab@arm.com> * aarch64.h (AARCH64_FEATURE_PAN): New. (aarch64_sys_reg_supported_p): Declare. (aarch64_pstatefield_supported_p): Declare. opcodes/ 2015-06-01 Matthew Wahab <matthew.wahab@arm.com> * aarch64-opc.c (F_ARCHEXT): New. (aarch64_sys_regs): Add "pan". (aarch64_sys_reg_supported_p): New. (aarch64_pstatefields): Add "pan". (aarch64_pstatefield_supported_p): New.
2015-06-01x86/Intel: fix i386_optab[] for vcvt{,u}si2s{d,s}Jan Beulich2-6/+10
opcodes/ 2015-06-01 Jan Beulich <jbeulich@suse.com> * i386-tbl.h: Regenerate.
2015-06-01x86/Intel: disassemble vcvt{,u}si2s{d,s} with correct operand orderJan Beulich2-0/+12
As pointed out before, the documentation mandates the rounding mode to follow the GPR, so disassembler should produce output accordingly. gas/testsuite/ 2015-06-01 Jan Beulich <jbeulich@suse.com> * gas/i386/avx512f.s: Adjust operand order for Intel syntax vcvt{,u}si2ss. * gas/i386/x86-64-avx512f.s: Adjust operand order for Intel syntax vcvt{,u}si2s{d,s}. opcodes/ 2015-06-01 Jan Beulich <jbeulich@suse.com> * i386-dis.c (print_insn): Swap rounding mode specifier and general purpose register in Intel mode.
2015-06-01x86/Intel: accept mandated operand order for vcvt{,u}si2s{d,s}Jan Beulich3-0/+143
As pointed out before, the documentation mandates the rounding mode to follow the GPR, so gas should accept such input. As the brojen code got released already we sadly will need to continue to also accept the badly ordered operands. gas/testsuite/ 2015-06-01 Jan Beulich <jbeulich@suse.com> * gas/i386/avx512f-intel.d: Adjust expectations on operand order. * gas/i386/evex-lig256-intel.d: Likewise. * gas/i386/evex-lig512-intel.d: Likewise. * gas/i386/x86-64-avx512f-intel.d: Likewise. * gas/i386/x86-64-evex-lig256-intel.d: Likewise. * gas/i386/x86-64-evex-lig512-intel.d: Likewise. opcodes/ 2015-06-01 Jan Beulich <jbeulich@suse.com> * i386-opc.tbl: New IntelSyntax entries for vcvt{,u}si2s{d,s}. * i386-tbl.h: Regenerate.
2015-05-18Remove Disp32 from AMD64 direct call/jmpH.J. Lu3-4/+9
* i386-opc.tbl: Remove Disp32 from AMD64 direct call/jmp. * i386-init.h: Regenerated.
2015-05-15Support AMD64/Intel ISAs in assembler/disassemblerH.J. Lu7-5296/+5387
AMD64 spec and Intel64 spec differ in direct unconditional branches in 64-bit mode. AMD64 supports direct unconditional branches with 16-bit offset via the data size prefix, which truncates RIP to 16 bits, while the data size prefix is ignored by Intel64. This patch adds -mamd64/-mintel64 option to x86-64 assembler and -Mamd64/-Mintel64 option to x86-64 disassembler. The most permissive ISA, which is AMD64, is the default. GDB can add an option, similar to (gdb) help set disassembly-flavor Set the disassembly flavor. The valid values are "att" and "intel", and the default value is "att". to select which ISA to disassemble. binutils/ PR binutis/18386 * doc/binutils.texi: Document -Mamd64 and -Mintel64. gas/ PR binutis/18386 * config/tc-i386.c (OPTION_MAMD64): New. (OPTION_MINTEL64): Likewise. (md_longopts): Add -mamd64 and -mintel64. (md_parse_option): Handle OPTION_MAMD64 and OPTION_MINTEL64. (md_show_usage): Add -mamd64 and -mintel64. * doc/c-i386.texi: Document -mamd64 and -mintel64. gas/testsuite/ PR binutis/18386 * gas/i386/i386.exp: Run x86-64-branch-2 and x86-64-branch-3. * gas/i386/x86-64-branch.d: Also pass -Mintel64 to objdump. * gas/i386/ilp32/x86-64-branch.d: Likewise. * gas/i386/x86-64-branch-2.d: New file. * gas/i386/x86-64-branch-2.s: Likewise. * gas/i386/x86-64-branch-3.l: Likewise. * gas/i386/x86-64-branch-3.s: Likewise. ld/testsuite/ PR binutis/18386 * ld-x86-64/tlsgdesc.dd: Also pass -Mintel64 to objdump. * ld-x86-64/tlspic.dd: Likewise. * ld-x86-64/x86-64.exp (x86_64tests): Also pass -Mintel64 to objdump for tlspic.dd and tlsgdesc.dd. opcodes/ PR binutis/18386 * i386-dis.c: Add comments for '@'. (x86_64_table): Use '@' on call/jmp for X86_64_E8/X86_64_E9. (enum x86_64_isa): New. (isa64): Likewise. (print_i386_disassembler_options): Add amd64 and intel64. (print_insn): Handle amd64 and intel64. (putop): Handle '@'. (OP_J): Don't ignore the operand size prefix for AMD64 in 64-bit. * i386-gen.c (cpu_flags): Add CpuAMD64 and CpuIntel64. * i386-opc.h (AMD64): New. (CpuIntel64): Likewise. (i386_cpu_flags): Add cpuamd64 and cpuintel64. * i386-opc.tbl: Add direct call/jmp with Disp16|Disp32 for AMD64. Mark direct call/jmp without Disp16|Disp32 as Intel64. * i386-init.h: Regenerated. * i386-tbl.h: Likewise.
2015-05-14Fix some PPC assembler errors.Peter Bergner2-3/+15
Remove the wait instructions for server processors, since they were never implemented. Also add the extra operands added to the tlbie and slbia instructions with ISA 2.06 and ISA 2.05 respectively. binutils/ * MAINTAINERS: Add myself as PPC maintainer. opcodes/ * ppc-opc.c (IH) New define. (powerpc_opcodes) <wait>: Do not enable for POWER7. <tlbie>: Add RS operand for POWER7. <slbia>: Add IH operand for POWER6. gas/testsuite/ * gas/ppc/power4.d: Add a slbia test. * gas/ppc/power4.s: Likewise. * gas/ppc/power6.d: Add slbia and tlbie tests. * gas/ppc/power6.s: Likewise. * gas/ppc/power7.d: Remove wait tests. Add a tlbie test. * gas/ppc/power7.s: Likewise.
2015-05-13Add missing ChangeLog entries for PR binutis/18386H.J. Lu1-0/+13
2015-05-11Remove Disp16|Disp32 from 64-bit direct branchesH.J. Lu3-5/+26
Disp16 and Disp32 aren't supported by direct branches in 64-bit mode. This patch removes them from 64-bit direct branches. * opcodes/i386-opc.tbl (call): Remove Disp16|Disp32 from 64-bit direct branch. (jmp): Likewise. * i386-tbl.h: Regenerated.
2015-05-11Add Intel MCU support to opcodesH.J. Lu8-5817/+5853
* configure.ac: Support bfd_iamcu_arch. * disassemble.c (disassembler): Support bfd_iamcu_arch. * i386-gen.c (cpu_flag_init): Add CPU_IAMCU_FLAGS and CPU_IAMCU_COMPAT_FLAGS. (cpu_flags): Add CpuIAMCU. * i386-opc.h (CpuIAMCU): New. (i386_cpu_flags): Add cpuiamcu. * configure: Regenerated. * i386-init.h: Likewise. * i386-tbl.h: Likewise.
2015-05-09Ignore 0x66 prefix for call/jmp/jcc in 64-bit modeH.J. Lu1-10/+40
The operand size prefix (0x66) is ignored for 32-bit PC-relative call, jmp and jcc in 64-bit mode. gas/testsuite/ PR binutis/18386 * gas/i386/i386.exp: Run x86-64-jump. * gas/i386/x86-64-branch.d: Updated. * gas/i386/ilp32/x86-64-branch.d: Likewise. * gas/i386/x86-64-branch.s: Add tests for the operand size prefix with call, jmp and jb. * gas/i386/x86-64-jump.d: New file. * gas/i386/x86-64-jump.s: Likewise. ld/testsuite/ PR binutis/18386 * ld-x86-64/tlsgdesc.dd: Updated. * ld-x86-64/tlspic.dd: Likewise. opcodes/ PR binutis/18386 * i386-dis.c (X86_64_E8): New. (X86_64_E9): Likewise. Update comments on 'T', 'U', 'V'. Add comments for '^'. (dis386): Replace callT/jmpT with X86_64_E8/X86_64_E9. (x86_64_table): Add X86_64_E8 and X86_64_E9. (mod_table): Replace {T|} with ^ on Jcall/Jmp. (putop): Handle '^'. (OP_J): Ignore the operand size prefix in 64-bit. Don't check REX_W.
2015-04-30Make RL78 disassembler and simulator respect ISA for mul/divDJ Delorie5-447/+509
[gas] * config/rl78-defs.h (rl78_isa_g10): New. (rl78_isa_g13): New. (rl78_isa_g14): New. * config/rl78-parse.y (ISA_G10): New. (ISA_G13): New. (ISA_G14): New. (MULHU, MULH, MULU, DIVHU, DIVWU, MACHU, MACH): Use them. * config/tc-rl78.c (rl78_isa_g10): New. (rl78_isa_g13): New. (rl78_isa_g14): New. [gdb] * rl78-tdep.c (rl78_analyze_prologue): Pass RL78_ISA_DEFAULT to rl78_decode_opcode [include] * dis-asm.h (print_insn_rl78_g10): New. (print_insn_rl78_g13): New. (print_insn_rl78_g14): New. (rl78_get_disassembler): New. * opcode/rl78.h (RL78_Dis_Isa): New. (rl78_decode_opcode): Add ISA parameter. [opcodes] * disassemble.c (disassembler): Choose suitable disassembler based on E_ABI. * rl78-decode.opc (rl78_decode_opcode): Take ISA parameter. Use it to decode mul/div insns. * rl78-decode.c: Regenerate. * rl78-dis.c (print_insn_rl78): Rename to... (print_insn_rl78_common): ...this, take ISA parameter. (print_insn_rl78): New. (print_insn_rl78_g10): New. (print_insn_rl78_g13): New. (print_insn_rl78_g14): New. (rl78_get_disassembler): New. [sim] * rl78/cpu.c (g14_multiply): New. * rl78/cpu.h (g14_multiply): New. * rl78/load.c (rl78_load): Decode ISA completely. * rl78/main.c (main): Expand -M to include other ISAs. * rl78/rl78.c (decode_opcode): Decode based on ISA. * rl78/trace.c (rl78_disasm_fn): New. (sim_disasm_init): Reset it. (sim_disasm_one): Get correct disassembler for ISA.
2015-04-29Updated translations for various binutils components.Nick Clifton2-481/+708
gold * po/fi.po: Updated Finnish translation. opcodes * po/fr.po: Updated French translation. gprof * po/da.po: Update Danish translation.
2015-04-27opcodes/Peter Bergner2-12/+34
* ppc-opc.c (DCBT_EO): New define. (powerpc_opcodes) <lbarx>: Enable for POWER8 and later. <lharx>: Likewise. <stbcx.>: Likewise. <sthcx.>: Likewise. <waitrsv>: Do not enable for POWER7 and later. <waitimpl>: Likewise. <dcbt>: Default to the two operand form of the instruction for all "old" cpus. For "new" cpus, use the operand ordering that matches whether the cpu is server or embedded. <dcbtst>: Likewise. gas/testsuite/ * gas/ppc/a2.s: Fixup test case due to dcbt/dcbtst embedded operand ordering change. * gas/ppc/a2.d: Likewise. * gas/ppc/476.d: Likewise. * gas/ppc/booke.s: Remove invalid 3 operand dcbt tests. * gas/ppc/booke.d: Likewise. * gas/ppc/power7.s: Remove lbarx, lharx, stbcx., sthcx., waitrsv and waitimpl tests. * gas/ppc/power7.d: Likewise.
2015-04-27S/390: Fixes for z13 instructions.Andreas Krebbel3-5/+13
opcodes/ * s390-opc.c: New instruction type VV0UU2. * s390-opc.txt: Fix instruction types for VFCE, VLDE, VFSQ, WFK, and WFC. gas/testsuite/ * gas/s390/zarch-z13.d: Fix tests for VFCE, VLDE, VFSQ, WFK, and WFC. * gas/s390/zarch-z13.s: Likewise.
2015-04-23x86: disambiguate disassembly of certain AVX512 insnsJan Beulich3-13/+52
Certain conversion operations as well as vfpclassp{d,s} are ambiguous when the input operand is in memory and no broadcast is being used. While in Intel mode this gets resolved by printing suitable operand size modifiers, AT&T mode need mnemonic suffixes to be added. gas/testsuite/ 2015-04-23 Jan Beulich <jbeulich@suse.com> * gas/i386/avx512dq.d: Add 'z' suffix to vfpclassp{d,s} non- register, non-broadcast cases. * gas/i386/x86-64-avx512dq.d: Likewise. * gas/i386/avx512dq_vl.d: Add 'x' and 'y' suffixes to vcvt{,u}qq2ps and vfpclassp{d,s} non-register, non-broadcast cases. * gas/i386/x86-64-avx512dq_vl.d: Likewise. * gas/i386/avx512f_vl.d: Add 'x' and 'y' suffixes to vcvt{,t}pd2{,u}dq and vcvtpd2ps non-register, non-broadcast cases. * gas/i386/x86-64-avx512f_vl.d: Likewise. opcodes/ 2015-04-23 Jan Beulich <jbeulich@suse.com> * i386-dis.c (putop): Extend "XY" handling to AVX512. Handle "XZ". * i386-dis-evex.h.c (vcvtpd2ps, vcvtqq2ps, vcvttpd2udq, vcvtpd2udq, vcvtuqq2ps, vcvttpd2dq, vcvtpd2dq): Add %XY. (vfpclasspd, vfpclassps): Add %XZ.
2015-04-15Remove the unused PREFIX_UD_XXXH.J. Lu2-6/+9
Remove the unused PREFIX_UD_XXX. Invalid opcodes should be handled by prefix_table. * i386-dis.c (PREFIX_UD_SHIFT): Removed. (PREFIX_UD_REPZ): Likewise. (PREFIX_UD_REPNZ): Likewise. (PREFIX_UD_DATA): Likewise. (PREFIX_UD_ADDR): Likewise. (PREFIX_UD_LOCK): Likewise.
2015-04-15Check dp->prefix_requirement insteadH.J. Lu2-5/+7
This patch removes prefix_requirement and checks dp->prefix_requirement instead. * i386-dis.c (prefix_requirement): Removed. (print_insn): Don't set prefix_requirement. Check dp->prefix_requirement instead of prefix_requirement.
2015-04-15Handle invalid prefixes for rdrand and rdseedH.J. Lu2-5/+35
This patch puts rdrand and rdseed in prefix_table so that invalid prefixes for rdrand and rdseed are handled properly. gas/testsuite/ PR binutils/17898 * gas/i386/prefix.s: Add rdrand/rdseed prefix tests. * gas/i386/prefix.d: Updated. opcodes/ PR binutils/17898 * i386-dis.c (PREFIX_0FC7_REG_6): Renamed to ... (PREFIX_MOD_0_0FC7_REG_6): This. (PREFIX_MOD_3_0FC7_REG_6): New. (PREFIX_MOD_3_0FC7_REG_7): Likewise. (prefix_table): Replace PREFIX_0FC7_REG_6 with PREFIX_MOD_0_0FC7_REG_6. Add PREFIX_MOD_3_0FC7_REG_6 and PREFIX_MOD_3_0FC7_REG_7. (mod_table): Replace PREFIX_0FC7_REG_6 with PREFIX_MOD_0_0FC7_REG_6. Use PREFIX_MOD_3_0FC7_REG_6 and PREFIX_MOD_3_0FC7_REG_7.
2015-04-15Replace mandatory_prefix with prefix_requirementH.J. Lu2-310/+349
* i386-dis.c (PREFIX_MANDATORY_REPZ): Removed. (PREFIX_MANDATORY_REPNZ): Likewise. (PREFIX_MANDATORY_DATA): Likewise. (PREFIX_MANDATORY_ADDR): Likewise. (PREFIX_MANDATORY_LOCK): Likewise. (PREFIX_MANDATORY): Likewise. (PREFIX_UD_SHIFT): Set to 8 (PREFIX_UD_REPZ): Updated. (PREFIX_UD_REPNZ): Likewise. (PREFIX_UD_DATA): Likewise. (PREFIX_UD_ADDR): Likewise. (PREFIX_UD_LOCK): Likewise. (PREFIX_IGNORED_SHIFT): New. (PREFIX_IGNORED_REPZ): Likewise. (PREFIX_IGNORED_REPNZ): Likewise. (PREFIX_IGNORED_DATA): Likewise. (PREFIX_IGNORED_ADDR): Likewise. (PREFIX_IGNORED_LOCK): Likewise. (PREFIX_OPCODE): Likewise. (PREFIX_IGNORED): Likewise. (Bad_Opcode): Replace PREFIX_MANDATORY with 0. (dis386_twobyte): Replace PREFIX_MANDATORY with PREFIX_OPCODE. (three_byte_table): Likewise. (mod_table): Likewise. (mandatory_prefix): Renamed to ... (prefix_requirement): This. (prefix_table): Replace PREFIX_MANDATORY with PREFIX_OPCODE. Update PREFIX_90 entry. (get_valid_dis386): Check prefix_requirement to see if a prefix should be ignored. (print_insn): Replace mandatory_prefix with prefix_requirement.
2015-04-15[ARM] Disassembles SSAT and SSAT16 instructions incorrectly for Thumb-2Renlin Li2-2/+14
2015-04-15 Renlin Li <renlin.li@arm.com> opcodes/: * arm-dis.c (thumb32_opcodes): Define 'D' format control code, use it for ssat and ssat16. (print_insn_thumb32): Add handle case for 'D' control code. gas/testsuite/: * gas/arm/arch7em.d: Adjust required ssat and ssat16 immediate field. * gas/arm/thumb32.d: Likewise.
2015-04-06x86: Use individual prefix control for each opcode.Ilya Tocar3-1914/+1941
2015-04-06 Ilya Tocar <ilya.tocar@intel.com> H.J. Lu <hongjiu.lu@intel.com> * i386-dis-evex.h (evex_table): Fill prefix_requirement field. * i386-dis.c (PREFIX_MANDATORY_REPZ, PREFIX_MANDATORY_REPNZ, PREFIX_MANDATORY_DATA, PREFIX_MANDATORY_ADDR, PREFIX_MANDATORY_LOCK, PREFIX_UD_SHIFT, PREFIX_UD_REPZ, REFIX_UD_REPNZ, PREFIX_UD_DATA, PREFIX_UD_ADDR, PREFIX_UD_LOCK, PREFIX_OPTIONAL, PREFIX_MANDATORY): Define. (Bad_Opcode, FLOAT, DIS386, DIS386_PREFIX, THREE_BYTE_TABLE_PREFIX): Fill prefix_requirement field. (struct dis386): Add prefix_requirement field. (dis386): Fill prefix_requirement field. (dis386_twobyte): Ditto. (twobyte_has_mandatory_prefix_: Remove. (reg_table): Fill prefix_requirement field. (prefix_table): Ditto. (x86_64_table): Ditto. (three_byte_table): Ditto. (xop_table): Ditto. (vex_table): Ditto. (vex_len_table): Ditto. (vex_w_table): Ditto. (mod_table): Ditto. (bad_opcode): Ditto. (print_insn): Use prefix_requirement. (FGRPd9_2, FGRPd9_4, FGRPd9_5, FGRPd9_6, FGRPd9_7, FGRPda_5, FGRPdb_4, FGRPde_3, FGRPdf_4): Fill prefix_requirement field. (float_reg): Ditto.
2015-03-30opcodes: d10v: fix old style prototypeMike Frysinger2-1/+5
2015-03-29Add the missing opcodes/ChangeLog entryH.J. Lu1-0/+4
2015-03-29Regenerate opcodes/Makefile.inH.J. Lu1-1/+0
* Makefile.in: Regenerated.
2015-03-26powerpc: Only initialise opcode indices onceAnton Blanchard2-25/+34
The gdb TUI is calling gdb_print_insn() (which calls disassemble_init_powerpc()) enough to show up high in profiles. As suggested by Alan, only initialise if the indices are empty. opcodes/ChangeLog: 2015-03-25 Anton Blanchard <anton@samba.org> * ppc-dis.c (disassemble_init_powerpc): Only initialise powerpc_opcd_indices and vle_opcd_indices once.
2015-03-26powerpc: Add slbfee. instructionAnton Blanchard2-0/+6
opcodes/ChangeLog: 2015-03-25 Anton Blanchard <anton@samba.org> * ppc-opc.c (powerpc_opcodes): Add slbfee.
2015-03-24Extend arm_feature_set struct to provide more bitsTerry Guo2-1294/+2543
gas/ChangeLog: 2015-03-24 Terry Guo <terry.guo@arm.com> * config/tc-arm.c (no_cpu_selected): Use new macro to compare features. (parse_psr): Likewise. (do_t_mrs): Likewise. (do_t_msr): Likewise. (static const arm_feature_set arm_ext_*): Defined with new macros. (static const arm_feature_set arm_cext_*): Likewise. (static const arm_feature_set fpu_fpa_ext_*): Likewise. (static const arm_feature_set fpu_vfp_ext_*): Likewise. (deprecated_coproc_regs): Likewise. (UL_BARRIER): Likewise. (barrier_opt_names): Likewise. (arm_cpus): Likewise. (arm_extensions): Likewise. include/opcode/ChangeLog: 2015-03-24 Terry Guo <terry.guo@arm.com> * arm.h (arm_feature_set): Extended to provide more available * bits. (ARM_ANY): Updated to follow above new definition. (ARM_CPU_HAS_FEATURE): Likewise. (ARM_CPU_IS_ANY): Likewise. (ARM_MERGE_FEATURE_SETS): Likewise. (ARM_CLEAR_FEATURE): Likewise. (ARM_FEATURE): Likewise. (ARM_FEATURE_COPY): New macro. (ARM_FEATURE_EQUAL): Likewise. (ARM_FEATURE_ZERO): Likewise. (ARM_FEATURE_CORE_EQUAL): Likewise. (ARM_FEATURE_LOW): Likewise. (ARM_FEATURE_CORE_LOW): Likewise. (ARM_FEATURE_CORE_COPROC): Likewise. opcodes/ChangeLog: 2015-03-24 Terry Guo <terry.guo@arm.com> * arm-dis.c (opcode32): Updated to use new arm feature struct. (opcode16): Likewise. (coprocessor_opcodes): Replace bit with feature struct. (neon_opcodes): Likewise. (arm_opcodes): Likewise. (thumb_opcodes): Likewise. (thumb32_opcodes): Likewise. (print_insn_coprocessor): Likewise. (print_insn_arm): Likewise. (select_arm_features): Follow new feature struct.
2015-03-17Add znver1 processorGanesh Gopalasubramanian7-5283/+5339
2015-03-13MIPS: Fix constraint issues with the R6 beqc and bnec instructionsAndrew Bennett2-2/+7
opcodes/ * mips-opc.c (decode_mips_operand): Fix constraint issues with u and y operands. gas/testsuite/ * gas/mips/mips.exp: Added branch constraints testcase. * gas/mips/r6-branch-constraints.s: New test. * gas/mips/r6-branch-constraints.l: New test.
2015-03-13Add support for MIPS R6 evp and dvp instructions.Andrew Bennett2-0/+8
opcodes/ * mips-opc.c (mips_builtin_opcodes): Add evp and dvp instructions. gas/testsuite/ * gas/mips/r6.s: Add evp and dvp instructions. * gas/mips/r6.d: Likewise. * gas/mips/r6-n32.d: Likewise. * gas/mips/r6-n64.d: Likewise.
2015-03-10S/390: Add more IBM z13 instructionsAndreas Krebbel3-0/+30
opcodes/ 2015-03-10 Andreas Krebbel <krebbel@linux.vnet.ibm.com> * s390-opc.c: Add new IBM z13 instructions. * s390-opc.txt: Likewise. gas/testsuite/ 2015-03-10 Andreas Krebbel <krebbel@linux.vnet.ibm.com> * gas/s390/zarch-z13.d: Add more z13 instructions. * gas/s390/zarch-z13.s: Likewise.
2015-03-10[AARCH64] Remove Load/Store register (unscaled immediate) alias.Jiong Wang5-490/+439
opcodes/ChangeLog: 2015-03-10 Renlin Li <renlin.li@arm.com> * aarch64-tbl.h (aarch64_opcode_table): Remove strub, ldurb, ldursb, stur, ldur, sturh, ldurh, ldursh, ldursw, prfum F_HAS_ALIAS flag and related alias. * aarch64-asm-2.c: Regenerate. * aarch64-dis-2.c: Likewise. * aarch64-opc-2.c: Likewise. gas/testsuite/ChangeLog: 2015-03-10 Renlin Li <renlin.li@arm.com> * gas/aarch64/ldst-reg-uns-imm.d: Adjust expected output. * gas/aarch64/ldst-reg-unscaled-imm.d: Likewise. * gas/aarch64/reloc-insn.d: Likewise.
2015-03-03[ARM] Skip private symbol when doing objdumpJiong Wang2-2/+9
2015-03-03 Jiong Wang <jiong.wang@arm.com> opcode/ * arm-dis.c (arm_symbol_is_valid): Skip ARM private symbols. binutils/testsuite/ * binutils-all/arm/rvct_symbol.s: New testcase. * binutils-all/arm/objdump.exp: Run it.
2015-02-25[SH] Fix clrs, sets, pref insn arch memberships.Oleg Endo2-3/+10
opcodes/ * sh-opc.h (clrs, sets): Mark as arch_sh3_nommu_up instead of arch_sh_up. (pref): Mark as arch_sh2a_nofpu_or_sh3_nommu_up instead of arch_sh2a_nofpu_or_sh4_nommu_nofpu_up. gas/testsuite/ * gas/sh/arch/arch.exp: Replace dead code to generate expected .s files with ... * gas/sh/arch/sh-opc-gen-as.pl: ... this new script. * gas/sh/arch/arch_expected.txt: Regenerate. * gas/sh/arch/sh-dsp.s: Likewise. * gas/sh/arch/sh-opc-gen-as.pl: Likewise. * gas/sh/arch/sh.s: Likewise. * gas/sh/arch/sh2.s: Likewise. * gas/sh/arch/sh2a-nofpu-or-sh3-nommu.s: Likewise. * gas/sh/arch/sh2a-nofpu-or-sh4-nommu-nofpu.s: Likewise. * gas/sh/arch/sh2a-nofpu.s: Likewise. * gas/sh/arch/sh2a-or-sh3e.s: Likewise. * gas/sh/arch/sh2a-or-sh4.s: Likewise. * gas/sh/arch/sh2a.s: Likewise. * gas/sh/arch/sh2e.s: Likewise. * gas/sh/arch/sh3-dsp.s: Likewise. * gas/sh/arch/sh3-nommu.s: Likewise. * gas/sh/arch/sh3.s: Likewise. * gas/sh/arch/sh3e.s: Likewise. * gas/sh/arch/sh4-nofpu.s: Likewise. * gas/sh/arch/sh4-nommu-nofpu.s: Likewise. * gas/sh/arch/sh4.s: Likewise. * gas/sh/arch/sh4a-nofpu.s: Likewise. * gas/sh/arch/sh4a.s: Likewise. * gas/sh/arch/sh4al-dsp.s: Likewise. ld/testsuite/ * ld-sh/arch/arch_expected.txt: Regenerate. * ld-sh/arch/sh-dsp.s: Likewise. * ld-sh/arch/sh.s: Likewise. * ld-sh/arch/sh2.s: Likewise. * ld-sh/arch/sh2a-nofpu-or-sh3-nommu.s: Likewise. * ld-sh/arch/sh2a-nofpu-or-sh4-nommu-nofpu.s: Likewise. * ld-sh/arch/sh2a-nofpu.s: Likewise. * ld-sh/arch/sh2a-or-sh3e.s: Likewise. * ld-sh/arch/sh2a-or-sh4.s: Likewise. * ld-sh/arch/sh2a.s: Likewise. * ld-sh/arch/sh2e.s: Likewise. * ld-sh/arch/sh3-dsp.s: Likewise. * ld-sh/arch/sh3-nommu.s: Likewise. * ld-sh/arch/sh3.s: Likewise. * ld-sh/arch/sh3e.s: Likewise. * ld-sh/arch/sh4-nofpu.s: Likewise. * ld-sh/arch/sh4-nommu-nofpu.s: Likewise. * ld-sh/arch/sh4.s: Likewise. * ld-sh/arch/sh4a-nofpu.s: Likewise. * ld-sh/arch/sh4a.s: Likewise. * ld-sh/arch/sh4al-dsp.s: Likewise.
2015-02-23Adds a space between the operands of the RL78's MOV instruction for ↵Vinay3-8/+14
consistency with the disassembling of other instructions. * rl78-decode.opc (MOV): Added space between two operands for 'mov' instruction in index addressing mode. * rl78-decode.c: Regenerate.
2015-02-19Wrap a few opcodes headers in extern "C" for C++Pedro Alves2-0/+12
These are sufficient to link an --enable-targets=all GDB build in C++ mode, on x86_64 Fedora 20. include/opcode/ 2015-02-19 Pedro Alves <palves@redhat.com> * cgen.h [__cplusplus]: Wrap in extern "C". * msp430-decode.h [__cplusplus]: Likewise. * nios2.h [__cplusplus]: Likewise. * rl78.h [__cplusplus]: Likewise. * rx.h [__cplusplus]: Likewise. * tilegx.h [__cplusplus]: Likewise. opcodes/ 2015-02-19 Pedro Alves <palves@redhat.com> * microblaze-dis.h [__cplusplus]: Wrap in extern "C".
2015-02-11Fixes a problem with the RL78 disassembler which would incorrectly ↵Nick Clifton3-93/+93
disassemble [HL+0] as [HL]. * rl78-decode.opc: Add 'a' attribute to instructions that support [HL+0] addressing. * rl78-decode.c: Regenerate. * rl78-dis.c (print_insn_rl78): Display the offset in [HL+0] addresses.
2015-02-10opcodes/microblaze: Rename 'or', 'and', 'xor' to avoid C++ conflictPedro Alves3-4/+13
Building GDB as a C++ program, we see: In file included from gdb/microblaze-tdep.c:37:0: gdb/../opcodes/../opcodes/microblaze-opcm.h: At global scope: gdb/../opcodes/../opcodes/microblaze-opcm.h:32:51: error: expected identifier before ‘or’ token ncget, ncput, muli, bslli, bsrai, bsrli, mului, or, and, xor, ^ gdb/../opcodes/../opcodes/microblaze-opcm.h:32:51: error: expected ‘}’ before ‘or’ token gdb/../opcodes/../opcodes/microblaze-opcm.h:32:51: error: expected unqualified-id before ‘or’ token gdb/../opcodes/../opcodes/microblaze-opcm.h:60:1: error: expected declaration before ‘}’ token }; ^ opcodes/ChangeLog: 2015-02-10 Pedro Alves <palves@redhat.com> Tom Tromey <tromey@redhat.com> * microblaze-opcm.h (or, and, xor): Rename to microblaze_or, microblaze_and, microblaze_xor. * microblaze-opc.h (opcodes): Adjust.
2015-01-29NDS32: Set branch instruction to relaxable.Kuan-Lin Chen1-1/+2
Relaxable fragments can be relaxed when there are alignment requirements. Besides, insert a dummy fragment in the final to make sure that all alignment is traversed. Finally, convert these fragments in md_convert_frag with relax_table.
2015-01-28FT32 initial supportAlan Modra9-0/+292
FT32 is a new 32-bit RISC core developed by FTDI for embedded applications. * configure.ac: Add FT32 support. * configure: Regenerate. bfd/ * Makefile.am: Add FT32 files. * archures.c (enum bfd_architecture): Add bfd_arch_ft32. (bfd_mach_ft32): Define. (bfd_ft32_arch): Declare. (bfd_archures_list): Add bfd_ft32_arch. * config.bfd: Handle FT32. * configure.ac: Likewise. * cpu-ft32.c: New file. * elf32-ft32.c: New file. * reloc.c (BFD_RELOC_FT32_10, BFD_RELOC_FT32_20, BFD_RELOC_FT32_17, BFD_RELOC_FT32_18): Define. * targets.c (_bfd_target_vector): Add ft32_elf32_vec. * bfd-in2.h: Regenerate. * libbfd.h: Regenerate. * Makefile.in: Regenerate. * configure: Regenerate. * po/SRC-POTFILES.in: Regenerate. binutils/ * readelf.c: Add FT32 support. gas/ * Makefile.am: Add FT32 files. * config/tc-ft32.c: New file. * config/tc-ft32.h: New file. * configure.tgt: Add FT32 support. * Makefile.in: Regenerate. * po/POTFILES.in: Regenerate. gas/testsuite/ * gas/ft32/ft32.exp: New file. * gas/ft32/insn.d: New file. * gas/ft32/insn.s: New file. include/ * dis-asm.h (print_insn_ft32): Declare. include/elf/ * common.h (EM_FT32): Define. * ft32.h: New file. include/opcode/ * ft32.h: New file. ld/ * Makefile.am: Add FT32 files. * configure.tgt: Handle FT32 target. * emulparams/elf32ft32.sh: New file. * scripttempl/ft32.sc: New file. * Makefile.in: Regenerate. opcodes/ * Makefile.am: Add FT32 files. * configure.ac: Handle FT32. * disassemble.c (disassembler): Call print_insn_ft32. * ft32-dis.c: New file. * ft32-opc.c: New file. * Makefile.in: Regenerate. * configure: Regenerate. * po/POTFILES.in: Regenerate.
2015-01-28NDS32/opcodes: Add new system registers.Kuan-Lin Chen2-2/+14
2015-01-16S/390: Add support for IBM z13.Andreas Krebbel5-530/+1203
- 32 128 bit vector registers (overlapping with the existing 16 64 bit floating point registers) - vector double instructions - vector integer instructions - scalar vector instructions (allowing to have more floating point registers for scalar operations) - vector string instructions gas/ChangeLog: * config/tc-s390.c (struct pd_reg): Remove. (pre_defined_registers): Remove. (REG_NAME_CNT): Remove. (reg_name_search): Calculate the register number instead of doing a lookup. (register_name, tc_s390_regname_to_dw2regnum): Adopt to the new reg_name_search signature. (s390_parse_cpu): Support the new arch string z13. (s390_insert_operand): Support for vector registers with the extra field for the fifth bit of each vector register operand. (md_gather_operand): Adjust to the new handling of optional parameters. * doc/as.texinfo: Document the z13 cpu string. gas/testsuite/ChangeLog: * gas/s390/esa-g5.d: Add a variant without the optional operand. * gas/s390/esa-g5.s: Likewise. * gas/s390/esa-z9-109.d: Likewise. * gas/s390/esa-z9-109.s: Likewise. * gas/s390/zarch-z9-109.d: Likewise. * gas/s390/zarch-z9-109.s: Likewise. * gas/s390/zarch-z10.d: For variants with a zero optional argument it is not dumped by objdump anymore. * gas/s390/zarch-zEC12.d: Likewise. * gas/s390/zarch-z13.d: New file. * gas/s390/zarch-z13.s: New file. * gas/s390/s390.exp: Run the test for the z13 files. include/opcode/ChangeLog: * s390.h (s390_opcode_cpu_val): Add S390_OPCODE_Z13. ld/testsuite/ChangeLog: * ld-s390/tlsbin.dd: The nopr register operand is optional and not printed if 0 anymore. opcodes/ChangeLog: * s390-dis.c (s390_extract_operand): Support vector register operands. (s390_print_insn_with_opcode): Support new operands types and add new handling of optional operands. * s390-mkopc.c (s390_opcode_mode_val, s390_opcode_cpu_val): Remove and include opcode/s390.h instead. (struct op_struct): New field `flags'. (insertOpcode, insertExpandedMnemonic): New parameter `flags'. (dumpTable): Dump flags. (main): Parse flags from the s390-opc.txt file. Add z13 as cpu string. * s390-opc.c: Add new operands types, instruction formats, and instruction masks. (s390_opformats): Add new formats for .insn. * s390-opc.txt: Add new instructions.
2015-01-02Regenerate Makeile.in file for copyright updateAlan Modra1-1/+1
2015-01-02ChangeLog rotatation and copyright year updateAlan Modra265-1150/+1168
2014-12-27Limit moxie sto/ldo offsets to 16 bitsAnthony Green3-16/+22
2014-12-24Add mul.x and umul.x instructions to moxie portAnthony Green2-9/+14
2014-12-16Add in a JALRC alias and fix the NAL instruction.Matthew Fortune2-1/+7
opcodes/ * mips-opc.c (mips_builtin_opcodes): Add JALRC alias for JIALC. Remove the operand from NAL. gas/testsuite/ * gas/mips/r6.s: Test JALRC and NAL * gas/mips/r6-n32.d: Add expected output for JALRC and NAL. * gas/mips/r6-n64.d: Likewise. * gas/mips/r6.d: Likewise.
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