| Age | Commit message (Expand) | Author | Files | Lines |
|---|
| 2015-06-12 | Remove unused MTMSRD_L macro and re-add accidentally deleted comment. | Peter Bergner | 2 | -2/+7 |
| 2015-06-04 | Add hwsync extended mnemonic. | Peter Bergner | 1 | -0/+1 |
| 2015-06-04 | Fixes the check for emulated MSP430 instrucrtions that take no operands. | Nick Clifton | 2 | -1/+6 |
| 2015-06-02 | [ARM] Support for ARMv8.1 Adv.SIMD extension | Matthew Wahab | 1 | -0/+19 |
| 2015-06-02 | [ARM] Add support for ARMv8.1 PAN extension | Matthew Wahab | 2 | -0/+10 |
| 2015-06-02 | [ARM] Rework CPU feature selection in the disassembler | Matthew Wahab | 2 | -29/+31 |
| 2015-06-02 | [AArch64] Support for ARMv8.1a Adv.SIMD instructions | Matthew Wahab | 5 | -1249/+1359 |
| 2015-06-02 | [AArch64] Support for ARMv8.1a Limited Ordering Regions extension | Matthew Wahab | 5 | -401/+478 |
| 2015-06-01 | [AArch64][libopcode] Add support for PAN architecture extension | Matthew Wahab | 2 | -0/+46 |
| 2015-06-01 | x86/Intel: fix i386_optab[] for vcvt{,u}si2s{d,s} | Jan Beulich | 2 | -6/+10 |
| 2015-06-01 | x86/Intel: disassemble vcvt{,u}si2s{d,s} with correct operand order | Jan Beulich | 2 | -0/+12 |
| 2015-06-01 | x86/Intel: accept mandated operand order for vcvt{,u}si2s{d,s} | Jan Beulich | 3 | -0/+143 |
| 2015-05-18 | Remove Disp32 from AMD64 direct call/jmp | H.J. Lu | 3 | -4/+9 |
| 2015-05-15 | Support AMD64/Intel ISAs in assembler/disassembler | H.J. Lu | 7 | -5296/+5387 |
| 2015-05-14 | Fix some PPC assembler errors. | Peter Bergner | 2 | -3/+15 |
| 2015-05-13 | Add missing ChangeLog entries for PR binutis/18386 | H.J. Lu | 1 | -0/+13 |
| 2015-05-11 | Remove Disp16|Disp32 from 64-bit direct branches | H.J. Lu | 3 | -5/+26 |
| 2015-05-11 | Add Intel MCU support to opcodes | H.J. Lu | 8 | -5817/+5853 |
| 2015-05-09 | Ignore 0x66 prefix for call/jmp/jcc in 64-bit mode | H.J. Lu | 1 | -10/+40 |
| 2015-04-30 | Make RL78 disassembler and simulator respect ISA for mul/div | DJ Delorie | 5 | -447/+509 |
| 2015-04-29 | Updated translations for various binutils components. | Nick Clifton | 2 | -481/+708 |
| 2015-04-27 | opcodes/ | Peter Bergner | 2 | -12/+34 |
| 2015-04-27 | S/390: Fixes for z13 instructions. | Andreas Krebbel | 3 | -5/+13 |
| 2015-04-23 | x86: disambiguate disassembly of certain AVX512 insns | Jan Beulich | 3 | -13/+52 |
| 2015-04-15 | Remove the unused PREFIX_UD_XXX | H.J. Lu | 2 | -6/+9 |
| 2015-04-15 | Check dp->prefix_requirement instead | H.J. Lu | 2 | -5/+7 |
| 2015-04-15 | Handle invalid prefixes for rdrand and rdseed | H.J. Lu | 2 | -5/+35 |
| 2015-04-15 | Replace mandatory_prefix with prefix_requirement | H.J. Lu | 2 | -310/+349 |
| 2015-04-15 | [ARM] Disassembles SSAT and SSAT16 instructions incorrectly for Thumb-2 | Renlin Li | 2 | -2/+14 |
| 2015-04-06 | x86: Use individual prefix control for each opcode. | Ilya Tocar | 3 | -1914/+1941 |
| 2015-03-30 | opcodes: d10v: fix old style prototype | Mike Frysinger | 2 | -1/+5 |
| 2015-03-29 | Add the missing opcodes/ChangeLog entry | H.J. Lu | 1 | -0/+4 |
| 2015-03-29 | Regenerate opcodes/Makefile.in | H.J. Lu | 1 | -1/+0 |
| 2015-03-26 | powerpc: Only initialise opcode indices once | Anton Blanchard | 2 | -25/+34 |
| 2015-03-26 | powerpc: Add slbfee. instruction | Anton Blanchard | 2 | -0/+6 |
| 2015-03-24 | Extend arm_feature_set struct to provide more bits | Terry Guo | 2 | -1294/+2543 |
| 2015-03-17 | Add znver1 processor | Ganesh Gopalasubramanian | 7 | -5283/+5339 |
| 2015-03-13 | MIPS: Fix constraint issues with the R6 beqc and bnec instructions | Andrew Bennett | 2 | -2/+7 |
| 2015-03-13 | Add support for MIPS R6 evp and dvp instructions. | Andrew Bennett | 2 | -0/+8 |
| 2015-03-10 | S/390: Add more IBM z13 instructions | Andreas Krebbel | 3 | -0/+30 |
| 2015-03-10 | [AARCH64] Remove Load/Store register (unscaled immediate) alias. | Jiong Wang | 5 | -490/+439 |
| 2015-03-03 | [ARM] Skip private symbol when doing objdump | Jiong Wang | 2 | -2/+9 |
| 2015-02-25 | [SH] Fix clrs, sets, pref insn arch memberships. | Oleg Endo | 2 | -3/+10 |
| 2015-02-23 | Adds a space between the operands of the RL78's MOV instruction for consisten... | Vinay | 3 | -8/+14 |
| 2015-02-19 | Wrap a few opcodes headers in extern "C" for C++ | Pedro Alves | 2 | -0/+12 |
| 2015-02-11 | Fixes a problem with the RL78 disassembler which would incorrectly disassembl... | Nick Clifton | 3 | -93/+93 |
| 2015-02-10 | opcodes/microblaze: Rename 'or', 'and', 'xor' to avoid C++ conflict | Pedro Alves | 3 | -4/+13 |
| 2015-01-29 | NDS32: Set branch instruction to relaxable. | Kuan-Lin Chen | 1 | -1/+2 |
| 2015-01-28 | FT32 initial support | Alan Modra | 9 | -0/+292 |
| 2015-01-28 | NDS32/opcodes: Add new system registers. | Kuan-Lin Chen | 2 | -2/+14 |
