aboutsummaryrefslogtreecommitdiff
path: root/opcodes
AgeCommit message (Expand)AuthorFilesLines
2014-02-28Regenerate opcodes/msp430-decode.cAlan Modra2-157/+179
2014-02-27opcodes/Yufeng Zhang2-10/+15
2014-02-27opcodes/Yufeng Zhang2-2/+10
2014-02-25Remove bogus vcvtps2ph variant.Ilya Tocar3-20/+6
2014-02-21Add support for CPUID PREFETCHWT1Ilya Tocar6-3854/+3880
2014-02-20Change cpu for vptestnmd and vptestnmq instructions.Ilya Tocar3-36/+41
2014-02-19Don't output trailing spaceH.J. Lu4-41865/+41882
2014-02-12Add clflushopt, xsaves, xsavec, xrstorsIlya Tocar7-3847/+4028
2014-02-10binutils potfiles regenAlan Modra3-120/+106
2014-01-30Fix shift for AVX512F gather/scatter instructionsMichael Zolotukhin2-3/+8
2014-01-09Fix buffer underrun in i386-dis.c.Roland McGrath2-1/+7
2014-01-08Update copyright year to 2014H.J. Lu2-2/+6
2014-01-08New Year - binutils ChangeLog rotationH.J. Lu2-1352/+1366
2014-01-06* nds32-asm.c (parse_operand): Fix out-of-range integer constant.Maciej W. Rozycki2-1/+5
2013-12-18Add system register and embedded debug register support.Kuan-Lin Chen3-6/+147
2013-12-17Properly handle ljmp/lcall with invalid MODRM byteMichael Zolotukhin2-2/+19
2013-12-16Add support to show the symbolic names of the MIPS CP1 registers.Andrew Bennett2-39/+115
2013-12-16Range of element index is too large on MIPS MSA element selection instructions.Andrew Bennett3-56/+67
2013-12-132013-12-13 Jan-Benedict Glaw <jbglaw@lug-owl.de>Jan-Benedict Glaw2-2/+6
2013-12-13Add support for Andes NDS32:Kuan-Lin Chen10-0/+3257
2013-12-05 * s390-mkopc.c (dumpTable): Provide a format string to printf soNick Clifton2-2/+8
2013-11-20gas/testsuite/Yufeng Zhang2-5/+9
2013-11-192013-11-19 Catherine Moore <clm@codesourcery.com>Catherine Moore3-57/+64
2013-11-18Revert "Add support for AArch64 trace unit registers."Yufeng Zhang2-236/+12
2013-11-15gas/Yufeng Zhang2-0/+244
2013-11-15MIPS/opcodes: Add MFCR and MTCR data dependenciesMaciej W. Rozycki2-2/+7
2013-11-11Fix ChangeLog entries from earlier commit.Catherine Moore1-0/+11
2013-11-112013-11-11 Catherine Moore <clm@codesourcery.com>Catherine Moore2-90/+90
2013-11-08Remove CpuNop from CPU_K6_2_FLAGSH.J. Lu3-2/+8
2013-11-05gas/Yufeng Zhang2-310/+330
2013-11-05gas/Yufeng Zhang7-35/+68
2013-11-05opcodes/Yufeng Zhang2-4/+19
2013-10-30S/390: Disassemble 31-bit binaries with "zarch" opcode set by defaultAndreas Arnez2-11/+6
2013-10-15Fix neon vshll disassembly.Ramana Radhakrishnan2-3/+7
2013-10-142013-10-14 Chao-ying Fu <Chao-ying.Fu@imgtec.com>Chao-ying Fu4-2/+1188
2013-10-142013-10-13 Sandra Loosemore <sandra@codesourcery.com>Sandra Loosemore2-2/+7
2013-10-12Only allow 32-bit/64-bit registers for bndcl/bndcu/bndcnH.J. Lu4-24/+82
2013-10-11 * Removed short_hand field from opcode table andSean Keys3-228/+209
2013-10-11opcodes/Roland McGrath2-20/+33
2013-10-10opcodes/Roland McGrath3-13/+24
2013-10-10opcodes/Roland McGrath2-3/+8
2013-10-08opcodes/Jan Beulich3-26/+33
2013-10-072013-10-07 Chao-ying Fu <Chao-ying.Fu@imgtec.com>Chao-ying Fu2-4/+8
2013-09-30Add Size64 to movq/vmovq with Reg64 operandH.J. Lu3-16/+21
2013-09-30Add AMD bdver4 support.Saravanan Ekanathan3-0/+13
2013-09-20 * libtool.m4 (_LT_ENABLE_LOCK <ld -m flags>): Remove non-canonicalAlan Modra2-5/+15
2013-09-17opcodes/Richard Sandiford2-1/+5
2013-09-04 PR gas/15914Nick Clifton2-3/+24
2013-09-022013-09-02 Andreas Krebbel <Andreas.Krebbel@de.ibm.com>Andreas Krebbel2-3/+9
2013-08-28 * aarch64-opc.c (aarch64_logical_immediate_p): Return FALSE if theNick Clifton2-1/+7
generated by cgit v1.1 at 2024-12-24 05:05:37 +0000