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2006-09-16* bfd-in.h (STRING_AND_COMMA): New macro. Takes one constant string as itsNick Clifton7-47/+58
argument and emits the string followed by a comma and then the length of the string. (CONST_STRNEQ): New macro. Checks to see if a variable string has a constant string as its initial characters. (CONST_STRNCPY): New macro. Copies a constant string to the start of a variable string. * bfd-in2.h: Regenerate. * <remainign files>: Make use of the new macros.
2006-09-052006-09-04 Paul Brook <paul@codesourcery.com>Paul Brook2-1/+5
gas/ * config/tc-arm.c (do_neon_dyadic_if_i): Remove. (do_neon_dyadic_if_i_d): Avoid setting U bit. (do_neon_mac_maybe_scalar): Ditto. (do_neon_dyadic_narrow): Force operand type to NT_integer. (insns): Remove out of date comments. gas/testsuite/ * gas/arm/neon-cov.s: Test .u and .s aliases for .i suffixes. * gas/arm/neon-cov.d: Adjust expected output. opcodes/ * arm-dis.c (neon_opcode): Fix suffix on VMOVN.
2006-08-232006-08-23 H.J. Lu <hongjiu.lu@intel.com>H.J. Lu2-3/+519
* i386-dis.c (three_byte_table): Expand to 256 elements.
2006-08-14Fix bug 3000Michael Meissner2-6/+55
2006-07-29opcodes/Richard Sandiford2-1/+6
* m68k-opc.c (m68k_opcodes): Fix operand specificer in the Coldfire "fdaddl" entry. gas/testsuite/ * gas/m68k/mcf-fpu.s: Add tests for all addressing modes. * gas/m68k/mcf-fpu.d: Update accordingly.
2006-07-192006-07-19 Paul Brook <paul@codesourcery.com>Paul Brook2-1/+5
gas/ * config/tc-arm.c (insns): Fix rbit Arm opcode. gas/testsuite/ * gas/arm/archv6t2.d: Adjust expected output for rbit. opcodes/ * armd-dis.c (arm_opcodes): Fix rbit opcode.
2006-07-18gas/testsuite/H.J. Lu2-3/+8
2006-07-18 H.J. Lu <hongjiu.lu@intel.com> * gas/i386/opcode.s: Add sldt, smsw and str. * gas/i386/x86-64-opcode.s: Likewise. * gas/i386/opcode.d: Updated. * gas/i386/x86-64-opcode.d: Likewise. opcodes/ 2006-07-18 H.J. Lu <hongjiu.lu@intel.com> * i386-dis.c (grps): Change "sldtQ", "strQ" and "smswQ" to "sldt", "str" and "smsw".
2006-07-15Add missing ChangeLog entry.H.J. Lu1-0/+17
2006-07-152006-07-15 H.J. Lu <hongjiu.lu@intel.com>H.J. Lu1-10/+34
PR binutils/2829 * i386-dis.c (GRP11_C6): NEW. (GRP11_C7): Likewise. (GRP12): Updated. (GRP13): Likewise. (GRP14): Likewise. (GRP15): Likewise. (GRP16): Likewise. (GRPAMD): Likewise. (GRPPADLCK1): Likewise. (GRPPADLCK2): Likewise. (dis386): Use GRP11_C6 and GRP11_C7 for entres 0xc6 and 0xc7, respectively. (grps): Add entries for GRP11_C6 and GRP11_C7.
2006-07-13Add amdfam10 instructionsMichael Meissner2-1000/+1077
2006-07-05 * arm-dis.c (coprocessor): Alter fmsrr disassembly syntax.Julian Brown2-1/+5
2006-06-12gas/testsuite/H.J. Lu2-2/+7
2006-06-12 H.J. Lu <hongjiu.lu@intel.com> * gas/i386/i386.exp: Run nops and x86-64-nops. * gas/i386/nops.d: New file. * gas/i386/nops.s: Likewise. * gas/i386/x86-64-nops.d: Likewise. * gas/i386/x86-64-nops.s: Likewise. include/opcode/ 2006-06-12 H.J. Lu <hongjiu.lu@intel.com> * i386.h (i386_optab): Add "nop" with memory reference. opcodes/ 2006-06-12 H.J. Lu <hongjiu.lu@intel.com> * i386-dis.c (dis386_twobyte): Use "nopQ" for 0x1f. (twobyte_has_modrm): Set 1 for 0x1f.
2006-06-12gas/H.J. Lu2-4/+29
2006-06-12 H.J. Lu <hongjiu.lu@intel.com> * config/tc-i386.c (process_suffix): Don't add rex64 for "xchg %rax,%rax". gas/testsuite/ 2006-06-12 H.J. Lu <hongjiu.lu@intel.com> * gas/i386/opcode.s: Add "xchg %ax,%ax". * gas/i386/opcode.d: Updated. * gas/i386/x86-64-opcode.s: Add xchg %ax,%ax, xchg %eax,%eax, xchg %rax,%rax, rex64 xchg %rax,%rax and xchg %rax,%r8. * gas/i386/x86-64-opcode.d: Updated. include/opcode/ 2006-06-12 H.J. Lu <hongjiu.lu@intel.com> * i386.h (i386_optab): Update comment for 64bit NOP. opcodes/ 2006-06-12 H.J. Lu <hongjiu.lu@intel.com> * i386-dis.c (NOP_Fixup): Removed. (NOP_Fixup1): New. (NOP_Fixup2): Likewise. (dis386): Use NOP_Fixup1 and NOP_Fixup2 on 0x90.
2006-06-12 * arm-dis.c (print_insn_neon): Disassemble 32-bit immediates as signedJulian Brown2-1/+8
on 64-bit hosts.
2006-06-102006-06-10 H.J. Lu <hongjiu.lu@intel.com>H.J. Lu2-14/+29
* i386.c (GRP10): Renamed to ... (GRP12): This. (GRP11): Renamed to ... (GRP13): This. (GRP12): Renamed to ... (GRP14): This. (GRP13): Renamed to ... (GRP15): This. (GRP14): Renamed to ... (GRP16): This. (dis386_twobyte): Updated. (grps): Likewise.
2006-06-09Updated Finnish translationNick Clifton2-184/+402
2006-06-07bfd/doc:Joseph Myers2-1/+5
* bfd.texinfo: Remove local @tex code. bfd: * po/Make-in (pdf, ps): New dummy targets. binutils: * po/Make-in (pdf, ps): New dummy targets. gas: * po/Make-in (pdf, ps): New dummy targets. gprof: * po/Make-in (pdf, ps): New dummy targets. ld: * po/Make-in (pdf, ps): New dummy targets. opcodes: * po/Make-in (pdf, ps): New dummy targets.
2006-06-072006-06-06 Paul Brook <paul@codesourcery.com>Paul Brook2-522/+707
opcodes/ * arm-dis.c (coprocessor_opcodes): Add %c to unconditional arm instructions. (neon_opcodes): Add conditional execution specifiers. (thumb_opcodes): Ditto. (thumb32_opcodes): Ditto. (arm_conditional): Change 0xe to "al" and add "" to end. (ifthen_state, ifthen_next_state, ifthen_address): New. (IFTHEN_COND): Define. (print_insn_coprocessor, print_insn_neon): Print thumb conditions. (print_insn_arm): Change %c to use new values of arm_conditional. (print_insn_thumb16): Print thumb conditions. Add %I. (print_insn_thumb32): Print thumb conditions. (find_ifthen_state): New function. (print_insn): Track IT block state. gas/testsuite/ * gas/arm/thumb2_bcond.d: Update expected output. * gas/arm/thumb32.d: Ditto. * gas/arm/vfp1_t2.d: Ditto. * gas/arm/vfp1xD_t2.d: Ditto. binutils/testsuite/ * binutils-all/arm/objdump.exp: New file. * binutils-all/arm/thumb2-cond.s: New test.
2006-06-07include/opcode/Alan Modra2-1/+13
* ppc.h (PPC_OPCODE_POWER6): Define. Adjust whitespace. gas/ * config/tc-ppc.c (parse_cpu): Handle "-mpower6". (md_show_usage): Document it. (ppc_setup_opcodes): Test power6 opcode flag bits. * doc/c-ppc.texi (PowerPC-Opts): Document "-mpower6". opcodes/ * ppc-dis.c (powerpc_dialect): Handle power6 option. (print_ppc_disassembler_options): Mention power6.
2006-06-06 [ gas/ChangeLog ]Thiemo Seufer3-2/+137
* config/tc-mips.c (ISA_SUPPORTS_DSP64): New macro. (CPU_HAS_MIPS3D, CPU_HAS_MDMX, CPU_HAS_DSP, CPU_HAS_MT): Delete. (macro_build): Update comment. (mips_ip): Allow DSP64 instructions for MIPS64R2. (mips_after_parse_args): Remove uses of CPU_HAS_MIPS3D and CPU_HAS_MDMX. (mips_cpu_info): Fix formatting. Add MIPS_CPU_ASE_MIPS3D and MIPS_CPU_ASE_MDMX flags for sb1. [ gas/testsuite/ChangeLog ] * gas/mips/mips64-dsp.s, gas/mips/mips64-dsp.d: New DSP64 tests. * gas/mips/mips.exp: Run DSP64 tests. [ opcodes/ChangeLog ] * mips-dis.c: Disassemble DSP64 instructions for MIPS64R2. * mips-opc.c: Add DSP64 instructions.
2006-06-06 * m68hc11-dis.c (print_insn): Warning fix.Alan Modra2-3/+8
2006-06-05bfd/, binutils/, gas/, gprof/, ld/, opcodes/Daniel Jacobowitz2-0/+5
* po/Make-in (top_builddir): Define.
2006-06-05 * Makefile.am: Run "make dep-am".Alan Modra4-116/+16
* Makefile.in: Regenerate. * config.in: Regenerate.
2006-05-31Configury changes: update src repository (binutils, gdb, and rda) to useDaniel Jacobowitz7-2788/+606
config/gettext-sister.m4 instead of the old gettext.m4. Regenerate all affected autotools files. Include intl in gdb releases again.
2006-05-30Update Spanish translationNick Clifton2-181/+396
2006-05-25include/opcodes/Richard Sandiford3-37/+81
* m68k.h (mcf_mask): Define. opcodes/ * m68k-opc.c (m68k_opcodes): Fix the masks of the Coldfire fmovemd and fmovem entries. Put register list entries before immediate mask entries. Use "l" rather than "L" in the fmovem entries. * m68k-dis.c (match_insn_m68k): Remove the PRIV argument and work it out from INFO. (m68k_scan_mask): New function, split out from... (print_insn_m68k): ...here. If no architecture has been set, first try printing an m680x0 instruction, then try a Coldfire one. gas/testsuite/ * gas/m68k/mcf-fpu.s: Add fmovemd and fmovem instructions. * gas/m68k/mcf-fpu.d: Adjust accordingly.
2006-05-24Updated Vietnamese and Irish translationsNick Clifton2-181/+396
2006-05-22* crx-dis.c (EXTRACT): Make macro work on 64-bit hosts.Nick Clifton2-1/+5
2006-05-22Updated Dutch translationNick Clifton2-194/+423
2006-05-22Remove ChangeLog entries, since the template files were already up to date.Nick Clifton1-4/+0
2006-05-22Update translation templatesNick Clifton1-0/+4
2006-05-17 * avr-dis.c: Formatting fix.Alan Modra2-2/+7
2006-05-14 [ gas/ChangeLog ]Thiemo Seufer2-134/+142
* config/tc-mips.c (macro_build): Test for currently active mips16 option. (mips16_ip): Reject invalid opcodes. [ opcodes/ChangeLog ] * mips16-opc.c (I1, I32, I64): New shortcut defines. (mips16_opcodes): Change membership of instructions to their lowest baseline ISA. [ gas/testsuite/ChangeLog ] * gas/mips/mips.exp: Run new tests. * gas/mips/mips16e.s, gas/mips/mips16e.d, gas/mips/mips16e-64.s, gas/mips/mips16e-64.d, gas/mips/mips16e-64.l: New tests.
2006-05-09gas/testsuite/H.J. Lu2-2/+6
2006-05-09 H.J. Lu <hongjiu.lu@intel.com> * gas/i386/i386.exp: Run x86-64-gidt. * gas/i386/x86-64-gidt.d: New file. * gas/i386/x86-64-gidt.s: Likewise. opcodes/ 2006-05-09 H.J. Lu <hongjiu.lu@intel.com> * i386-dis.c (grps): Update sgdt/sidt for 64bit.
2006-05-05 * arm-dis.c (coprocessor_opcodes): Don't interpret fldmx/fstmx asJulian Brown2-4/+9
vldm/vstm.
2006-05-05 [ gas/ChangeLog ]Thiemo Seufer2-0/+6
* config/tc-mips.c (macro_build): Add case 'k' to handle cache instruction. (macro): Add new case M_CACHE_AB. [ opcodes/ChangeLog ] * mips-opc.c: Add macro for cache instruction. [ include/opcode/ChangeLog ] * mips.h (enum): Add macro M_CACHE_AB.
2006-05-04[ gas/testsuite/ChangeLog ]Thiemo Seufer4-105/+160
2006-05-04 Thiemo Seufer <ths@mips.com> Nigel Stephens <nigel@mips.com> * gas/mips/mips.exp: Run mips32-dsp tests only for mips32r2. * gas/mips/set-arch.d: Adjust according to opcode table changes. [ include/opcode/ChangeLog ] 2006-05-04 Thiemo Seufer <ths@mips.com> Nigel Stephens <nigel@mips.com> David Ung <davidu@mips.com> * mips.h: Add INSN_SMARTMIPS define. [ opcodes/ChangeLog ] 2006-05-04 Thiemo Seufer <ths@mips.com> Nigel Stephens <nigel@mips.com> David Ung <davidu@mips.com> * mips-dis.c (mips_arch_choices): Add smartmips instruction decoding to MIPS32 and MIPS32R2. Limit DSP decoding to release 2 ISAs. Add MIPS3D decoding to MIPS32R2. Add MT decoding to MIPS64R2. * mips-opc.c: fix random typos in comments. (INSN_SMARTMIPS): New defines. (mips_builtin_opcodes): Add paired single support for MIPS32R2. Move bc3f, bc3fl, bc3t, bc3tl downwards. Move flushi, flushd, flushid, wb upwards. Move cfc3, ctc3 downwards. Rework the FP_S and FP_D flags to denote single and double register accesses separately. Move dmfc3, dmtc3, mfc3, mtc3 downwards. Allow jr.hb and jalr.hb for release 1 ISAs. Allow luxc1, suxc1 for MIPS32R2. Add SmartMIPS instructions. Add two-argument variants of bc2f, bc2fl, bc2t, bc2tl. Add mfhc2, mthc2 to release 2 ISAs. * mips16-opc.c (mips16_opcodes): Add sdbbp instruction.
2006-05-032006-05-03 Thiemo Seufer <ths@mips.com>Thiemo Seufer2-1/+5
[ opcodes/ChangeLog ] * mips-opc.c (mips_builtin_opcodes): Fix mftr argument order. [ gas/testsuite/ChangeLog ] * gas/mips/mips32-mt.d: Fix mftr argument order.
2006-05-02 * mips-dis.c (print_insn_args): Force mips16 to odd addresses.Thiemo Seufer2-3/+25
(print_mips16_insn_arg): Force mips16 to odd addresses.
2006-04-30[ gas/ChangeLog ]Thiemo Seufer3-0/+93
2006-04-30 Thiemo Seufer <ths@mips.com> David Ung <davidu@mips.com> * config/tc-mips.c (validate_mips_insn): Handling of udi cases. (mips_immed): New table that records various handling of udi instruction patterns. (mips_ip): Adds udi handling. [ include/opcode/ChangeLog ] 2006-04-30 Thiemo Seufer <ths@mips.com> David Ung <davidu@mips.com> * mips.h: Defines udi bits and masks. Add description of characters which may appear in the args field of udi instructions. [ opcodes/ChangeLog ] 2006-04-30 Thiemo Seufer <ths@mips.com> David Ung <davidu@mips.com> * mips-opc.c (mips_builtin_opcodes): Add udi instructions "udi0" to "udi15". * mips-dis.c (print_insn_args): Adds udi argument handling.
2006-04-29Fix buglet noticed while looking at PR 1298.Jim Wilson2-2/+9
* m68k-dis.c (match_insn_m68k): Restore fprintf_func before printing error message.
2006-04-28Don't mis-spell your boss' name...Thiemo Seufer1-4/+4
2006-04-28[ opcodes/ChangeLog ]Thiemo Seufer2-0/+28
2006-04-28 Thiemo Seufer <ths@mips.com> David Ung <davidu@mips.com> Nigel Stevens <nigel@mips.com> * mips-dis.c (mips_cp0sel_names_mips3264r2): Add MT register names. [ gas/testsuite/ChangeLog ] 2006-04-28 Thiemo Seufer <ths@mips.com> David Ung <davidu@mips.com> Nigel Stevens <nigel@mips.com> * gas/mips/cp0sel-names-mips32r2.d, gas/mips/cp0sel-names-mips64r2.d: Update for MT register names.
2006-04-28 * mips-dis.c (print_insn_args): Add mips_opcode argument.Thiemo Seufer2-2/+10
(print_insn_mips): Adjust print_insn_args call.
2006-04-28 * mips-dis.c (print_insn_args): Print $fcc only for FPThiemo Seufer2-1/+9
instructions, use $cc elsewise.
2006-04-28 * opcodes/mips-dis.c (mips16_to_32_reg_map, mips16_reg_names):Thiemo Seufer2-11/+21
Map MIPS16 registers to O32 names. (print_mips16_insn_arg): Use mips16_reg_names.
2006-04-26 * arm-dis.c (print_insn_neon): Disassemble floating-point constantJulian Brown2-2/+30
VMOV.
2006-04-26 * opcodes/arm-dis.c (coprocessor_opcodes): Add %A, %B, %k, convertJulian Brown2-368/+1096
%<code>[zy] into %[zy]<code>. Expand meaning of %<bitfield>['`?]. Add unified load/store instruction names. (neon_opcode_table): New. (arm_opcodes): Expand meaning of %<bitfield>['`?]. (arm_decode_bitfield): New. (print_insn_coprocessor): Add pc argument. Add %A & %B specifiers. Use arm_decode_bitfield and adjust numeric specifiers. Adjust %z & %y. (print_insn_neon): New. (print_insn_arm): Adjust print_insn_coprocessor call. Call print_insn_neon. Use arm_decode_bitfield and adjust numeric specifiers. (print_insn_thumb32): Likewise.
2006-04-19 * Makefile.am: Run "make dep-am".Alan Modra3-34/+43
* Makefile.in: Regenerate.
2006-04-19 * avr-dis.c (avr_operand): Warning fix.Alan Modra2-1/+3
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