aboutsummaryrefslogtreecommitdiff
path: root/opcodes
AgeCommit message (Expand)AuthorFilesLines
2015-06-22PPC sync instruction accepts invalid and incompatible operandsPeter Bergner2-13/+48
2015-06-22Stop "objdump -d" from disassembling past a symbolic address.Nick Clifton7-6/+33
2015-06-19Allow for optional operands with non-zero default values.Peter Bergner3-26/+34
2015-06-16[AArch64] Support id_mmfr4 system registerMatthew Wahab2-0/+5
2015-06-16Fixes a compile time warnng about left shifting a negative value.Szabolcs Nagy2-1/+5
2015-06-12Remove unused MTMSRD_L macro and re-add accidentally deleted comment.Peter Bergner2-2/+7
2015-06-04Add hwsync extended mnemonic.Peter Bergner1-0/+1
2015-06-04Fixes the check for emulated MSP430 instrucrtions that take no operands.Nick Clifton2-1/+6
2015-06-02[ARM] Support for ARMv8.1 Adv.SIMD extensionMatthew Wahab1-0/+19
2015-06-02[ARM] Add support for ARMv8.1 PAN extensionMatthew Wahab2-0/+10
2015-06-02[ARM] Rework CPU feature selection in the disassemblerMatthew Wahab2-29/+31
2015-06-02[AArch64] Support for ARMv8.1a Adv.SIMD instructionsMatthew Wahab5-1249/+1359
2015-06-02[AArch64] Support for ARMv8.1a Limited Ordering Regions extensionMatthew Wahab5-401/+478
2015-06-01[AArch64][libopcode] Add support for PAN architecture extensionMatthew Wahab2-0/+46
2015-06-01x86/Intel: fix i386_optab[] for vcvt{,u}si2s{d,s}Jan Beulich2-6/+10
2015-06-01x86/Intel: disassemble vcvt{,u}si2s{d,s} with correct operand orderJan Beulich2-0/+12
2015-06-01x86/Intel: accept mandated operand order for vcvt{,u}si2s{d,s}Jan Beulich3-0/+143
2015-05-18Remove Disp32 from AMD64 direct call/jmpH.J. Lu3-4/+9
2015-05-15Support AMD64/Intel ISAs in assembler/disassemblerH.J. Lu7-5296/+5387
2015-05-14Fix some PPC assembler errors.Peter Bergner2-3/+15
2015-05-13Add missing ChangeLog entries for PR binutis/18386H.J. Lu1-0/+13
2015-05-11Remove Disp16|Disp32 from 64-bit direct branchesH.J. Lu3-5/+26
2015-05-11Add Intel MCU support to opcodesH.J. Lu8-5817/+5853
2015-05-09Ignore 0x66 prefix for call/jmp/jcc in 64-bit modeH.J. Lu1-10/+40
2015-04-30Make RL78 disassembler and simulator respect ISA for mul/divDJ Delorie5-447/+509
2015-04-29Updated translations for various binutils components.Nick Clifton2-481/+708
2015-04-27opcodes/Peter Bergner2-12/+34
2015-04-27S/390: Fixes for z13 instructions.Andreas Krebbel3-5/+13
2015-04-23x86: disambiguate disassembly of certain AVX512 insnsJan Beulich3-13/+52
2015-04-15Remove the unused PREFIX_UD_XXXH.J. Lu2-6/+9
2015-04-15Check dp->prefix_requirement insteadH.J. Lu2-5/+7
2015-04-15Handle invalid prefixes for rdrand and rdseedH.J. Lu2-5/+35
2015-04-15Replace mandatory_prefix with prefix_requirementH.J. Lu2-310/+349
2015-04-15[ARM] Disassembles SSAT and SSAT16 instructions incorrectly for Thumb-2Renlin Li2-2/+14
2015-04-06x86: Use individual prefix control for each opcode.Ilya Tocar3-1914/+1941
2015-03-30opcodes: d10v: fix old style prototypeMike Frysinger2-1/+5
2015-03-29Add the missing opcodes/ChangeLog entryH.J. Lu1-0/+4
2015-03-29Regenerate opcodes/Makefile.inH.J. Lu1-1/+0
2015-03-26powerpc: Only initialise opcode indices onceAnton Blanchard2-25/+34
2015-03-26powerpc: Add slbfee. instructionAnton Blanchard2-0/+6
2015-03-24Extend arm_feature_set struct to provide more bitsTerry Guo2-1294/+2543
2015-03-17Add znver1 processorGanesh Gopalasubramanian7-5283/+5339
2015-03-13MIPS: Fix constraint issues with the R6 beqc and bnec instructionsAndrew Bennett2-2/+7
2015-03-13Add support for MIPS R6 evp and dvp instructions.Andrew Bennett2-0/+8
2015-03-10S/390: Add more IBM z13 instructionsAndreas Krebbel3-0/+30
2015-03-10[AARCH64] Remove Load/Store register (unscaled immediate) alias.Jiong Wang5-490/+439
2015-03-03[ARM] Skip private symbol when doing objdumpJiong Wang2-2/+9
2015-02-25[SH] Fix clrs, sets, pref insn arch memberships.Oleg Endo2-3/+10
2015-02-23Adds a space between the operands of the RL78's MOV instruction for consisten...Vinay3-8/+14
2015-02-19Wrap a few opcodes headers in extern "C" for C++Pedro Alves2-0/+12
generated by cgit v1.1 at 2024-11-26 03:46:50 +0000