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1996-11-20 * mn10300-dis.c (disassemble): Handle register lists.Jeff Law2-0/+47
More disassembler stuff.
1996-11-20 * mn10300-opc.c: Fix handling of register list operand forJeff Law2-9/+12
"call", "ret", and "rets" instructions. Stuff noticed while working on disasembler.
1996-11-20 * mn10300-dis.c (disassemble): Print PC-relative and memoryJeff Law3-41/+67
addresses symbolically if possible. * mn10300-opc.c: Distinguish between absolute memory addresses, pc-relative offsets & random immediates. More disassembler work.
1996-11-20 * mn10300-dis.c (print_insn_mn10300): Fix fetch of last byteJeff Law2-4/+27
in 7 byte insns. (disassemble): Handle SPLIT and EXTENDED operands.
1996-11-20 * mn10300-dis.c: Rough cut at printing some operands.Jeff Law2-19/+86
1996-11-19 * mn10300-dis.c: Start working on disassembler support.Jeff Law3-9/+276
* mn10300-opc.c (mn10300_opcodes): Fix masks on several insns. Selects opcodes & consumes bytes. Breaks badly if given data instead of code. No operands yet.
1996-11-19 * mn10300-opc.c (mn10300_operands): Add "REGS" for a registerJeff Law2-2/+11
list. (mn10300_opcodes): Use REGS for register list in "movm" instructions.
1996-11-18Add3 sets the carryMichael Meissner1-0/+6
1996-11-15 * mn10300-opc.c (mn10300_opcodes): Demand parens aroundJeff Law2-2/+12
register argument is calls and jmp instructions. Found trying to build libgcc2 for the mn10300 :-)
1996-11-07 * mn10300-opc.c (mn10300_opcodes): Use DN01 for putx andJeff Law1-5/+5
getx operand. Fix opcode for mulqu imm,dn. Fix bugs exposed by gas testsuite (extended instructions).
1996-11-06 * mn10300-opc.c (mn10300_operands): Hijack "bits" fieldJeff Law2-8/+41
in MN10300_OPERAND_SPLIT operands for how many bits appear in the basic insn word. Add IMM32_HIGH24, IMM32_HIGH24_LOWSHIFT8, IMM8E_SHIFT8. (mn10300_opcodes): Use new operands as needed. Support for everything in the basic instruction manual (yippie!)
1996-11-06 * mn10300-opc.c (mn10300_operands): Add IMM32_LOWSHIFT8Jeff Law2-5/+20
for bset, bclr, btst instructions. (mn10300_opcodes): Use new IMM32_LOWSHIFT8 as needed. For btst, bclr & bset.
1996-11-06 * mn10300-opc.c (mn10300_operands): Remove many redundantJeff Law2-77/+69
operands. Update opcode table as appropriate. (IMM32): Add MN10300_OPERAND_SPLIT flag. (mn10300_opcodes): Fix single bit error in mov imm32,dn insn. Cleaning up a little. Attempting to insert most 32bit operands. And a bug found by assembler testsuite.
1996-11-05 * mn10300-opc.c (mn10300_operands): Add DN2, DM2, AN2, AM2Jeff Law2-20/+57
operands (for indexed load/stores). Fix bitpos for DI operand. Add SN8N_SHIFT8, IMM8_SHIFT8, and D16_SHIFT for the few instructions that insert immediates/displacements in the middle of the instruction. Add IMM8E for 8 bit immediate in the extended part of an instruction. (mn10300_operands): Use new opcodes as appropriate. Opcode table changes so we can correctly insert everything except 32bit operands.
1996-11-05Tue Nov 5 10:30:51 1996 Martin M. Hunt <hunt@pizza.cygnus.com>Martin Hunt1-0/+8
* d10v-opc.c (d10v_opcodes): Declare the trap instruction sequential so the assembler never parallelizes it with other instructions.
1996-11-04 * mn10300-opc.c (mn10300_operands): Add DN01 and AN01 forJeff Law2-4/+18
a data/address register that appears in register field 0 and register field 1. (mn10300_opcodes): Use DN01 and AN01 for mov/cmp imm8,DN/AN Hacking Matsushita again. Yippie!
1996-11-01Fri Nov 1 10:29:11 1996 Richard Henderson <rth@tamu.edu>Ian Lance Taylor1-0/+9
* alpha-dis.c (print_insn_alpha): Use new NOPAL mask for standard disassembly. * alpha-opc.c (alpha_operands): Rearrange flags slot. (alpha_opcodes): Add new BWX, CIX, and MAX instructions. Recategorize PALcode instructions.
1996-10-30 * v850-opc.c (v850_opcodes): Add relaxing "jbr".Jeff Law1-0/+6
1996-10-29 * mips-dis.c (_print_insn_mips): Don't print a trailing tab ifIan Lance Taylor1-0/+5
there are no operand types.
1996-10-29 * v850-opc.c (D9_RELAX): Renamed from D9, all referencesJeff Law2-13/+35
changed. (v850_operands): Make sure D22 immediately follows D9_RELAX.
1996-10-24 * v850-opc.c (v850_opcodes): Add "jCC" instructions (aliases forJeff Law2-1/+33
"bCC"instructions). Because quantum's code uses jnz, jcc, etc etc etc.
1996-10-24 * mips-dis.c (_print_insn_mips): Use a tab between the instructionIan Lance Taylor1-0/+5
and the arguments.
1996-10-23 * ppc-opc.c (PPCPWR2): Define.Ian Lance Taylor1-0/+6
(powerpc_opcodes): Use PPCPWR2 for fsqrt, rather than duplicating it.
1996-10-11 * mn10300-opc.c (mn10300_opcodes): Fix typo in opcodeJeff Law2-1/+12
field for movhu instruction. Bug found by gas testsuite. * v850-dis.c (disassemble): For V850_OPERAND_SIGNED operands, cast value to "long" not "signed long" to keep hpux10 compiler quiet. Found in an attempt to build the v850 on hpux10 with the HP compiler.
1996-10-10 * mn10300-opc.c (mn10300_opcodes): Fix typo in opcode fieldJeff Law1-0/+3
for mov (abs16),DN. Bug found by gas testsuite. Matsushita.
1996-10-10 * mn10300-opc.c (FMT*): Remove definitions.Jeff Law2-15/+2
Moved into opcode/mn10300.h
1996-10-10 * mn10300-opc.c (mn10300_opcodes): Fix destination registerJeff Law2-3/+6
for shift-by-register opcodes. Bug found by testsuite.
1996-10-10 * mn10300-opc.c (mn10300_operands): Break DN, DM, AN, AMJeff Law2-200/+218
into [AD][MN][01] for encoding the position of the register in the opcode. Matsushita.
1996-10-09 * mn10300-opc.c (mn10300_opcodes): Add "extended" instructions,Jeff Law2-0/+19
"putx", "getx", "mulq", "mulqu", "sat16", "sat24", "bsch". Matsushita.
1996-10-08 * mn10300-opc.c (mn10300_operands): Remove "REGS" operand.Jeff Law2-245/+253
Fix various typos. Add "PAREN" operand. (MEM, MEM2): Define. (mn10300_opcodes): Surround all memory addresses with "PAREN" operands. Fix several typos. Should parse all opcodes in the instruction specification, except the "user extension instructions".
1996-10-08 * mn10300-opc.c (mn10300_opcodes): Fix typos in yesterday'sJeff Law2-2/+7
changes. Matsushita.
1996-10-07 * mn10300-opc.c (FMT_XX): Renumber starting at one.Jeff Law2-268/+328
(mn10300_operands): Rough cut. Enough to parse "mov" instructions at this time. (mn10300_opcodes): Break opcode format out into its own field. Update many operand fields to deal with signed vs unsigned issues. Fix one or two typos in the "mov" instruction opcode, mask and/or operand fields. Checkpointing today's work. Matsushita.
1996-10-07Mon Oct 7 11:39:49 1996 Andreas Schwab ↵Ian Lance Taylor1-0/+5
<schwab@issan.informatik.uni-dortmund.de> * m68k-opc.c (plusha): Prefer encoding for m68040up, in case m68851 wasn't reset.
1996-10-04 * mn10300-opc.c (mn10300_opcodes): Add opcode & masks forJeff Law2-248/+275
all opcodes. Very rough cut at operands for all opcodes. Matsushita.
1996-10-04 * mn10300-opc.c (mn10300_opcodes): Start fleshing out theJeff Law2-3/+252
opcode table. Checkpointint 10300 work.
1996-10-03 * Makefile.in (ALL_MACHINES): Add mn10200-dis.o, mn10200-opc.o,Ian Lance Taylor2-1/+6
mn10300-dis.o, and mn10300-opc.o. Also add d10v and v850 files, with appropriate sanitization.
1996-10-03Grrr. The mn10200 and mn10300 are _not_ similar enough to easily supportJeff Law6-9/+108
with a single generic configuration. So break them up into two different configurations. See the individual ChangeLogs for additional detail.
1996-10-03 * Makefile.in (MOSTLYCLEAN): Move config.log to distclean.Jason Molenda2-17/+21
1996-10-03 * mn10x00-opc.c, mn10x00-dis.c: New files for MatsushitaJeff Law6-18/+129
MN10x00 processors. * disassemble (ARCH_mn10x00): Define. (disassembler): Handle bfd_arch_mn10x00. * configure.in: Recognize bfd_mn10x00_arch. * configure: Rebuilt. Continue stubbing out for Matsushita work.
1996-10-03Add missing copyright.Jeff Law1-5/+23
1996-10-01 * i386-dis.c (op_rtn): Change to be a pointer. Adjust usesIan Lance Taylor1-0/+23
accordingly. Don't declare functions using op_rtn. Remove ANSI C constructs.
1996-09-17 * mips-opc.c: Add a case for "div" and "divu" with two registersIan Lance Taylor1-0/+5
and a destination of $0. PR 10654.
1996-09-11 * mips-dis.c (print_insn_arg): Add prototype.Fred Fish1-0/+5
(_print_insn_mips): Ditto.
1996-09-09 * mips-dis.c (print_insn_arg): Print condition code registers asIan Lance Taylor2-31/+85
$fccN.
1996-09-03 * v850-dis.c (disassemble): Make static. Provide prototype.Jeff Law1-0/+9
1996-09-02whoops--typoIan Lance Taylor1-0/+27
1996-09-02file was really removed a long time agoIan Lance Taylor2-32/+0
1996-08-31 * v850-dis.c (disassemble): Handle insertion of ',', '[' andJeff Law2-80/+89
']' characters into the output stream. * v850-opc.c (v850_opcodes: Remove size field from all opcodes. Add "memop" field to all opcodes (for the disassembler). Reorder opcodes so that "nop" comes before "mov" and "jr" comes before "jarl". Should give us a functional disassembler.
1996-08-31 * v850-dis.c (print_insn_v850): Properly handle disassemblingJeff Law2-2/+21
a two byte insn at the end of a memory region when the memory region's size is only two byte aligned.
1996-08-31 * v850-dis.c (v850_cc_names): Fix stupid thinkos.Jeff Law2-2/+3
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