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1998-07-08 * m10300-dis.c (disassemble): When printing RREGs and XRREGs, mapJeff Law1-0/+7
from raw register #s to symbolic names to make debugging easier.
1998-07-03 * m32r-opc.h (CGEN_MIN_INSN_SIZE): New #define.Doug Evans1-0/+4
1998-07-01 * Makefile.am (CGENDIR): Set via configure.Doug Evans4-84/+86
(CGEN): New variable. (CGENFILES): object.scm renamed to cos.scm. (run-cgen): Renamed from cgen. stamp file renamed to stamp-$prefix. (stamp-m32r): Pass prefix to run-cgen. * Makefile.in: Regenerate. * cgen-asm.in: @arch@-opc.h renamed to @prefix@-opc.h. * cgen-dis.in: Ditto. * cgen-opc.in: Ditto. * cgen.sh: New args cgen,prefix. Delete args scheme,schemeflags. * configure.in: AC_SUBST cgen,cgendir. No longer look for guile. * configure: Regenerate. * m32r-asm.c,m32r-dis.c,m32r-opc.c,m32r-opc.h: Regenerate.
1998-07-01 * dvp-opc.c (DVP_OPERAND_RELOC_11_S4): Temporarily back outDoug Evans1-0/+15
the DVP_OPERAND_RELOC_11_S4 relocation. * dvp-opc.c (LIMM11, LUIMM15): New symbol types DVP_OPERAND_RELOC_U15_S3 and DVP_OPERAND_RELOC_11_S4 to allow labels to be used as immediate values.
1998-07-01Replace object.scm with cos.scmNick Clifton2-1/+5
1998-06-30 * m10300-opc.c: Reorder "movbu" and "movhu" instructions too.Jeff Law2-34/+42
Why oh why didn't they take our advice about register prefixing. It would have avoided the ambigious syntax issues. Sigh.
1998-06-29 * m10300-opc.c: Reorder more instructions so that we do notJeff Law2-33/+54
accidentally match a mn10300 instruction when we really wanted an am33 instruction.
1998-06-26 * m10300-dis.c: Only recognize instructions from the currentlyJeff Law3-698/+720
selected machine. * m10300-opc.c: Add field indicating the particular variant of the mn10300 each instruction is available on.
1998-06-26 * configure.in: For bfd_vax_arch, build vax-dis.lo.Ian Lance Taylor7-211/+588
* Makefile.am: Rebuild dependencies. (CFILES): Add vax-dis.c. (ALL_MACHINES): Add vax-dis.lo. * aclocal.m4: Rebuild with current libtool. * configure, Makefile.in: Rebuild. Fri Jun 26 12:03:20 1998 Klaus Kaempf <kkaempf@progis.de> * vax-dis.c: New file, from work by Pauline Middelink <middelin@polyware.iaf.nl>. * disassemble.c (ARCH_vax): Define if ARCH_all. (disassembler): Add case for ARCH_vax. * makefile.vms: Support compilation on vms/vax.
1998-06-24 * m10300-dis.c (print_insn_mn10300): 0xf7 opcode prefix specifiesJeff Law2-4/+12
4 byte instructions. (disassemble): Correctly handle FMT_D10 instructions.
1998-06-24 * mn10300-opc.c (mn10300_opcodes): Fix typo in IMM24 versions of theJeff Law2-3/+6
am33 shift instructions.
1998-06-24 * mn10300-dis.c (print_insn_mn10300): 0xf9 opcode prefix specifiesJeff Law3-1/+693
3 byte instructions. (disassemble): Handle new instruction formats FMT_D6, FMT_D7, FMT_D8 FMT_D9 and FMT_D10. Handle various new opcode flags for the am33.
1998-06-24 * mn10300-opc.c (IMM32_HIGH8_MEM): New operand type.Jeff Law2-95/+169
(mn10300_opcodes): Reorder so as to try and select opcodes from the core chip when multiple alternatives exist. Change several am33 instructions to use IMM32_HIGH8_MEM. Fix typos in "mac" and "macbu" instructions. Fix typos in a couple DSP instructions too.
1998-06-24 * m10200-dis.c (print_insn_mn10200): Fix various non-portabilitiesMark Alexander1-0/+5
related to sign extension and the size of ints.
1998-06-23 * m10300-opc.c: Support one operand "asr", "lsr" and "asl"Jeff Law2-0/+17
instructions. Support (sp) addressing mode by expanding it into (0,sp).
1998-06-22 * m10300-opc.c: Support 4 byte DSP instructions.Jeff Law2-45/+550
1998-06-19 * m10300-opc.c: Support 6 and 7 byte am33 instructions.Jeff Law1-0/+6
1998-06-19 * m10200-dis.c (print_insn_mn10200): Recognize 'break' pseudo-op.Mark Alexander2-0/+344
1998-06-19 * m10300-opc.c: Support for 3 byte and 4 byte extended instructionsJeff Law2-10/+279
found on the mn10300.
1998-06-19formatting fixesIan Lance Taylor1-23/+32
1998-06-19Update.Ulrich Drepper1-66/+71
1998-06-18Fix compile errors in set_mips_isa_typeJohn Metzler1-2/+3
1998-06-18*** empty log message ***John Metzler1-11/+14
1998-06-18Rework ChangeLog entry to avoid mentioning vr5400 in a r5900 entry.Jeff Law1-2/+1
1998-06-18 * mips-dis.c (print_insn_little_mips): Previously, instructionJohn Metzler2-36/+98
printing references the symbol table to determine whether the instruction resides in a block regular instructions or mips16 instructions. However, when the disassembler gets used in other environments where the symbol table is not present, we no longer rely in the symbol table, rather, use the low bit of the instructions address to guess. There should be no change for usage of the disassembler in host based programse, gdb ,objdump. (print_insn_big_mips): ditto. (print_insn_mips): ditto
1998-06-18tipoIan Lance Taylor1-1/+1
1998-06-17start-sanitize-am33Jeff Law3-0/+626
* m10300-opc.c (USP, SSP, MSP, PC, IMM4, EPSW, RN0, RM1): New operands for the am33. (mn10300_opcodes): Add new instructions from the am33. end-sanitize-am33 * m10300-opc.c (mn10300_opcodes): Change opcode for "syscall". Snapshot current work.
1998-06-16Tue Jun 16 13:10:51 1998 Alan Modra <alan@spri.levels.unisa.edu.au>Ian Lance Taylor1-0/+5
* i386-dis.c (index16): Add '%' to register names. Use ',' instead of '+'.
1998-06-13Sat Jun 13 11:33:55 1998 Alan Modra <alan@spri.levels.unisa.edu.au>Ian Lance Taylor2-220/+313
* i386-dis.c: Don't print opcode suffix when we can figure out the size (and gas can!) by register operands, or from the default size. (putop): Handle 'A', 'B', 'L', 'P', 'Q', 'R' macros. Rename 'C' macro to 'E'. (dis386, dis386_twobyte, grps): Use new suffix macros. (dis386): Correct imul Ib to imul sIb. Change jnl to jge to be consistent. Add suffix for call, jmp, lcall, ljmp, iret. Reverse order of cmps operands to agree with Intel docs. Correct operand of aad and aam (Ib -> sIb). Change ud2b from 0fb8 to 0fb9 to agree with Intel docs. (print_insn_x86): Print orphan fwait before other prefixes. Return correct byte count for orphan fwait with prefixes. Don't print `bound' operands in reverse order. (ckprefix): Stop accumulating prefixes if we get fwait. (OP_DIR): Print `$' before Ap operands of ljmp, lcall.
1998-06-12 * po/Make-in (all-yes): If maintainer mode, depend on .pot file.Tom Tromey1-0/+5
($(PACKAGE).pot): Unconditionally depend on POTFILES.
1998-06-12Fri Jun 12 11:04:06 1998 Andreas Schwab ↵Ian Lance Taylor2-7/+31
<schwab@issan.informatik.uni-dortmund.de> Fix problems when bfd_vma is wider than long. * i386-dis.c: Make op_address and start_pc unsigned. (set_op): Make parameter unsigned. (print_insn_x86): Cast to bfd_vma when passing a value to print_address_func. * ns32k-dis.c (CORE_ADDR): Don't define. (print_insn_ns32k): Change type of addr to bfd_vma. Use bfd_scan_vma to read back address. (print_insn_arg): Change type of addr to bfd_vma. Use sprintf_vma to format it. * m68k-dis.c (COERCE32): Cast to bfd_signed_vma to avoid overflow. (NEXTULONG): New definition. (print_insn_m68k): Avoid overflow when computing third argument of print_insn_arg. (print_insn_arg): Use NEXTULONG to fetch 32 bit address values. Use disp instead of val to store offset values. (print_indexed): Use base_disp instead of word to store base displacement, to avoid overflow. * m10300-dis.c (disassemble): Cast value to long when computing pc-relative address, to get correct sign extension.
1998-06-10 * m32r-opc.c: Regenerate.Doug Evans1-0/+4
Updates from better VoidMode handling in cgen.
1998-06-09Disassemble 'add rX, rY, #0' as 'mov rX, rY'.Nick Clifton2-0/+6
1998-06-09Fix for PR16116 - remove FLAG_MUL32 attribute from MULX2H insn.Nick Clifton1-0/+4
1998-06-06Fri Jun 5 23:47:55 1998 Alan Modra <alan@spri.levels.unisa.edu.au>Ian Lance Taylor2-227/+238
* i386-dis.c: Combine aflag and dflag into sizeflag. Change OP_* functions to void. (OP_DSreg): Rename from OP_DSSI. (OP_ESreg): Rename from OP_ESDI. (Xb, Xv, Yb, Yv): Use index reg code, not b_mode or v_mode. (DSBX): Define. (append_seg): Rename from append_prefix. (ptr_reg): New function. (dis386): Add S suffix to pushf, popf, ret, lret, enter, leave. Add DSBX for xlat. (PREFIX_ADDR): Rename from PREFIX_ADR. (float_reg): Add non-broken opcodes for people who don't want UNIXWARE_COMPAT.
1998-06-05Fri Jun 5 19:15:04 1998 Andreas Schwab ↵Ian Lance Taylor1-0/+5
<schwab@issan.informatik.uni-dortmund.de> * m68k-opc.c (tstb, tstw, tstl): Don't allow pcrel on 68000/68008/68010.
1998-06-03xIan Lance Taylor1-0/+4
1998-06-02Tue Jun 2 15:06:46 1998 Geoff Keating <geoffk@ozemail.com.au>Ian Lance Taylor1-0/+6
* ppc-opc.c (powerpc_macros): Support shifts and rotates of size 0; produce error message for shifts of size 32 (or 64 for 64-bit shifts), because the hardware doesn't support them.
1998-06-01 * mips-opc.c (c.lt.s): Remove r5900 specific variant.Jeff Law1-0/+3
(c.le.s): Likewise.
1998-06-01 * vu0.h (sqc2): Fix opcode.Jeff Law2-1/+3
1998-06-01 * mips-opc.c (rsqrt.s): Update based on r5900 ISA manual version 2.1Jeff Law2-9/+38
(sqrt.s): Likewise.
1998-05-27sparclite 86x big endian instruction / little endian data support.Stan Cox1-0/+9
1998-05-26Fix PR15984 - Add flags to various opcodesNick Clifton2-4/+9
1998-05-26Fix Pr15998 - Make SHORT_B3(b) formats examin but not modify their first ↵Nick Clifton2-52/+62
register argument.
1998-05-22 * cgen-asm.in (insert_normal): Handle empty fields and 64 bit hosts.Doug Evans2-26/+42
* cgen-dis.in (extract_normal): Likewise. * m32r-asm.c,m32r-dis.c: Regenerate.
1998-05-22 * cgen-asm.in (insert_normal): Handle empty fields and 64 bit hosts.Doug Evans1-0/+5
* cgen-dis.in (extract_normal): Likewise.
1998-05-22 * dvp-opc.c (parse_dotdest): Missing dest -> xyzw.Doug Evans1-0/+6
1998-05-20 * mips-opc.c (multu1): Add two operand variant for the r5900.Jeff Law1-0/+6
1998-05-19 * mips-dis.c (print_mips16_insn_arg): Handle type ']' correctlyIan Lance Taylor1-0/+5
with a shift count of 0.
1998-05-18* Followup for SCEI PR 15853: 2-operand R5900 "mult1" instruction.Frank Ch. Eigler2-0/+5
Mon May 18 14:27:06 1998 Frank Ch. Eigler <fche@cygnus.com> * mips-opc.c (mult1): Add two-operand variety of mult1 for R5900.
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