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2007-05-24 * regenerated files from updating libtool.Steve Ellcey3-1054/+13125
2007-05-24 * ltmain.sh: Update from GCC.Steve Ellcey1-0/+6
* libtool.m4: Update from GCC. * ltsugar.m4: New. Update from GCC. * ltversion.m4: New. Update from GCC. * ltoptions.m4: New. Update from GCC. * ltconfig: Remove. * ltcf-c.sh: Remove. * ltcf-cxx.sh: Remove. * ltcf-gcj.sh: Remove. * src-release: Update with new libtool file list. * newlib/*/configure.in: invoke _LD_DECL_SED. * newlib/*/Makefile.am: Ensure toplevel is included in ACLOCAL_AMFLAGS. * Regenerate subdirectories
2007-05-18 * ppc-dis.c (print_insn_powerpc): Don't skip all operandsAlan Modra2-9/+16
after setting skip_optional.
2007-05-17 * ppc-dis.c (operand_value_powerpc, skip_optional_operands): New.Peter Bergner3-30/+91
(print_insn_powerpc): Use the new operand_value_powerpc and skip_optional_operands functions to omit or print all optional operands as a group. * ppc-opc.c (BFF, W, XFL_L, XWRA_MASK): New. (XFL_MASK): Delete L and W bits from the mask. (mtfsfi, mtfsfi.): Replace use of BF with BFF. Relpace use of XRA_MASK with XWRA_MASK. Use W. (mtfsf, mtfsf.): Use XFL_L and W.
2007-05-15gas/testsuite/H.J. Lu2-1/+6
2007-05-14 H.J. Lu <hongjiu.lu@intel.com> PR binutils/4502 * gas/i386/amd.d: Replace "pfmulhrw" with "pmulhrw". opcodes/ 2007-05-14 H.J. Lu <hongjiu.lu@intel.com> PR binutils/4502 * i386-dis.c (Suffix3DNow): Replace "pfmulhrw" with "pmulhrw".
2007-05-102007-05-10 H.J. Lu <hongjiu.lu@intel.com>H.J. Lu2-27/+57
* i386-opc.h (ShortForm): Redefined. (Jump): Likewise. (JumpDword): Likewise. (JumpByte): Likewise. (JumpInterSegment): Likewise. (FloatMF): Likewise. (FloatR): Likewise. (FloatD): Likewise. (Size16): Likewise. (Size32): Likewise. (Size64): Likewise. (IgnoreSize): Likewise. (DefaultSize): Likewise. (No_bSuf): Likewise. (No_wSuf): Likewise. (No_lSuf): Likewise. (No_sSuf): Likewise. (No_qSuf): Likewise. (No_xSuf): Likewise. (FWait): Likewise. (IsString): Likewise. (regKludge): Likewise. (IsPrefix): Likewise. (ImmExt): Likewise. (NoRex64): Likewise. (Rex64): Likewise. (Ugh): Likewise.
2007-05-072007-05-07 H.J. Lu <hongjiu.lu@intel.com>H.J. Lu2-2/+8
* i386-dis.c (threebyte_0x38_uses_DATA_prefix): Correct entries for some SSE4 instructions. (threebyte_0x3a_uses_DATA_prefix): Likewise.
2007-05-03gas/H.J. Lu3-4/+17
2007-05-03 H.J. Lu <hongjiu.lu@intel.com> * config/tc-i386.c (match_template): Don't explicitly check suffix for crc32 in Intel mode. (process_suffix): Issue an error for crc32 if the operand size is ambiguous. gas/testsuite/ 2007-05-03 H.J. Lu <hongjiu.lu@intel.com> * gas/i386/crc32-intel.d: Updated. * gas/i386/crc32.d: Likewise. * gas/i386/sse4_2.d: Likewise. * gas/i386/x86-64-crc32-intel.d: Likewise. * gas/i386/x86-64-crc32.d: Likewise. * gas/i386/x86-64-sse4_2.d: Likewise. * gas/i386/crc32.s: Remove crc32 instructions with ambiguous operand size and suffix in crc32 instructions in Intel mode. * gas/i386/x86-64-crc32.s: Likewise. * gas/i386/sse4_2.s: Remove crc32 instructions with ambiguous operand size. * gas/i386/x86-64-sse4_2.s: Likewise. * gas/i386/i386.exp: Run inval-crc32 and x86-64-inval-crc32. * gas/i386/inval-crc32.l: New. * gas/i386/inval-crc32.s: Likewise. * gas/i386/x86-64-inval-crc32.l: Likewise. * gas/i386/x86-64-inval-crc32.s: Likewise. opcodes/ 2007-05-03 H.J. Lu <hongjiu.lu@intel.com> * i386-dis.c (CRC32_Fixup): Don't print suffix in Intel mode. * i386-opc.c (i386_optab): Remove IgnoreSize and correct operand type for crc32.
2007-05-01gas/config/H.J. Lu3-9/+17
2007-05-01 H.J. Lu <hongjiu.lu@intel.com> * config/tc-i386.c (match_template): Check suffix for crc32 in Intel mdoe. (process_suffix): Default the suffix of 8bit crc32 to BYTE_MNEM_SUFFIX. (check_byte_reg): Skip check for 8bit crc32. gas/testsuite/ 2007-05-01 H.J. Lu <hongjiu.lu@intel.com> * gas/i386/crc32-intel.d: New file. * gas/i386/crc32.d:Likewise. * gas/i386/crc32.s:Likewise. * gas/i386/x86-64-crc32-intel.d:Likewise. * gas/i386/x86-64-crc32.d:Likewise. * gas/i386/x86-64-crc32.s:Likewise. * gas/i386/i386.exp: Run crc32, crc32-intel, x86-64-crc32 and x86-64-crc32-intel. opcodes/ 2007-05-01 H.J. Lu <hongjiu.lu@intel.com> * i386-dis.c (CRC32_Fixup): Properly handle Intel mode and check data size prefix in 16bit mode. * i386-opc.c (i386_optab): Default crc32 to non-8bit and support Intel mode.
2007-04-30Support new FR-V SPRsMark Salter3-12/+51
2007-04-30opcodes/Alan Modra2-1/+6
PR 4436 * ppc-opc.c (powerpc_operands): Correct bitm for second entry of MBE. gas/ PR 4436 * config/tc-ppc.c (ppc_insert_operand): Disable range check if min > max.
2007-04-272007-04-27 H.J. Lu <hongjiu.lu@intel.com>H.J. Lu2-1/+5
* i386-dis.c (modrm): Put reg before rm.
2007-04-27gas/testsuite/H.J. Lu2-10/+69
2007-04-26 H.J. Lu <hongjiu.lu@intel.com> PR binutils/4430 * gas/i386/amd.d: Updated. * gas/i386/immed32.d: Likewise. * gas/i386/intel.d: Likewise. * gas/i386/intel16.d: Likewise. * gas/i386/intelok.d: Likewise. * gas/i386/jump16.d: Likewise. * gas/i386/naked.d: Likewise. * gas/i386/opcode-suffix.d: Likewise. * gas/i386/opcode.d: Likewise. * gas/i386/prescott.d: Likewise. * gas/i386/ssemmx2.d: Likewise. * gas/i386/tlsd.d: Likewise. * gas/i386/tlspic.d: Likewise. * gas/i386/x86-64-addr32.d: Likewise. * gas/i386/x86-64-prescott.d: Likewise. * gas/i386/x86-64-rip.d: Likewise. * gas/i386/x86_64.d: Likewise. ld/testsuite/ 2007-04-26 H.J. Lu <hongjiu.lu@intel.com> PR binutils/4430 * ld-i386/tlsbin.dd: Updated. * ld-i386/tlsbindesc.dd: Likewise * ld-i386/tlsdesc.dd: Likewise * ld-i386/tlsgdesc.dd: Likewise * ld-i386/tlsnopic.dd: Likewise * ld-i386/tlspic.dd: Likewise * ld-x86-64/tlsbin.dd: Likewise * ld-x86-64/tlsbindesc.dd: Likewise * ld-x86-64/tlsdesc.dd: Likewise * ld-x86-64/tlsgdesc.dd: Likewise * ld-x86-64/tlspic.dd: Likewise opcodes/ 2007-04-26 H.J. Lu <hongjiu.lu@intel.com> PR binutils/4430 * i386-dis.c (print_displacement): New. (OP_E): Call print_displacement instead of print_operand_value to output displacement when either base or index exist. Print the explicit zero displacement in 16bit mode.
2007-04-26gas/testsuite/H.J. Lu2-4/+25
2007-04-26 H.J. Lu <hongjiu.lu@intel.com> PR binutils/4429 * gas/i386/i386.exp: Run "x86-64-addr32-intel" and "x86-64-rip-intel". * gas/i386/intelok.d: Updated. * gas/i386/x86-64-addr32-intel.d: New file. * gas/i386/x86-64-rip-intel.d: Likewise. opcodes/ 2007-04-26 H.J. Lu <hongjiu.lu@intel.com> PR binutils/4429 * i386-dis.c (print_insn): Also swap the order of op_riprel when swapping op_index. Break when the RIP relative address is printed. (OP_E): Properly handle RIP relative addressing and print the explicit zero displacement for Intel mode.
2007-04-26bfd/Alan Modra1-1/+8
* sysdep.h: Include config.h first. Many files: Include sysdep.h before bfd.h. * Makefile.am: Run "make dep-am". * Makefile.in: Regenerate. binutils/ * bucumm.h: Split off host dependencies to.. * sysdep.h: ..here. Many files: Include sysdep.h. Remove duplicate headers and reorder. * Makefile.am: Run "make dep-am". * Makefile.in: Regenerate. ld/ Many files: Include sysdep.h first. Remove duplicate headers. * Makefile.am: Run "make dep-am". * Makefile.in: Regenerate. opcodes/ * Makefile.am: Run "make dep-am". * Makefile.in: Regenerate. * ns32k-dis.c: Include sysdep.h first.
2007-04-26bfd/Alan Modra3-10/+8
Many files: Include sysdep.h before bfd.h. * Makefile.am: Run "make dep-am". * Makefile.in: Regenerate. binutils/ * bucumm.h: Split off host dependencies to.. * sysdep.h: ..here. Many files: Include sysdep.h. Remove duplicate headers and reorder. * Makefile.am: Run "make dep-am". * Makefile.in: Regenerate. ld/ Many files: Include sysdep.h first. Remove duplicate headers. * Makefile.am: Run "make dep-am". * Makefile.in: Regenerate. opcodes/ * Makefile.am: Run "make dep-am". * Makefile.in: Regenerate. * ns32k-dis.c: Include sysdep.h first.
2007-04-242007-04-24 Andreas Krebbel <krebbel1@de.ibm.com>Martin Schwidefsky3-1/+9
* opcodes/s390-opc.c (MASK_SSF_RRDRD): Fourth nybble belongs to the opcode. * opcodes/s390-opc.txt (pfpo, ectg, csst): New z9-ec instructions added. 2007-04-24 Andreas Krebbel <krebbel1@de.ibm.com> * gas/s390/zarch-z9-ec.d: Add pfpo, ectg and csst. * gas/s390/zarch-z9-ec.s: Likewise.
2007-04-24Fix compile time warning (at -O3 with gcc 4.1.2)Nick Clifton2-1/+5
2007-04-24 * cgen-types.h: Include bfd_stdint.h, not stdint.h.Alan Modra4-23/+38
* Makefile.am: Run "make dep-am". * Makefile.in: Regenerate.
2007-04-23 gas/testsuite/Nathan Sidwell2-38/+42
* gas/m68k/br-isaa.s: New. * gas/m68k/br-isaa.d: New. * gas/m68k/br-isab.s: New. * gas/m68k/br-isab.d: New. * gas/m68k/br-isac.s: New. * gas/m68k/br-isac.d: New. * gas/m68k/all.exp: Adjust. gas/ * config/tc-m68k.c (mcf54455_ctrl): New. (HAVE_LONG_DISP, HAVE_LONG_CALL, HAVE_LONG_COND): New. (m68k_archs): Add isac. (m68k_cpus): Add 54455 family. (m68k_ip): Split Bg into Bb, Bs, Bg. (m68k_elf_final_processing): Add ISA_C. * doc/c-m68k.texi (M680x0 Options): Add isac. include/opcode/ * m68k.h (mcfisa_c): New. (mcfusp, mcf_mask): Adjust. bfd/ * archures.c (bfd_mach_mcf_isa_c, bfd_mach_mcf_isa_c_mac, bfd_mach_mcf_isa_c_emac): New. * elf32-m68k.c (ISAC_PLT_ENTRY_SIZE, elf_isac_plt0_entry, elf_isac_plt_entry, elf_isac_plt_info): New. (elf32_m68k_object_p): Add ISA_C. (elf32_m68k_print_private_bfd_data): Print ISA_C. (elf32_m68k_get_plt_info): Detect ISA_C. * cpu-m68k.c (arch_info): Add ISAC. (m68k_arch_features): Likewise, (bfd_m68k_compatible): ISAs B & C are not compatible. opcodes/ * m68k-opc.c: Mark mcfisa_c instructions.
2007-04-21 * arm-dis.c (arm_opcodes): Disassemble to unified syntax.Richard Earnshaw2-90/+121
(thumb_opcodes): Add missing white space in adr. (arm_decode_shift): New parameter, print_shift. Only decode the shift parameter if set. Adjust callers. (print_insn_arm): Support for operand type q with no shift decode.
2007-04-21gas/Alan Modra3-9/+7
* expr.c (expr): Assert on rankarg, not rank which can be unsigned. * read.c (read_a_source_file): Remove buffer_limit[-1] assertion. Don't skip over NUL char. (pseudo_set): Set X_op for registers to O_register. * symbols.c (symbol_clone): Remove assertion that sym is defined. (resolve_symbol_value): Resolve O_register symbols. * config/tc-i386.c (parse_real_register): Don't use i386_float_regtab. Instead find st(0) by hash lookup. * config/tc-ppc.c (ppc_macro): Warning fix. opcodes/ * i386-opc.c (i386_float_regtab, i386_float_regtab_size): Delete. Move contents to.. (i386_regtab): ..here. * i386-opc.h (i386_float_regtab, i386_float_regtab_size): Delete.
2007-04-21 * ppc-opc.c (powerpc_operands): Delete duplicate entries.Alan Modra2-58/+36
(BA_MASK, FXM_MASK, STRM_MASK, VA_MASK, VB_MASK, VC_MASK): Delete. (VD_MASK, WS_MASK, MTMSRD_L, XRT_L): Delete. (powerpc_opcodes): Replace uses of MTMSRD_L and XRT_L.
2007-04-20 gas/Nathan Sidwell2-1/+8
* config/m68k-parse.h (RAMBAR_ALT): New. * config/tc-m68k.c (mcf5206_ctrl, mcf5307_ctrl): New. (mcf_ctrl, mcf5208_ctrl, mcf5210a_ctrl, mcf5213_ctrl, mcf52235_ctrl, mcf5225_ctrl, mcf5235_ctrl, mcf5271_ctrl, mcf5275_ctrl, mcf5282_ctrl, mcf5329_ctrl, mcf5373_ctrl, mcfv4e_ctrl, mcf5475_ctrl, mcf5485_ctrl): Add RAMBAR synonym for RAMBAR1. (mcf5272_ctrl): Add RAMBAR0, replace add RAMBAR with RAMBAR_ALT. (m68k_cpus): Adjust 5206, 5206e & 5307 entries. (m68k_ip) <Case J>: Detect when RAMBAR_ALT should be used. Add it to control register mapping. gas/testsuite/ * gas/m68k/ctrl-1.d, gas/m68k/ctrl-1.s: New. * gas/m68k/ctrl-2.d, gas/m68k/ctrl-2.s: New. * gas/m68k/all.exp: Add them. opcodes/ * m68k-dis.c (print_insn_arg): Show c04 as rambar0 and c05 as rambar1.
2007-04-20include/opcode/Alan Modra3-365/+137
* ppc.h (struct powerpc_operand): Replace "bits" with "bitm". (num_powerpc_operands): Declare. (PPC_OPERAND_SIGNED et al): Redefine as hex. (PPC_OPERAND_PLUS1): Define. opcodes/ * ppc-dis.c (print_insn_powerpc): Adjust for struct powerpc_operand change. * ppc-opc.c (powerpc_operands): Replace bit count with bit mask in all entries. Add PPC_OPERAND_SIGNED to DE entry. Remove references to following deleted functions. (insert_bd, extract_bd, insert_dq, extract_dq): Delete. (insert_ds, extract_ds, insert_de, extract_de): Delete. (insert_des, extract_des, insert_li, extract_li): Delete. (insert_nb, insert_rsq, insert_rtq, insert_ev2, extract_ev2): Delete. (insert_ev4, extract_ev4, insert_ev8, extract_ev8): Delete. (num_powerpc_operands): New constant. (XSPRG_MASK): Remove entire SPRG field. (powerpc_opcodes <bcctre, bcctrel>): Use XLBB_MASK not XLYBB_MASK. gas/ * messages.c (as_internal_value_out_of_range): Extend to report errors for values with invalid low bits set. * config/tc-ppc.c (ppc_setup_opcodes): Check powerpc_operands bitm fields. Check that operands and opcode fields are disjoint. (ppc_insert_operand): Check operands using mask rather than bit count. Check low bits too. Handle PPC_OPERAND_PLUS1. Adjust insertion code. (md_apply_fix): Adjust for struct powerpc_operand change.
2007-04-20 * ppc-opc.c (DCM, DGM, TE, RMC, R, SP, S): Correct shift.Alan Modra2-37/+37
(Z2_MASK): Define. (powerpc_opcodes): Use Z2_MASK in all insns taking RMC operand.
2007-04-20 * arm-dis.c (print_insn): Only look for a mapping symbol in the sectionRichard Earnshaw2-2/+9
being disassembled.
2007-04-19Correct SSE4.2 ChangeLog entry.H.J. Lu1-1/+1
2007-04-19..Alan Modra1-0/+6
2007-04-19 * Makefile.am: Run "make dep-am".Alan Modra3-6/+9
* Makefile.in: Regenerate. * po/POTFILES.in: Regenerate.
2007-04-19 * ppc-opc.c (powerpc_opcodes): Add cctpl, cctpm, cctph, db8cyc,Alan Modra2-0/+12
db10cyc, db12cyc, db16cyc.
2007-04-18 * ppc-opc.c (powerpc_opcodes): Recognize three-operand tlbsxe.Alan Modra2-2/+6
2007-04-18gas/H.J. Lu4-11/+170
2007-04-18 H.J. Lu <hongjiu.lu@intel.com> * config/tc-i386.c (cpu_arch): Add .sse4.2 and .sse4. (match_template): Handle operand size for crc32 in SSE4.2. (process_suffix): Handle operand type for crc32 in SSE4.2. (output_insn): Support SSE4.2. gas/testsuite/ 2007-04-18 H.J. Lu <hongjiu.lu@intel.com> * gas/i386/i386.exp: Add sse4.2 and x86-64-sse4.2. * gas/i386/sse4_2.d: New file. * gas/i386/sse4_2.s: Likewise. * gas/i386/x86-64-sse4_2.d: Likewise. * gas/i386/x86-64-sse4_2.s: Likewise. opcodes/ 2007-04-18 H.J. Lu <hongjiu.lu@intel.com> * i386-dis.c (CRC32_Fixup): New. (PREGRP85, PREGRP86, PREGRP87, PREGRP88, PREGRP89, PREGRP90, PREGRP91): New. (threebyte_0x38_uses_DATA_prefix): Updated for SSE4.2. (threebyte_0x3a_uses_DATA_prefix): Likewise. (prefix_user_table): Add PREGRP85, PREGRP86, PREGRP87, PREGRP88, PREGRP89, PREGRP90 and PREGRP91. (three_byte_table): Likewise. * i386-opc.c (i386_optab): Add SSE4.2 opcodes. * gas/config/tc-i386.h (CpuSSE4_2): New. (CpuSSE4): Likewise. (CpuUnknownFlags): Add CpuSSE4_2.
2007-04-18gas/H.J. Lu4-57/+590
2007-04-18 H.J. Lu <hongjiu.lu@intel.com> * config/tc-i386.c (cpu_arch): Add .sse4.1. (process_operands): Adjust implicit operand for blendvpd, blendvps and pblendvb in SSE4.1. (output_insn): Support SSE4.1. gas/testsuite/ 2007-04-18 H.J. Lu <hongjiu.lu@intel.com> * gas/i386/i386.exp: Add sse4.1 and x86-64-sse4.1. * gas/i386/sse4_1.d: New file. * gas/i386/sse4_1.s: Likewise. * gas/i386/x86-64-sse4_1.d: Likewise. * gas/i386/x86-64-sse4_1.s: Likewise. opcodes/ 2007-04-18 H.J. Lu <hongjiu.lu@intel.com> * i386-dis.c (XMM_Fixup): New. (Edqb): New. (Edqd): New. (XMM0): New. (dqb_mode): New. (dqd_mode): New. (PREGRP39 ... PREGRP85): New. (threebyte_0x38_uses_DATA_prefix): Updated for SSE4. (threebyte_0x3a_uses_DATA_prefix): Likewise. (prefix_user_table): Add PREGRP39 ... PREGRP85. (three_byte_table): Likewise. (putop): Handle 'K'. (intel_operand_size): Handle dqb_mode, dqd_mode): (OP_E): Likewise. (OP_G): Likewise. * i386-opc.c (i386_optab): Add SSE4.1 opcodes. * i386-opc.h (CpuSSE4_1): New. (CpuUnknownFlags): Add CpuSSE4_1. (regKludge): Update comment.
2007-04-182007-04-18 Matthias Klose <doko@ubuntu.com>Daniel Jacobowitz3-2/+7
* Makefile.am (libbfd_la_LDFLAGS): Use bfd soversion. (bfdver.h): Use the date in non-release builds for the soversion. * Makefile.in: Regenerate. 2007-04-18 Matthias Klose <doko@ubuntu.com> * Makefile.am (libopcodes_la_LDFLAGS): Use bfd soversion. * Makefile.in: Regenerate.
2007-04-14 * Makefile.am: Add ACLOCAL_AMFLAGS.Steve Ellcey3-0/+7
* Makefile.in: Regenerate.
2007-04-13Remove trailing white spaces.H.J. Lu3-2/+4
2007-04-132007-04-13 H.J. Lu <hongjiu.lu@intel.com>H.J. Lu2-21/+25
* i386-dis.c: Remove trailing white spaces.
2007-04-112007-04-11 H.J. Lu <hongjiu.lu@intel.com>H.J. Lu2-113/+142
PR binutils/4333 * i386-dis.c (GRP1a): New. (GRP1b ... GRPPADLCK2): Update index. (dis386): Use GRP1a for entry 0x8f. (mod, rm, reg): Removed. Replaced by ... (modrm): This. (grps): Add GRP1a.
2007-04-09 * m68k-dis.c (print_insn_m68k): Restore info->fprintf_func andKazu Hirata2-2/+31
info->print_address_func if longjmp is called.
2007-03-29* m32c.cpu (Imm-8-s4n): Fix print hook.DJ Delorie4-115/+121
(Lab-24-8, Lab-32-8, Lab-40-8): Fix. (arith-jnz-imm4-dst-defn): Make relaxable. (arith-jnz16-imm4-dst-defn): Fix encodings. * m32c-desc.c: Regenerate. * m32c-dis.c: Regenerate. * m32c-opc.c: Regenerate. * config/tc-m32c.c (rl_for, relaxable): Protect argument. (md_relax_table): Add entries for ADJNZ macros. (M32C_Macros): Add ADJNZ macros. (subtype_mappings): Add entries for ADJNZ macros. (insn_to_subtype): Check for adjnz and sbjnz insns. (md_estimate_size_before_relax): Pass insn to insn_to_subtype. (md_convert_frag): Convert adjnz and sbjnz.
2007-03-29gas/H.J. Lu3-22/+30
2007-03-28 H.J. Lu <hongjiu.lu@intel.com> * config/tc-i386.c (build_modrm_byte): For instructions with 2 register operands, encode destination in i.rm.regmem if its RegMem bit is set. opcodes/ 2007-03-28 H.J. Lu <hongjiu.lu@intel.com> * i386-opc.c (i386_optab): Change InvMem to RegMem for mov and movq. Remove InvMem from sldt, smsw and str. * i386-opc.h (InvMem): Renamed to ... (RegMem): Update comments. (AnyMem): Remove InvMem.
2007-03-27Fix year.H.J. Lu1-4/+4
2007-03-272006-03-27 Paul Brook <paul@codesourcery.com>Paul Brook2-0/+6
opcodes/ * arm-dis.c (thumb_opcodes): Add entry for undefined insns (0xbe??).
2007-03-242007-03-24 Paul Brook <paul@codesourcery.com>Paul Brook2-2/+12
opcodes/ * arm-dis.c (coprocessor_opcodes): Remove superfluous 0x. (print_insn_coprocessor): Handle %<bitfield>x.
2007-03-242007-03-24 Paul Brook <paul@codesourcery.com>Paul Brook2-3/+8
Mark Shinwell <shinwell@codesourcery.com> gas/ * config/tc-arm.c (operand_parse_code): Add OP_oRRw. (parse_operands): Don't expect comma if first operand missing. Handle OP_oRRw. (do_srs): Encode register number, checking it is r13. Update comment. (insns): Update SRS entries to take a register. gas/testsuite/ * gas/arm/archv6.s: Add new SRS tests. * gas/arm/archv6.d: Update expected output. * gas/arm/thumb32.s: Add new SRS tests. * gas/arm/thumb32.d: Update expected output. * gas/arm/srs-t2.d: New. * gas/arm/srs-t2.l: New. * gas/arm/srs-t2.s: New. * gas/arm/srs-arm.d: New. * gas/arm/srs-arm.l: New. * gas/arm/srs-arm.s: New. opcodes/ * arm-dis.c (arm_opcodes): Print SRS base register.
2007-03-23gas/H.J. Lu3-16/+42
2003-03-23 H.J. Lu <hongjiu.lu@intel.com> * config/tc-i386.c (md_begin): Allow '.' in mnemonic. gas/testsuite/ 2003-03-23 H.J. Lu <hongjiu.lu@intel.com> * gas/i386/rex.s: Add tests for rex.WRXB. * gas/i386/rex.d: Updated. * gas/i386/rex.d: Replace rex64XYZ with rex.WRXB. * gas/i386/x86-64-io-intel.d : Likewise. * gas/i386/x86-64-io-suffix.d: Likewise. * gas/i386/x86-64-io.d: Likewise. * gas/i386/x86-64-opcode.d: Likewise. opcodes/ 2003-03-23 H.J. Lu <hongjiu.lu@intel.com> * i386-dis.c (prefix_name): Replace rex64XYZ with rex.WRXB. * i386-opc.c (i386_optab): Add rex.wrxb.
2007-03-21gas/H.J. Lu2-71/+80
2003-03-21 H.J. Lu <hongjiu.lu@intel.com> * config/tc-i386.c: Replace REX_MODE64, REX_EXTX, REX_EXTY and REX_EXTZ with REX_W, REX_R, REX_X and REX_B respectively. include/opcode/ 2003-03-21 H.J. Lu <hongjiu.lu@intel.com> * i386.h (REX_MODE64): Renamed to ... (REX_W): This. (REX_EXTX): Renamed to ... (REX_R): This. (REX_EXTY): Renamed to ... (REX_X): This. (REX_EXTZ): Renamed to ... (REX_B): This. opcodes/ 2003-03-21 H.J. Lu <hongjiu.lu@intel.com> * i386-dis.c (REX_MODE64): Remove definition. (REX_EXTX): Likewise. (REX_EXTY): Likewise. (REX_EXTZ): Likewise. (USED_REX): Use REX_OPCODE instead of 0x40. Replace REX_MODE64, REX_EXTX, REX_EXTY and REX_EXTZ with REX_W, REX_R, REX_X and REX_B respectively.
2007-03-21gas/H.J. Lu3-18/+39
2003-03-21 H.J. Lu <hongjiu.lu@intel.com> PR binutils/4218 * config/tc-i386.c (match_template): Properly handle 64bit mode "xchg %eax, %eax". gas/testsuite/ 2003-03-21 H.J. Lu <hongjiu.lu@intel.com> PR binutils/4218 * gas/i386/nops.s: Add testcases for nop r/m. * gas/i386/x86-64-nops.s: Likewise. * gas/i386/x86-64-opcode.s: Add testcases for xchg with %ax, %eax and %rax. * gas/i386/nops.d: Updated. * gas/i386/x86-64-nops.d: Likewise. * gas/i386/x86-64-opcode.d: Likewise. opcodes/ 2003-03-21 H.J. Lu <hongjiu.lu@intel.com> PR binutils/4218 * i386-dis.c (PREGRP38): New. (dis386): Use PREGRP38 for 0x90. (prefix_user_table): Add PREGRP38. (print_insn): Set uses_REPZ_prefix to 1 for pause. (NOP_Fixup1): Properly handle REX bits. (NOP_Fixup2): Likewise. * i386-opc.c (i386_optab): Allow %eax with xchg in 64bit. Allow register with nop.
2007-03-21* m32c.cpu (f-dsp-40-u20, f-dsp-48-u20, Dsp-40-u20, Dsp-40-u20,DJ Delorie8-286/+441
mem20): New. (src16-16-20-An-relative-*): New. (dst16-*-20-An-relative-*): New. (dst16-16-16sa-*): New (dst16-16-16ar-*): New (dst32-16-16sa-Unprefixed-*): New (jsri): Fix operands. (setzx): Fix encoding. * m32c-asm.c: Regenerate. * m32c-desc.c: Regenerate. * m32c-desc.h: Regenerate. * m32c-dis.h: Regenerate. * m32c-ibld.c: Regenerate. * m32c-opc.c: Regenerate. * m32c-opc.h: Regenerate.
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