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2017-03-03opcodes: link against libbfd.la for rpath depsusers/gentoo/2.28Mike Frysinger2-2/+2
The reason opcodes doesn't link against libbfd.la is to workaround a libtool bug where it uses installed -L paths ahead of DESTDIR paths. The downside is that the library itself lacks rpath tags to find the right version of libbfd.so. Since Gentoo has patched the libtool bug for a while, we don't need the workaround. Use the .la file so we get the rpath tags. URL: https://bugs.gentoo.org/563934
2017-03-02Add generated filesbinutils-2_28Tristan Gingold18-10/+14
2017-02-27Add SFENCE.VMA instructionAndrew Waterman2-0/+8
include/ChangeLog: 2017-02-14 Andrew Waterman <andrew@sifive.com> * opcode/riscv-opc.h (MATCH_SFENCE_VMA): New define. (MASK_SFENCE_VMA): Likewise. (sfence_vma): Declare instruction. opcodes/ChangeLog: 2017-02-14 Andrew Waterman <andrew@sifive.com> * riscv-opc.c (riscv_opcodes): Add sfence.vma instruction and pseudoinstructions.
2017-02-27 sveRichard Sandiford11-2089/+2815
[AArch64] Additional SVE instructions This patch supports some additions to the SVE architecture prior to its public release. include/ * opcode/aarch64.h (AARCH64_OPND_SVE_ADDR_RI_S4x16) (AARCH64_OPND_SVE_IMM_ROT1, AARCH64_OPND_SVE_IMM_ROT2) (AARCH64_OPND_SVE_Zm3_INDEX, AARCH64_OPND_SVE_Zm3_22_INDEX) (AARCH64_OPND_SVE_Zm4_INDEX): New aarch64_opnds. opcodes/ * aarch64-tbl.h (OP_SVE_HMH, OP_SVE_VMU_HSD, OP_SVE_VMVU_HSD) (OP_SVE_VMVV_HSD, OP_SVE_VMVVU_HSD, OP_SVE_VM_HSD, OP_SVE_VUVV_HSD) (OP_SVE_VUV_HSD, OP_SVE_VU_HSD, OP_SVE_VVVU_H, OP_SVE_VVVU_S) (OP_SVE_VVVU_HSD, OP_SVE_VVV_D, OP_SVE_VVV_D_H, OP_SVE_VVV_H) (OP_SVE_VVV_HSD, OP_SVE_VVV_S, OP_SVE_VVV_S_B, OP_SVE_VVV_SD_BH) (OP_SVE_VV_BHSDQ, OP_SVE_VV_HSD, OP_SVE_VZVV_HSD, OP_SVE_VZV_HSD) (OP_SVE_V_HSD): New macros. (OP_SVE_VMU_SD, OP_SVE_VMVU_SD, OP_SVE_VM_SD, OP_SVE_VUVV_SD) (OP_SVE_VU_SD, OP_SVE_VVVU_SD, OP_SVE_VVV_SD, OP_SVE_VZVV_SD) (OP_SVE_VZV_SD, OP_SVE_V_SD): Delete. (aarch64_opcode_table): Add new SVE instructions. (aarch64_opcode_table): Use imm_rotate{1,2} instead of imm_rotate for rotation operands. Add new SVE operands. * aarch64-asm.h (ins_sve_addr_ri_s4): New inserter. (ins_sve_quad_index): Likewise. (ins_imm_rotate): Split into... (ins_imm_rotate1, ins_imm_rotate2): ...these two inserters. * aarch64-asm.c (aarch64_ins_imm_rotate): Split into... (aarch64_ins_imm_rotate1, aarch64_ins_imm_rotate2): ...these two functions. (aarch64_ins_sve_addr_ri_s4): New function. (aarch64_ins_sve_quad_index): Likewise. (do_misc_encoding): Handle "MOV Zn.Q, Qm". * aarch64-asm-2.c: Regenerate. * aarch64-dis.h (ext_sve_addr_ri_s4): New extractor. (ext_sve_quad_index): Likewise. (ext_imm_rotate): Split into... (ext_imm_rotate1, ext_imm_rotate2): ...these two extractors. * aarch64-dis.c (aarch64_ext_imm_rotate): Split into... (aarch64_ext_imm_rotate1, aarch64_ext_imm_rotate2): ...these two functions. (aarch64_ext_sve_addr_ri_s4): New function. (aarch64_ext_sve_quad_index): Likewise. (aarch64_ext_sve_index): Allow quad indices. (do_misc_decoding): Likewise. * aarch64-dis-2.c: Regenerate. * aarch64-opc.h (FLD_SVE_i3h, FLD_SVE_rot1, FLD_SVE_rot2): New aarch64_field_kinds. (OPD_F_OD_MASK): Widen by one bit. (OPD_F_NO_ZR): Bump accordingly. (get_operand_field_width): New function. * aarch64-opc.c (fields): Add new SVE fields. (operand_general_constraint_met_p): Handle new SVE operands. (aarch64_print_operand): Likewise. * aarch64-opc-2.c: Regenerate. gas/ * doc/c-aarch64.texi: Document that sve implies fp16, simd and compnum. * config/tc-aarch64.c (parse_vector_type_for_operand): Allow .q to be used with SVE registers. (parse_operands): Handle new SVE operands. (aarch64_features): Make "sve" require F16 rather than FP. Also require COMPNUM. * testsuite/gas/aarch64/sve.s: Add tests for new instructions. Include compnum tests. * testsuite/gas/aarch64/sve.d: Update accordingly. * testsuite/gas/aarch64/sve-invalid.s: Add tests for new instructions. * testsuite/gas/aarch64/sve-invalid.l: Update accordingly. Also update expected output for new FMOV and MOV alternatives.
2017-02-27 sveRichard Sandiford2-6/+17
[AArch64] Add a "compnum" feature This patch adds a named "compnum" feature for the ARMv8.3-A FCADD and FCMLA extensions. include/ * opcode/aarch64.h (AARCH64_FEATURE_COMPNUM): New macro. (AARCH64_ARCH_V8_3): Include AARCH64_FEATURE_COMPNUM. opcodes/ * aarch64-tbl.h (aarch64_feature_simd_v8_3): Replace with... (aarch64_feature_compnum): ...this. (SIMD_V8_3): Replace with... (COMPNUM): ...this. (CNUM_INSN): New macro. (aarch64_opcode_table): Use it for the complex number instructions. gas/ * doc/c-aarch64.texi: Add a "compnum" entry. * config/tc-aarch64.c (aarch64_features): Likewise, * testsuite/gas/aarch64/advsimd-compnum.s: New test. * testsuite/gas/aarch64/advsimd-compnum.d: Likewise.
2017-02-27 sveRichard Sandiford2-0/+21
[AArch64] Add SVE system registers This patch adds the SVE-specific system registers. opcodes/ * aarch64-opc.c (aarch64_sys_regs): Add SVE registers. (aarch64_sys_reg_supported_p): Handle them. gas/ * testsuite/gas/aarch64/sve-sysreg.s, testsuite/gas/aarch64/sve-sysreg.d, testsuite/gas/aarch64/sve-sysreg-invalid.d, testsuite/gas/aarch64/sve-sysreg-invalid.l: New tests.
2017-02-27[AArch64] Add separate feature flag for weaker release consistent load insnsRichard Sandiford2-3/+13
The weaker release consistency support of ARMv8.3-A is allowed as an optional extension for ARMv8.2-A, so separate command line option and feature flag is added: -march=armv8.2-a+rcpc turns LDAPR, LDAPRB, LDAPRH instructions on. opcodes/ 2017-01-04 Szabolcs Nagy <szabolcs.nagy@arm.com> * aarch64-tbl.h (RCPC, RCPC_INSN): Define. (aarch64_opcode_table): Use RCPC_INSN. include/ 2017-01-04 Szabolcs Nagy <szabolcs.nagy@arm.com> * opcode/aarch64.h (AARCH64_FEATURE_RCPC): Define. (AARCH64_ARCH_V8_3): Update. gas/ 2017-01-04 Szabolcs Nagy <szabolcs.nagy@arm.com> * config/tc-aarch64.c (aarch64_features): Add rcpc. * doc/c-aarch64.texi (AArch64 Extensions): Document rcpc. * testsuite/gas/aarch64/ldst-exclusive-armv8_3.d: Rename to ... * testsuite/gas/aarch64/ldst-rcpc.d: This. * testsuite/gas/aarch64/ldst-exclusive-armv8_3.s: Rename to ... * testsuite/gas/aarch64/ldst-rcpc.s: This. * testsuite/gas/aarch64/ldst-rcpc-armv8_2.d: New test.
2017-02-23S/390: Add support for new cpu architecture - arch12.Andreas Krebbel3-79/+311
This adds support of new instructions to the S/390 specific parts. The important feature of the new instruction set is the support of single and extended precision floating point vector operations. Note: arch12 is NOT the official name of the new CPU. It just continues the series of archXX options supported as alternate names. The archXX terminology refers to the edition number of the Principle of Operations manual. The official CPU name will be added later while keeping support of the arch12 for backwards compatibility. No testsuite regressions. Committed to mainline. Bye, -Andreas- opcodes/ChangeLog: 2017-02-23 Andreas Krebbel <krebbel@linux.vnet.ibm.com> * s390-mkopc.c (main): Accept arch12 as cpu string and vx2 as facility. * s390-opc.c: Add new operand description macros, new instruction types, instruction masks, and new .insn instruction types. * s390-opc.txt: Add new arch12 instructions. include/ChangeLog: 2017-02-23 Andreas Krebbel <krebbel@linux.vnet.ibm.com> * opcode/s390.h (enum s390_opcode_cpu_val): New value S390_OPCODE_ARCH12. (S390_INSTR_FLAG_VX2): New macro definition. gas/ChangeLog: 2017-02-23 Andreas Krebbel <krebbel@linux.vnet.ibm.com> * config/tc-s390.c (s390_parse_cpu): New entry for arch12. * doc/as.texinfo: Document arch12 as cpu type. * doc/c-s390.texi: Likewise. * testsuite/gas/s390/s390.exp: Run arch12 specific tests. * testsuite/gas/s390/zarch-arch12.d: New test. * testsuite/gas/s390/zarch-arch12.s: New test. * testsuite/gas/s390/zarch-z13.d: Rename some mnemonics in the output patterns.
2017-02-11Fix use after free in cgen instruction lookupAlan Modra2-15/+20
* cgen-opc.c (cgen_lookup_insn): Delete buf and base_insn temps. Use insn_bytes_value and insn_int_value directly instead. Don't free allocated memory until function exit.
2017-02-11POWER9 add scv/rfscv instruction supportNicholas Piggin2-1/+7
opcodes/ * ppc-opc.c (powerpc_opcodes) <scv, rfscv>: New mnemonics. gas/ * testsuite/gas/ppc/power9.d <scv, rfscv>: New tests.
2017-01-13Enable Intel AVX512_VPOPCNTDQ instructionsIgor Tsimbalist8-5344/+5432
gas/ 2017-01-12 Igor Tsimbalist <igor.v.tsimbalist@intel.com> * config/tc-i386.c (cpu_arch): Add .avx512_vpopcntdq. (cpu_noarch): Add noavx512_vpopcntdq. * doc/c-i386.texi: Document avx512_vpopcntdq, noavx512_vpopcntdq. * testsuite/gas/i386/i386.exp: Run AVX512_VPOPCNTDQ tests. * testsuite/gas/i386/avx512_vpopcntdqd-intel.d: New file. * testsuite/gas/i386/avx512_vpopcntdqd.d: Ditto. * testsuite/gas/i386/avx512_vpopcntdqd.s: Ditto. * testsuite/gas/i386/x86-64-avx512_vpopcntdqd-intel.d: Ditto. * testsuite/gas/i386/x86-64-avx512_vpopcntdqd.d: Ditto. * testsuite/gas/i386/x86-64-avx512_vpopcntdqd.s: Ditto. opcodes/ 2017-01-12 Igor Tsimbalist <igor.v.tsimbalist@intel.com> * i386-dis.c (enum): Add PREFIX_EVEX_0F3855, EVEX_W_0F3855_P_2. * i386-dis-evex.h (evex_table): Updated. * i386-gen.c (cpu_flag_init): Add CPU_AVX512_VPOPCNTDQ_FLAGS, CPU_ANY_AVX512_VPOPCNTDQ_FLAGS. Update CPU_ANY_AVX512F_FLAGS. (cpu_flags): Add CpuAVX512_VPOPCNTDQ. * i386-opc.h (enum): (AVX512_VPOPCNTDQ): New. (i386_cpu_flags): Add cpuavx512_vpopcntdq. * i386-opc.tbl: Add Intel AVX512_VPOPCNTDQ instructions. * i386-init.h: Regenerate. * i386-tbl.h: Ditto.
2017-01-02Update year range in copyright notice of all files.Alan Modra273-276/+280
2017-01-02ChangeLog rotationAlan Modra2-2144/+2158
2016-12-28Check bfd support for bfd_mips_elf_get_abiflags in mips make ruleAlan Modra7-132/+38
The previous scheme with a dependency in opcodes on libbfd.la broke "make distclean". * configure.ac: Revert 2016-12-23. * Makefile.am: Likewise. (MIPS_DEFS): Define. (mips-dis.lo): Add rule. * Makefile.in: Regenerate. * aclocal.m4: Regenerate. * config.in: Regenerate. * configure: Regenerate.
2016-12-23MIPS16: Add ASMACRO instruction supportMaciej W. Rozycki2-0/+15
Add ASMACRO instruction support as per the MIPS16e ASE architecture specifications [1][2], completing MIPS16e instruction set support. [1] "MIPS32 Architecture for Programmers, Volume IV-a: The MIPS16e Application-Specific Extension to the MIPS32 Architecture", MIPS Technologies, Inc., Document Number: MD00076, Revision 2.63, July 16, 2013, Section 4.1 "MIPS16e Instruction Descriptions", p. 65 [2] "MIPS64 Architecture for Programmers, Volume IV-a: The MIPS16e Application-Specific Extension to the MIPS64 Architecture", MIPS Technologies, Inc., Document Number: MD00077, Revision 2.60, June 25, 2008, Section 1.1 "MIPS16e Instruction Descriptions", p. 66 include/ * opcode/mips.h: Document `0', `1', `2', `3', `4' and `s' operand codes. opcodes/ * mips16-opc.c (decode_mips16_operand): Add `0', `1', `2', `3', `4' and `s' operand codes. (mips16_opcodes): Add "asmacro" entry. binutils/ * testsuite/binutils-all/mips/mips16-extend-insn.d: Update for ASMACRO support. gas/ * testsuite/gas/mips/mips16-asmacro.d: New test. * testsuite/gas/mips/mips16-32@mips16-asmacro.d: New test. * testsuite/gas/mips/mips16-64@mips16-asmacro.d: New test. * testsuite/gas/mips/mips16-asmacro.s: New test source. * testsuite/gas/mips/mips.exp: Run the new tests. (cherry picked from commit 5284e471d53ccb7c7a1d140bd83098607ccf4b8a)
2016-12-23MIPS16: Simplify extended operand handlingMaciej W. Rozycki3-20/+25
Simplify extended operand handling and only specially process immediates which require bit shuffling, using the generic operand insertion and extraction handlers for the '<' (5-bit shift amount) operand code in particular. Require the least significant bit of all extended operand forms to be (artificially) set to 0 for their special processing to trigger. gas/ * config/tc-mips.c (mips16_immed): Limit `mips16_immed_extend' use to operands whose LSB position is zero. opcodes/ * mips-dis.c (print_mips16_insn_arg): Simplify processing of extended operands. * mips16-opc.c (decode_mips16_operand): Switch the extended form of the `<' operand type to LSB position 22. (cherry picked from commit bdd152861ce75c36828904cf3d10f8ce14da6cf5)
2016-12-23MIPS16: Reassign `0' and `4' operand codesMaciej W. Rozycki2-15/+22
Replace `0' and `4' operand codes with `.' and `F' respectively to free up the `0'-`4' consecutive range. No functional change. gas/ * config/tc-mips.c (mips16_macro_build): Replace `0' and `4' operand codes with `.' and `F' respectively. (mips16_macro): Likewise. include/ * opcode/mips.h: Replace `0' and `4' operand codes with `.' and `F' respectively. opcodes/ * mips16-opc.c (decode_mips16_operand): Replace `0' and `4' operand codes with `.' and `F' respectively. (mips16_opcodes): Likewise. (cherry picked from commit d8722d7641d234dcd3d1f2254fbc5d9cf234e4e6)
2016-12-23MIPS16: Handle non-extensible instructions correctlyMaciej W. Rozycki3-68/+86
Identify non-extensible instructions in the MIPS16 opcode table and disallow their use with the `.e' instruction size suffix in assembly and do not interpret any EXTEND prefix present as a part of the instruction in disassembly. According to all versions of the MIPS16 ASE specifications the following instructions encodings are not extensible [1][2][3][4][5][6]: I8/MOV32R, I8/MOVR32, all RRR minor opcodes, all RR minor opcodes except from DSRA and DSRL, and EXTEND itself, and as from revision 2.50 of the MIPS16e ASE specifications it has been further clarified what was previously implied, that non-extesiable instructions when preceded with an EXTEND prefix must cause a Reserved Instruction exception [3][5]. Therefore in the presence of an EXTEND prefix none of these instructions are supposed to be handled as extended instructions and supporting these forms in disassembly causes confusion, and in the case of the RRR major opcode it also clashes with the ASMACRO encoding. References: [1] "Product Description, MIPS16 Application-Specific Extension", Version 1.3, MIPS Technologies, Inc., 970130, Table 3. "MIPS16 Instruction Set Summary", p. 5 [2] same, Table 5 "RR Minor Opcodes (RR-type instructions)", p.10 [3] "MIPS32 Architecture for Programmers, Volume IV-a: The MIPS16e Application-Specific Extension to the MIPS32 Architecture", MIPS Technologies, Inc., Document Number: MD00076, Revision 2.63, July 16, 2013, Section 3.9 "MIPS16e Instruction Summaries", pp. 37-39 [4] same, Section 3.15 "Instruction Bit Encoding", pp. 46-49 [5] "MIPS64 Architecture for Programmers, Volume IV-a: The MIPS16e Application-Specific Extension to the MIPS64 Architecture", MIPS Technologies, Inc., Document Number: MD00077, Revision 2.60, June 25, 2008, Section 1.9 "MIPS16e Instruction Summaries", pp. 38-41 [6] same, Section 1.15 "Instruction Bit Encoding", pp. 48-51 include/ * opcode/mips.h (INSN2_SHORT_ONLY): New macro. gas/ * config/tc-mips.c (is_size_valid_16): Disallow a `.e' suffix instruction size override for INSN2_SHORT_ONLY opcode table entries. * testsuite/gas/mips/mips16-extend-swap.d: Adjust output. * testsuite/gas/mips/mips16-macro-e.l: Adjust error messages. * testsuite/gas/mips/mips16-32@mips16-macro-e.l: Adjust error messages. * testsuite/gas/mips/mips16e-32@mips16-macro-e.l: Adjust error messages. * testsuite/gas/mips/mips16-insn-e.d: New test. * testsuite/gas/mips/mips16-insn-t.d: New test. * testsuite/gas/mips/mips16-32@mips16-insn-e.d: New test. * testsuite/gas/mips/mips16-64@mips16-insn-e.d: New test. * testsuite/gas/mips/mips16e-32@mips16-insn-e.d: New test. * testsuite/gas/mips/mips16-32@mips16-insn-t.d: New test. * testsuite/gas/mips/mips16-64@mips16-insn-t.d: New test. * testsuite/gas/mips/mips16e-32@mips16-insn-t.d: New test. * testsuite/gas/mips/mips16-insn-e.l: New stderr output. * testsuite/gas/mips/mips16-insn-t.l: New stderr output. * testsuite/gas/mips/mips16-32@mips16-insn-e.l: New stderr output. * testsuite/gas/mips/mips16-64@mips16-insn-e.l: New stderr output. * testsuite/gas/mips/mips16e-32@mips16-insn-e.l: New stderr output. * testsuite/gas/mips/mips16-32@mips16-insn-t.l: New stderr output. * testsuite/gas/mips/mips16-64@mips16-insn-t.l: New stderr output. * testsuite/gas/mips/mips16e-32@mips16-insn-t.l: New stderr output. * testsuite/gas/mips/mips16-insn-e.s: New test source. * testsuite/gas/mips/mips16-insn-t.s: New test source. * testsuite/gas/mips/mips.exp: Run the new tests. opcodes/ * mips-dis.c (print_insn_mips16): Disallow EXTEND prefix matching for INSN2_SHORT_ONLY opcode table entries. * mips16-opc.c (SH): New macro. (mips16_opcodes): Set SH in `pinfo2' for non-extensible instruction entries: "nop", "addu", "and", "break", "cmp", "daddu", "ddiv", "ddivu", "div", "divu", "dmult", "dmultu", "drem", "dremu", "dsllv", "dsll", "dsrav", "dsra", "dsrlv", "dsrl", "dsubu", "exit", "entry", "jalr", "jal", "jr", "j", "jalrc", "jrc", "mfhi", "mflo", "move", "mult", "multu", "neg", "not", "or", "rem", "remu", "sllv", "sll", "slt", "sltu", "srav", "sra", "srlv", "srl", "subu", "xor", "sdbbp", "seb", "seh", "sew", "zeb", "zeh", "zew" and "extend". binutils/ * testsuite/binutils-all/mips/mips16-extend-insn.d: New test. * testsuite/binutils-all/mips/mips16-extend-insn.s: New test source. * testsuite/binutils-all/mips/mips.exp: Run the new tests. (cherry picked from commit 0674ee5dada21c8deec690ca66d5b2870f13ea49)
2016-12-23MIPS16: Remove "extended" BREAK/SDBBP handlingMaciej W. Rozycki2-2/+6
Remove special casing for the `6' operand code used for the embedded trap code of the BREAK and the SDBBP instructions to support supposedly extended forms of these instructions. According to all versions of the MIPS16 ASE specifications these instructions are not extensible [1][2][3][4][5][7][8][10][11], and as from revision 2.50 of the MIPS16e ASE specifications it has been further clarified what was previously implied, that non-extesiable instructions when preceded with an EXTEND prefix must cause a Reserved Instruction exception [5][6][9][10]. Therefore supposedly extended BREAK and SDBBP instructions do not serve their purpose anymore as they do not cause a Bp and a Debug exception respectively and supporting these forms in disassembly only causes confusion. References: [1] "Product Description, MIPS16 Application-Specific Extension", Version 1.3, MIPS Technologies, Inc., 970130, Table 3. "MIPS16 Instruction Set Summary", p. 5 [2] same, Table 5 "RR Minor Opcodes (RR-type instructions)", p.10 [3] same, Table 18. "Extendable MIPS16 Instructions", p. 24 [4] "MIPS32 Architecture for Programmers, Volume IV-a: The MIPS16e Application-Specific Extension to the MIPS32 Architecture", MIPS Technologies, Inc., Document Number: MD00076, Revision 2.63, July 16, 2013, Table 3.8 "MIPS16e Special Instructions", p. 38 [5] same, Section 3.11 "MIPS16e Extensible Instructions, p. 41 [6] same, Table 3.15 "MIPS16e Extensible Instructions", p. 41 [7] same, Table 3.24 "MIPS16e RR Encoding of the Funct Field", p. 49 [8] "MIPS64 Architecture for Programmers, Volume IV-a: The MIPS16e Application-Specific Extension to the MIPS64 Architecture", MIPS Technologies, Inc., Document Number: MD00077, Revision 2.60, June 25, 2008, Table 1.8 "MIPS16e Special Instructions", p. 39 [9] same, Section 1.11 "MIPS16e Extensible Instructions", p. 42 [10] same, Table 1.15 "MIPS16e Extensible Instructions", pp. 42-43 [11] same, Table 1.24 "MIPS16e RR Encoding of the Funct Field", p. 50 gas/ * config/tc-mips.c (match_mips16_insn): Remove the `6' operand code special case and its associated comment. opcodes/ * mips16-opc.c (decode_mips16_operand) <'6'>: Remove extended encoding support. (cherry picked from commit b2805ed55456cea2694d31fc8627cca17120267b)
2016-12-23MIPS16/GAS: Disallow EXTEND delay-slot schedulingMaciej W. Rozycki2-1/+6
Do not allow any explicitly coded EXTEND instruction to be automatically scheduled into a jump delay slot, as an EXTEND prefix is coupled with the next regular MIPS16 instruction and therefore swapping it with a jump would change program's semantics; EXTEND is not architecturally allowed to be present in a jump delay slot anyway. opcodes/ * mips16-opc.c (mips16_opcodes): Set NODS in `pinfo' for "extend". gas/ * testsuite/gas/mips/mips16-extend-swap.d: New test. * testsuite/gas/mips/mips16-extend-swap.s: New test source. * testsuite/gas/mips/mips.exp: Run the new test. (cherry picked from commit 645c455650ed35460afdacb078c7c58308607fbe)
2016-12-23opcodes: Use autoconf to check for `bfd_mips_elf_get_abiflags' in BFDMaciej W. Rozycki8-12/+150
Fix a regression introduced with commit 5e7fc731f80e ("MIPS/opcodes: Also set disassembler's ASE flags from ELF structures"), further updated with commit 4df995c77118 ("MIPS/opcodes: Also set disassembler's ASE flags from ELF structures"), and use autoconf to check for the presence of `bfd_mips_elf_get_abiflags' in BFD. opcodes/ * mips-dis.c (set_default_mips_dis_options): Use HAVE_BFD_MIPS_ELF_GET_ABIFLAGS rather than BFD64 to guard the call to `bfd_mips_elf_get_abiflags'. * configure.ac: Check for `bfd_mips_elf_get_abiflags' in BFD. * Makefile.am (CONFIG_STATUS_DEPENDENCIES): Add `libbfd.la'. * aclocal.m4: Regenerate. * configure: Regenerate. * config.in: Regenerate. * Makefile.in: Regenerate. (cherry picked from commit 9e76c212e6311abaee4d02473473f7d6dcad972f)
2016-12-23Bumping version to 2.27.90Tristan Gingold2-10/+14
bfd/ 2016-12-23 Tristan Gingold <gingold@adacore.com> * version.m4: Bump version to 2.27.90 * configure: Regenerate. binutils/ 2016-12-23 Tristan Gingold <gingold@adacore.com> * configure: Regenerate. gas/ 2016-12-23 Tristan Gingold <gingold@adacore.com> * configure: Regenerate. gprof/ 2016-12-23 Tristan Gingold <gingold@adacore.com> * configure: Regenerate. ld/ 2016-12-23 Tristan Gingold <gingold@adacore.com> * configure: Regenerate. opcodes/ 2016-12-23 Tristan Gingold <gingold@adacore.com> * configure: Regenerate.
2016-12-23Regenerate pot files.Tristan Gingold2-372/+640
2016-12-22ChangeLog formatting fixesAlan Modra1-1/+1
2016-12-22Avoid creating symbol table entries for registersAndrew Waterman2-2/+6
Instructions like "jal t0, foo" were erroneously creating symbol table entries for t0 as well as foo, which causes linking problems. Fix by reordering instruction alternatives so that t0 is first attempted to be parsed as a register, rather than as a symbol. * riscv-opc.c (riscv_opcodes): Reorder jal and call entries.
2016-12-20MIPS16/opcodes: Respect ISA and ASE in disassemblyMaciej W. Rozycki2-1/+11
Limit MIPS16 instruction disassembly according to the ISA level and ASE set selected, as with the regular MIPS and microMIPS instruction sets. Retain the property of `objdump -m mips:16' disassembling all MIPS16 instructions however, regardless of any ISA level recorded in the binary examined. To validate the disassembler use the GAS test suite for its convenience of running tests across multiple ISAs, even though placing the tests in the binutils test suite would be more appropriate. Adjust the single binutils test which depends on 64-bit instruction disassembly to have the ISA level required actually recorded in the binary examined. opcodes/ * mips-dis.c (mips_arch_choices): Use ISA_MIPS64 rather than ISA_MIPS3 as the `isa' selection in the `bfd_mach_mips16' entry. (print_insn_mips16): Check opcode entries for validity against the ISA level and ASE set selected. binutils/ * testsuite/binutils-all/mips/mips16-undecoded.s: Use `.module' rather than `.set' to set the ISA level. gas/ * testsuite/gas/mips/mips16-sub.d: New test. * testsuite/gas/mips/mips16-32@mips16-sub.d: New test. * testsuite/gas/mips/mips16e-32@mips16-sub.d: New test. * testsuite/gas/mips/mips16e-sub.d: New test. * testsuite/gas/mips/mips16-32@mips16e-sub.d: New test. * testsuite/gas/mips/mips16-64@mips16e-sub.d: New test. * testsuite/gas/mips/mips16e-64-sub.d: New test. * testsuite/gas/mips/mips16-32@mips16e-64-sub.d: New test. * testsuite/gas/mips/mips16-64@mips16e-64-sub.d: New test. * testsuite/gas/mips/mips16e-32@mips16e-64-sub.d: New test. * testsuite/gas/mips/mips16-sub.s: New test source. * testsuite/gas/mips/mips16e-sub.s: New test source. * testsuite/gas/mips/mips16e-64-sub.s: New test source. * testsuite/gas/mips/mips.exp: Run the new tests.
2016-12-20MIPS16: Switch to 32-bit opcode table interpretationMaciej W. Rozycki3-81/+90
Switch to 32-bit MIPS16 opcode table entry interpretation, similar to how the microMIPS opcode table is handled, for both the `match' and `mask' fields, removing special casing for JAL and JALX instructions and their `a' and `i' operand codes throughout, while retaining automatic processing of extendable opcodes in assembly and disassembly. In assembly disallow size enforcement suffixes as appropriate: `.t' for both 32-bit instructions and macros and `.e' for macros only, making macro handling consistent with the microMIPS instruction set. In disassembly fully decode EXTEND prefixes prepended to unsupported instruction encodings (according to the ISA selection) rather than dumping them as hexadecimal data along with the following instruction, removing all special casing for the EXTEND prefix and making its handling rely on its opcode table entry, except where it is considered a part of an extendable instruction. include/ * opcode/mips.h (mips_opcode_32bit_p): New inline function. gas/ * config/tc-mips.c (micromips_insn_length): Use `mips_opcode_32bit_p'. (is_size_valid): Adjust description. (is_size_valid_16): New function. (validate_mips_insn): Use `mips_opcode_32bit_p' in MIPS16 operand decoding. (validate_mips16_insn): Remove `a' and `i' operand code special casing, use `mips_opcode_32bit_p' to determine instruction width. (append_insn): Adjust forced MIPS16 instruction size determination. (match_mips16_insn): Likewise. Don't shift the instruction's opcode with the `a' and `i' operand codes. Use `mips_opcode_32bit_p' in operand decoding. (match_mips16_insns): Check for forced instruction size's validity. (mips16_ip): Don't force instruction size in the `noautoextend' mode. * testsuite/gas/mips/mips16-jal-e.d: New test. * testsuite/gas/mips/mips16-jal-t.d: New test. * testsuite/gas/mips/mips16-macro-e.d: New test. * testsuite/gas/mips/mips16-macro-t.d: New test. * testsuite/gas/mips/mips16-jal-t.l: New stderr output. * testsuite/gas/mips/mips16-macro-e.l: New stderr output. * testsuite/gas/mips/mips16-macro-t.l: New stderr output. * testsuite/gas/mips/mips16-jal-e.s: New test source. * testsuite/gas/mips/mips16-jal-t.s: New test source. * testsuite/gas/mips/mips16-macro-e.s: New test source. * testsuite/gas/mips/mips16-macro-t.s: New test source. * testsuite/gas/mips/mips.exp: Run the new tests. opcodes/ * mips-dis.c (print_mips16_insn_arg): Always handle `extend' and `insn' together, with `extend' as the high-order 16 bits. (match_kind): New enum. (print_insn_mips16): Rework for 32-bit instruction matching. Do not dump EXTEND prefixes here. * mips16-opc.c (mips16_opcodes): Move "extend" entry to the end. Recode `match' and `mask' fields as 32-bit in absolute "jal" and "jalx" entries. binutils/ * testsuite/binutils-all/mips/mips16-extend-noinsn.d: Adjust test for separate EXTEND prefix disassembly.
2016-12-20MIPS16/opcodes: Correct 64-bit macros' ISA membershipMaciej W. Rozycki2-6/+12
Limit the DDIV, DDIVU, DREM, DREMU and DSUBU macros to the MIPS III rather than MIPS I ISA. These macros expand to machine code sequences including 64-bit instructions which require a 64-bit ISA. Entries for those instructions are already correctly marked, however the marking is ignored if entries are used in the process of macro expansion rather than directly, making it possible to indirectly produce 64-bit machine code even when output requested has been limited to a 32-bit ISA. opcodes/ * mips16-opc.c (mips16_opcodes): Set membership to I3 rather than I1 for the "ddiv", "ddivu", "drem", "dremu" and "dsubu" INSN_MACRO entries. gas/ * testsuite/gas/mips/mips16-macro.l: New list test. * testsuite/gas/mips/mips.exp: Run the new test.
2016-12-20MIPS16/opcodes: Correct I64/SDRASP opcode's ISA membershipMaciej W. Rozycki2-1/+7
Limit the `SD ra, offset(sp)' instruction (I64/SDRASP major/minor opcode) to the MIPS III rather than MIPS I ISA. This is a 64-bit instruction requiring a 64-bit ISA. This bug has been there since forever. opcodes/ * mips16-opc.c (mips16_opcodes): Set membership to I3 rather than I1 for the SP-relative "sd"/$ra entry (SDRASP minor opcode). gas/ * testsuite/gas/mips/mips16-sdrasp.d: New test. * testsuite/gas/mips/mips16-sdrasp.l: New stderr output. * testsuite/gas/mips/mips16-sdrasp.s: New test source. * testsuite/gas/mips/mips.exp: Run the new test.
2016-12-20Correct assembler mnemonic for RISC-V aqrl AMOsAndrew Waterman2-22/+27
sc is a misnomer, because they aren't inherently sc. * riscv-opc.c (riscv_opcodes): Rename the "*.sc" instructions to "*.aqrl".
2016-12-20Fix disassembly of RISC-V CSR instructions under -Mno-aliasesAndrew Waterman2-22/+27
This fixes https://github.com/riscv/riscv-binutils-gdb/issues/36. * riscv-opc.c (riscv_opcodes): Mark the rd* and csr* aliases as INSN_ALIAS.
2016-12-20Add canonical JALR for RISC-VAndrew Waterman2-0/+8
jalr rd,offset(rs1) rather than jalr rd,rs1,offset This matches the format of other instructions. * riscv-opc.c (riscv_opcodes): Change jr and jalr to "o(s)" format.
2016-12-20Re-work RISC-V gas flags: now we just support -mabi and -marchAndrew Waterman2-2/+11
We've decided to standardize on two flags for RISC-V: "-march" sets the target architecture (which determines which instructions can be generated), and "-mabi" sets the target ABI. We needed to rework this because the old flag set didn't support soft-float or single-float ABIs, and didn't support an x32-style ABI on RISC-V. Additionally, we've changed the behavior of the -march flag: it's now a lot stricter and only parses things we can actually understand. Additionally, it's now lowercase-only: the rationale is that while the RISC-V ISA manual specifies that ISA strings are case-insensitive, in Linux-land things are usually case-sensitive. Since this flag can be used to determine library paths, we didn't want to bake some case-insensitivity in there that would case trouble later. This patch implements these two new flags and removes the old flags that could conflict with these. There wasn't a RISC-V release before, so we want to just support a clean flag set. include/ * elf/riscv.h (EF_RISCV_SOFT_FLOAT): Don't define. (EF_RISCV_FLOAT_ABI, EF_RISCV_FLOAT_ABI_SOFT): Define. (EF_RISCV_FLOAT_ABI_SINGLE, EF_RISCV_FLOAT_ABI_DOUBLE): Define. (EF_RISCV_FLOAT_ABI_QUAD): Define. bfd/ * elfnn-riscv.c (_bfd_riscv_elf_merge_private_bfd_data): Use EF_RISCV_FLOAT_ABI_SOFT instead of EF_RISCV_SOFT_FLOAT. binutils/ * readelf.c (get_machine_flags): Use EF_RISCV_FLOAT_ABI_{SOFT,SINGLE,DOBULE,QUAD) instead of EF_RISCV_{SOFT,HARD}_FLOAT. gas/ * config/tc-riscv.h (xlen): Delete. * config/tc-riscv.c (xlen): Make static. (abi_xlen): New variable. (options): Replace OPTION_{M32,M64,MSOFT_FLOAT,MHARD_FLOAT,MRVC} with OPTION_MABI. (md_longopts): Likewise. (md_parse_option): Likewise. (riscv_elf_final_processing): Likewise. * doc/as.texinfo (Target RISC-V options): Likewise. * doc/c-riscv.texi (OPTIONS): Likewise. * config/tc-riscv.c (float_mode): Removed. (float_abi): New type, specifies the floating-point ABI. (riscv_set_abi): New function. (riscv_add_subset): Only allow lower-case ISA names and require them to start with "rv". (riscv_after_parse_args): Likewise. opcodes/ * riscv-dis.c (riscv_disassemble_insn): Default to the ELF's XLEN when none is provided.
2016-12-20Formatting changes for RISC-VAndrew Waterman2-8/+10
This is a mixed bag of format changes: * Replacing constants with macros (0xffffffff with MINUS_ONE, for example). There's one technically functional change in here (some MINUS_ONEs are changed to 0), but it only changes the behavior of an otherwise-unused field. * Using 0 instead of 0x0 in the relocation table. * There were some missing spaces before parens, the spaces have been added. * A handful of comments are now more descriptive. * A bunch of whitespace-only changes, mostly alignment and brace newlines. bfd/ * elfnn-riscv.c: Formatting and comment fixes throughout. * elfxx-riscv.c: Likewise. (howto_table): Change the src_mask field from MINUS_ONE to 0 for R_RISCV_TLS_DTPMOD32, R_RISCV_TLS_DTPMOD64, R_RISCV_TLS_DTPREL32, R_RISCV_TLS_DTPREL64, R_RISCV_TLS_TPREL32, R_RISCV_TLS_TPREL64. opcodes/ * riscv-opc.c: Formatting fixes. gas/ * config/tc-riscv.c: Formatting and comment fixes throughout.
2016-12-20Add opcodes RISC-V dependenciesAlan Modra4-0/+14
* Makefile.am (TARGET_LIBOPCODES_CFILES): Add riscv files. * Makefile.in: Regenerate. * po/POTFILES.in: Regenerate.
2016-12-19MIPS/opcodes: Only examine ELF file structures if SYMTAB_AVAILABLEMaciej W. Rozycki2-1/+6
Correct commit 640c0ccdc980 ("some objdump -M options, better reg dumps"), <https://sourceware.org/ml/binutils/2002-12/msg00706.html>, and only execute code setting up disassembler options based on ELF file structures if SYMTAB_AVAILABLE is set. opcodes/ * mips-dis.c (set_default_mips_dis_options) [SYMTAB_AVAILABLE]: Only examine ELF file structures here.
2016-12-19MIPS/opcodes: Only call `bfd_mips_elf_get_abiflags' if BFD64Maciej W. Rozycki2-2/+14
Complement commit 5e7fc731f80e ("MIPS/opcodes: Also set disassembler's ASE flags from ELF structures") and fix an `--enable-targets=all' GDB build regression on 32-bit hosts where the MIPS target is a secondary: ../opcodes/libopcodes.a(mips-dis.o): In function `set_default_mips_dis_options': mips-dis.c:(.text+0x906): undefined reference to `bfd_mips_elf_get_abiflags' collect2: error: ld returned 1 exit status make[2]: *** [gdb] Error 1 by avoiding making a call to the `bfd_mips_elf_get_abiflags' function, which is not available, because there is no MIPS/ELF BFD included in 32-bit BFD builds. This call is only made from a conditional code block guarded by a check against `bfd_target_elf_flavour', which is dead in such a configuration, however cannot be optimized away by the compiler. Also some other MIPS BFDs may be available, such as a.out, ECOFF or PE, so the disassembler has to remain functional. opcodes/ * mips-dis.c (set_default_mips_dis_options) [BFD64]: Only call `bfd_mips_elf_get_abiflags' here.
2016-12-16Fix compile time warning building arm-dis.cNick Clifton2-2/+7
2016-12-14MIPS/opcodes: Also set disassembler's ASE flags from ELF structuresMaciej W. Rozycki2-2/+48
Respect any ASE flags recorded in ELF file structures for the purpose of selecting instructions to be disassembled, preventing code from being hex-dumped even though having been clearly indicated as valid at the assembly time. Use date from the MIPS ABI flags structure if present, and otherwise there may be an MDMX ASE flag set in the ELF file header. For backwards compatibility only set extra flags and do not clear any, preserving all previously set by the architecture selected to be disassembled for. include/ * elf/mips.h (Elf_Internal_ABIFlags_v0): Also declare struct typedef as `elf_internal_abiflags_v0'. bfd/ * bfd-in.h (elf_internal_abiflags_v0): New struct declaration. (bfd_mips_elf_get_abiflags): New prototype. * elfxx-mips.c (bfd_mips_elf_get_abiflags): New function. * bfd-in2.h: Regenerate. opcodes/ * mips-dis.c (mips_convert_abiflags_ases): New function. (set_default_mips_dis_options): Also infer ASE flags from ELF file structures. binutils/ * testsuite/binutils-all/mips/mips-ase-1.d: New test. * testsuite/binutils-all/mips/mips-ase-2.d: New test. * testsuite/binutils-all/mips/mips-ase-3.d: New test. * testsuite/binutils-all/mips/mips-ase-1.s: New test source. * testsuite/binutils-all/mips/mips-ase-2.s: New test source. * testsuite/binutils-all/mips/mips.exp: Run the new tests.
2016-12-14MIPS/opcodes: Reorder ELF file header flag handling in disassemblerMaciej W. Rozycki2-13/+18
Move ELF file header flag interpretation code, used to set disassembler options, beyond architecture setup. No functional change as the effects of both code sections are disjoint from each other, but this provides for a further expansion of ELF file header flag interpretation. opcodes/ * mips-dis.c (set_default_mips_dis_options): Reorder ELF file header flag interpretation code.
2016-12-14MIPS16: Fix SP-relative SD instruction annotationMaciej W. Rozycki2-2/+7
Fix the annotation of SP-relative SD instructions incorrectly marked as reading from the PC rather than SP, which in turn prevented their 16-bit forms from being scheduled into jump delay slots. This bug has been there since forever. opcodes/ * mips16-opc.c (mips16_opcodes): Set RD_SP rather than RD_PC in `pinfo2' with SP-relative "sd" entries. gas/ * testsuite/gas/mips/mips16-sprel-swap.d: New test. * testsuite/gas/mips/mips16-sprel-swap.s: New test source. * testsuite/gas/mips/mips.exp: Run the new test.
2016-12-14MIPS16/opcodes: Fix and clarify MIPS16e commentaryMaciej W. Rozycki2-4/+9
Correct the note about JALRC/JRC being compact jumps rather than branches, and add a reference from where the remaining MIPS16e additions live and the jumps used to be too, complementing commit ceb94aa50d68 ("Update insn_mo when converting to a MIPS16e compact jump"), <https://sourceware.org/ml/binutils/2011-06/msg00369.html>. opcodes/ * mips16-opc.c (mips16_opcodes): Update comments on MIPS16e compact jumps.
2016-12-13[Binutils][AARCH64]Remove Cn register for coprocessor CRn, CRm fieldRenlin Li6-25/+29
The internal CN register representation for coprocessor fields used in aarch64 sys, sysl instructions are removed in this patch. After the change, those fields are represented as immediate. Related checks are added as well. opcodes/ * aarch64-opc.c (aarch64_opnd_qualifiers): New CR value range qualifier. (operand_general_constraint_met_p): Remove case for CP_REG. (aarch64_print_operand): Print CRn, CRm operand using imm field. * aarch64-tbl.h (QL_SYS): Use CR qualifier. (QL_SYSL): Likewise. (aarch64_opcode_table): Change CRn, CRm operand class and type. * aarch64-opc-2.c : Regenerate. * aarch64-asm-2.c : Likewise. * aarch64-dis-2.c : Likewise. include/ * opcode/aarch64.h (aarch64_operand_class): Remove AARCH64_OPND_CLASS_CP_REG. (enum aarch64_opnd): Change AARCH64_OPND_Cn to AARCH64_OPND_CRn, AARCH64_OPND_Cm to AARCH64_OPND_CRm. (aarch64_opnd_qualifier): Define AARCH64_OPND_QLF_CR qualifier. gas/ * config/tc-aarch64.c (AARCH64_REG_TYPES): Remove CN register. (get_reg_expected_msg): Remove CN register case. (parse_operands): rewrite parser for CRn, CRm operand. (reg_names): Remove CN register. * testsuite/gas/aarch64/diagnostic.s: Add a new test case. * testsuite/gas/aarch64/diagnostic.l: Adjust error message.
2016-12-12Handle memory error in print_insn_rxYao Qi2-4/+36
Nowadays, memory error in rx disassembly is not handled, so if I start a fresh GDB, and disassemble, (gdb) set architecture rx The target architecture is assumed to be rx (gdb) disassemble 0x0,+4 Dump of assembler code from 0x0 to 0x4: 0x00000000: brk 0x00000001: brk 0x00000002: brk 0x00000003: brk the output is wrong. This patch adds code to call dis->memory_error_func on memory error, and longjmp to print_insn_rx. With this patch applied, (gdb) set architecture rx The target architecture is assumed to be rx (gdb) disassemble 0,+4 Dump of assembler code from 0x0 to 0x4: 0x00000000: Cannot access memory at address 0x0 opcodes: 2016-12-12 Yao Qi <yao.qi@linaro.org> * rx-dis.c: Include <setjmp.h> (struct private): New. (rx_get_byte): Check return value of read_memory_func, and call memory_error_func and OPCODES_SIGLONGJMP on error. (print_insn_rx): Call OPCODES_SIGSETJMP.
2016-12-12Handle memory error in print_insn_rl78_commonYao Qi2-4/+36
Nowadays, memory error in rl78 disassembly is not handled, so if I start a fresh GDB, and disassemble, (gdb) set architecture rl78 The target architecture is assumed to be rl78 (gdb) disassemble 0x0,+4 Dump of assembler code from 0x0 to 0x4: 0x00000000: nop 0x00000001: nop 0x00000002: nop 0x00000003: nop the output is wrong. This patch adds code to call dis->memory_error_func on memory error, and longjmp to print_insn_rl78_common. With this patch applied, (gdb) set architecture rl78 The target architecture is assumed to be rl78 (gdb) disassemble 0,+4 Dump of assembler code from 0x0 to 0x4: 0x00000000: Cannot access memory at address 0x0 opcodes: 2016-12-12 Yao Qi <yao.qi@linaro.org> * rl78-dis.c: Include <setjmp.h>. (struct private): New. (rl78_get_byte): Check return value of read_memory_func, and call memory_error_func and OPCODES_SIGLONGJMP on error. (print_insn_rl78_common): Call OPCODES_SIGJMP.
2016-12-09MIPS16: Remove unused `>' operand codeMaciej W. Rozycki2-2/+4
This code has never been used throughout the repository history, and likely not before either, as due to the assymetry of MIPS16 instruction set encoding there are no 32-bit shift operations having their immediate shift count placed in the position of the usual `rx' instruction field. gas/ * config/tc-mips.c (mips16_macro_build) <'>'>: Remove case. include/ * opcode/mips.h: Remove references to `>' operand code. opcodes/ * mips16-opc.c (decode_mips16_operand) <'>'>: Remove cases.
2016-12-09MIPS16/opcodes: Use hexadecimal interpretation for the `e' operand codeMaciej W. Rozycki2-1/+6
Make the `e' operand code used with raw EXTEND instructions use the hexadecimal rather than decimal format, for consistency with what is actually produced by code in `print_insn_mips16' dedicated to EXTEND disassembly. Due to that special handling the operand code is only interpreted for assembly however, which accepts either format either way, so there is no functional change here. opcodes/ * mips16-opc.c (decode_mips16_operand) <'e'>: Use HINT rather than UINT. gas/ * testsuite/gas/mips/mips16-extend.d: New test. * testsuite/gas/mips/mips16-extend.s: New test source. * testsuite/gas/mips/mips.exp: Run the new test.
2016-12-09MIPS16/opcodes: Reformat raw EXTEND and undecoded outputMaciej W. Rozycki2-4/+11
Use a tab rather than a space to separate `extend' and its uninterpreted argument output, like with regular instructions. Separate hexadecimal halves of undecoded extended instructions output with a space instead of presenting them concatenated. opcodes/ * mips-dis.c (print_insn_mips16): Use a tab rather than a space to separate `extend' and its uninterpreted argument output. Separate hexadecimal halves of undecoded extended instructions output. binutils/ * testsuite/binutils-all/mips/mips16-extend-noinsn.d: New test. * testsuite/binutils-all/mips/mips16-extend-noinsn.s: New test source. * testsuite/binutils-all/mips/mips.exp: Run the new test.
2016-12-08MIPS16/opcodes: Fix off-by-one indentation in `print_mips16_insn_arg'Maciej W. Rozycki2-30/+35
opcodes/ * mips-dis.c (print_mips16_insn_arg): Remove extraneous indentation space across.
2016-12-08MIPS16/opcodes: Fix PC-relative operation delay-slot adjustmentMaciej W. Rozycki2-6/+16
Complement commit dd8b7c222e0e ("MIPS: mips16e jalrc/jrc opcodes"), <https://sourceware.org/ml/binutils/2005-07/msg00349.html>, and stop the disassembler making a delay-slot adjustment for PC-relative operations following either MIPS16e compact jumps, or undefined RR/J(AL)R(C) encodings that have the `l' (link) and `ra' (source register is `ra') bits set both at a time. Adjust code description for accuracy. Add a suitable test case. opcodes/ * mips-dis.c (print_mips16_insn_arg): Avoid delay-slot adjustment for PC-relative operations following MIPS16e compact jumps or undefined RR/J(AL)R(C) encodings. binutils/ * testsuite/binutils-all/mips/mips16-pcrel.d: New test. * testsuite/binutils-all/mips/mips16-pcrel.s: New test source. * testsuite/binutils-all/mips/mips.exp: Run the new test.
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