aboutsummaryrefslogtreecommitdiff
path: root/opcodes
AgeCommit message (Expand)AuthorFilesLines
2020-03-03x86: Replace IgnoreSize/DefaultSize with MnemonicSizeH.J. Lu5-10857/+10874
2020-03-03The patch fixed invalid compilation of instruction LD IY,(HL) and disassemble...Sergey Belyashov2-2/+8
2020-03-03x86: Allow integer conversion without suffix in AT&T syntaxH.J. Lu3-20/+189
2020-02-26Indent labelsAlan Modra10-24/+36
2020-02-25[ARC][committed] Update int_vector_base aux register.Claudiu Zissulescu2-2/+6
2020-02-20RISC-V: Support the ISA-dependent CSR checking.Nelson Chu2-1/+6
2020-02-19RISC-V: Convert the ADD/ADDI to the compressed MV/LI if RS1 is zero.Jim Wilson2-0/+7
2020-02-17x86: Remove CpuABM and add CpuPOPCNTH.J. Lu6-2822/+2848
2020-02-17x86: fold certain VCVT{,U}SI2S{S,D} templatesJan Beulich3-133/+38
2020-02-17x86: fold AddrPrefixOpReg templatesJan Beulich3-201/+52
2020-02-17x86/Intel: improve diagnostics for ambiguous VCVT* operandsJan Beulich3-33/+194
2020-02-16x86: Don't disable SSE3 when disabling SSE4aH.J. Lu3-2/+7
2020-02-17Re: x86: Don't disable SSE4a when disabling SSE4Alan Modra2-2/+6
2020-02-16x86: Don't disable SSE4a when disabling SSE4H.J. Lu3-4/+9
2020-02-14Remove Intel syntax comments on movsx and movzxH.J. Lu2-3/+7
2020-02-14x86: replace adhoc (partly wrong) ambiguous operand checking for MOVSX/MOVZXJan Beulich3-118/+21
2020-02-13x86: fix SSE4a dependencies of ".arch .nosse*"Jan Beulich3-4/+21
2020-02-12x86: correct VFPCLASSP{S,D} operand size handlingJan Beulich3-4/+44
2020-02-12x86: fold two JMP templatesJan Beulich3-16/+8
2020-02-12x86-64: Intel64 adjustments for insns dealing with far pointersJan Beulich4-25/+136
2020-02-11x86: drop ShortForm attributeJan Beulich5-10944/+10952
2020-02-11x86: drop stray ShortForm attributesJan Beulich3-12/+18
2020-02-11Ensure *valuep always written by extract_normal returnAlan Modra16-15/+68
2020-02-10[binutils][arm] Implement Custom Datapath Extensions for MVEMatthew Malcomson2-0/+45
2020-02-10[binutils][arm] arm support for ARMv8.m Custom Datapath ExtensionMatthew Malcomson2-1/+221
2020-02-10x86: Accept Intel64 only instruction by defaultH.J. Lu5-3948/+3974
2020-02-07Add support for the GBZ80 and Z80N variants of the Z80 architecture, and add ...Sergey Belyashov2-20/+158
2020-02-04ubsan: d30v: negation of -2147483648Alan Modra2-2/+6
2020-02-03ubsan: m32c: left shift of negative valueAlan Modra2-2/+6
2020-02-01ubsan: frv: left shift of negative valueAlan Modra2-3/+7
2020-01-31x86: replace EXxmm_mdq by EXVexWdqScalarJan Beulich3-27/+29
2020-01-31x86: drop unused EXVexWdq / vex_w_dq_modeJan Beulich2-7/+10
2020-01-31aarch64: Fix MOVPRFX markup for bf16 conversionsRichard Sandiford2-2/+7
2020-01-30ubsan: m32c: left shift of negative valueAlan Modra2-12/+16
2020-01-30cpu,opcodes,gas: fix neg and neg32 instructions in BPFJose E. Marchesi2-4/+8
2020-01-30x86-64: honor vendor specifics for near RETJan Beulich4-6/+55
2020-01-30x86: drop further pointless/bogus DefaultSizeJan Beulich3-17/+25
2020-01-30ubsan: tic4x: left shift cannot be represented in type 'int'Alan Modra2-1/+5
2020-01-27x86-64: Properly encode and decode movsxdH.J. Lu4-6/+108
2020-01-27AArch64: Fix cfinv disassembly issuesTamar Christina5-1278/+1293
2020-01-21x86: improve handling of insns with ambiguous operand sizesJan Beulich3-2/+7
2020-01-21x86: VCVTNEPS2BF16{X,Y} should permit broadcastingJan Beulich3-8/+15
2020-01-20Updated translations for various binutils sub-directoriesNick Clifton4-1053/+1365
2020-01-20ubsan: hppa: negation of -2147483648Alan Modra2-1/+5
2020-01-20ubsan: arm: out of bounds array accessAlan Modra2-1/+5
2020-01-18Update version to 2.34.50. Regenerate configure and .pot files.Nick Clifton3-38/+43
2020-01-18Add markers for 2.34 branch to the NEWS files and ChangeLogs.Nick Clifton1-0/+4
2020-01-17Fix spelling errorsChristian Biesinger2-1/+5
2020-01-17x86: Add {vex} pseudo prefixH.J. Lu3-0/+18
2020-01-16[binutils][arm] PR25376 Change MVE into a CORE_HIGH featureAndre Vieira2-232/+248
generated by cgit v1.1 at 2024-11-23 14:15:31 +0000