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2016-07-08FT32: adjust disassembly opcode match fieldsjamesbowman2-2/+7
2016-07-01x86: allow suffix-less movzw and 64-bit movzbJan Beulich3-80/+14
2016-07-01x86: remove stray instruction attributesJan Beulich3-88/+103
2016-07-01x86/Intel: fix operand checking for MOVSDJan Beulich3-4/+9
2016-06-30Fix typo in commentYao Qi2-1/+5
2016-06-28[AArch64] Make register indices be full 64-bit valuesRichard Sandiford2-2/+19
2016-06-25remove a few sentinalsTrevor Saunders3-8/+13
2016-06-23[ARC] Misc minor edits/fixesGraham Markall2-3/+6
2016-06-22Add support for yet some more new ISA 3.0 instructions.Peter Bergner2-5/+54
2016-06-22addmore extern CTrevor Saunders2-0/+12
2016-06-21Arc assembler: Convert nps400 from a machine type to an extension.Graham Markall4-198/+208
2016-06-17opcodes,gas: sparc: fix rdasr,wrasr,rdpr,wrpr,rdhpr,wrhpr insns.Jose E. Marchesi3-52/+146
2016-06-17opcodes,gas: adjust sparc insns and make GAS aware of itJose E. Marchesi2-170/+175
2016-06-17bfd,opcodes: sparc: new opcode v9{c,d,e,v,m} architectures and bfd machine nu...Jose E. Marchesi3-9/+90
2016-06-15Fix simple gas testsuite failures.Nick Clifton2-14/+49
2016-06-15opcodes/arc: Fix extract for some add_s instructionsAndrew Burgess2-1/+5
2016-06-14opcode/gas: Fix incorrect dates on ChangeLog entriesGraham Markall1-3/+3
2016-06-14[ARC] Add ldbit for npsGraham Markall3-0/+62
2016-06-14[ARC] Add deep packet inspection instructions for npsGraham Markall3-15/+205
2016-06-14[ARC] Add arithmetic and logic instructions for npsGraham Markall3-1/+293
2016-06-10S/390: Dump unknown instructions according to their length.Andreas Krebbel2-17/+48
2016-06-09Print symbol names in comments for LDS/STS disassembly.Denis Chertykov2-4/+15
2016-06-07PowerPC VLEAlan Modra3-3666/+3678
2016-06-07[ARM] Add command line option for RAS extension.Matthew Wahab2-2/+7
2016-06-03Re-add support for lbarx, lharx, stbcx. and sthcx. insns back to the E6500 cpu.Peter Bergner2-4/+10
2016-06-03Handle indirect branches for AMD64 and Intel64H.J. Lu4-7/+75
2016-06-02Add support for 48 and 64 bit ARC instructions.Andrew Burgess4-93/+722
2016-06-01add more extern CTrevor Saunders3-0/+21
2016-06-01Add support for some variants of the ARC nps400 rflt instruction.Graham Markall2-5/+19
2016-05-31sh: make constant unsigned to avoid narrowingTrevor Saunders2-1/+6
2016-05-29Add missing ChangeLog entriesH.J. Lu1-0/+10
2016-05-29Add .noavx512XX directives to x86 assemblerH.J. Lu2-0/+81
2016-05-27Update x86 CPU_XXX_FLAGS handlingH.J. Lu5-5452/+5631
2016-05-27Replace CpuAMD64/CpuIntel64 with AMD64/Intel64H.J. Lu6-10532/+10554
2016-05-27Correct CpuMax in i386-opc.hH.J. Lu4-4/+20
2016-05-27Improve the MSP430 disassembler's handling of memory read errors.Nick Clifton2-272/+408
2016-05-26Add support for new POWER ISA 3.0 instructions.Peter Bergner2-0/+13
2016-05-25Enable VREX for all AVX512 directivesH.J. Lu3-49/+58
2016-05-25Enable VREX for AVX512 directivesH.J. Lu3-8/+15
2016-05-25Reimplement .no87/.nommx/.nosse/.noavx directivesH.J. Lu3-2/+17
2016-05-23[ARC] Update instruction type and delay slot info.Claudiu Zissulescu4-113/+144
2016-05-23[ARC] Add XY registers, update neg instruction.Claudiu Zissulescu2-0/+7
2016-05-23[ARC] Rename "class" named attributes.Claudiu Zissulescu3-5/+11
2016-05-23tic54x: rename typedef of struct symbol_Trevor Saunders3-7/+12
2016-05-19Correct "Fix powerpc subis range"Alan Modra2-1/+5
2016-05-19Fix powerpc subis rangeAlan Modra2-12/+26
2016-05-18MIPS/opcodes: Correct mixed MIPS16 and microMIPS disassemblyMaciej W. Rozycki2-17/+28
2016-05-13Accept valid one byte signed and unsigned values for the IMM8 operand.Peter Bergner2-1/+5
2016-05-11Add MIPS32 DSPr3 support.Matthew Fortune3-2/+11
2016-05-10Enable Intel RDPID instruction.Alexander Fomin7-5308/+5365
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