| Age | Commit message (Expand) | Author | Files | Lines |
|---|
| 2015-11-23 | opcodes: handle mach-o for thumb/arm disambiguation. | Tristan Gingold | 2 | -0/+12 |
| 2015-11-20 | [AArch64] Add support for ARMv8.1 Virtulization Host Extensions. | Matthew Wahab | 2 | -0/+78 |
| 2015-11-20 | Remove a if-clause that is redundant because the same test has been performed... | Nick Clifton | 2 | -4/+5 |
| 2015-11-20 | Update translations. | Nick Clifton | 2 | -317/+1153 |
| 2015-11-19 | [AArch64] Reject invalid immediate operands to MSR PAN | Matthew Wahab | 2 | -0/+13 |
| 2015-11-17 | Fix the disassembly of conditional instructions will illegal condition select... | Nick Clifton | 2 | -1/+6 |
| 2015-11-14 | Bump version to 2.26.51 | Tristan Gingold | 2 | -10/+14 |
| 2015-11-11 | Add assembler, disassembler and linker support for power9. | Peter Bergner | 3 | -107/+686 |
| 2015-11-09 | Move copy_u.w to MSA64 ASE, remove copy_u.d. | Robert Suchanek | 1 | -2/+1 |
| 2015-11-02 | Disassemble RX NOP instructions as such. | Nick Clifton | 3 | -18/+98 |
| 2015-11-02 | Fix disassembly of RX zero-offset register indirect instructions. | Nick Clifton | 4 | -7/+14 |
| 2015-10-28 | Pass noaliases_p to aarch64_decode_insn | Yao Qi | 2 | -5/+15 |
| 2015-10-27 | Fix RL78 disassembly of DE+offset addressing to always show the offset, even ... | Vinay Kumar | 3 | -24/+31 |
| 2015-10-27 | Display system registers by their names when disassembling RL78 instructions. | Vinay Kumar | 4 | -13/+34 |
| 2015-10-27 | Fix RL78 disassembly so that SP+OFFSET addressing always shows the offset, ev... | Vinay Kumar | 3 | -20/+27 |
| 2015-10-14 | Add missing changelog entries | Andreas Krebbel | 1 | -0/+7 |
| 2015-10-14 | S/390: Fix instruction type of troo, trot, trto, and trtt. | Andreas Krebbel | 2 | -5/+5 |
| 2015-10-08 | Fix compile time warning compiling ARC port. | Nick Clifton | 2 | -1/+6 |
| 2015-10-07 | Avoid using 'template' C++ keyword | Yao Qi | 3 | -3/+9 |
| 2015-10-07 | New ARC implementation. | Nick Clifton | 9 | -2824/+21958 |
| 2015-10-02 | [aarch64] expose disas_aarch64_insn and rename it to aarch64_decode_insn | Yao Qi | 2 | -4/+12 |
| 2015-10-02 | [aarch64] Remove argument pc from disas_aarch64_insn | Yao Qi | 2 | -3/+7 |
| 2015-09-29 | Add support for extensions in the .machine pseudoop on S/390, e.g. ".machine ... | Dominik Vogt | 3 | -508/+522 |
| 2015-09-28 | Updare French translation for binutils and German translation for opcodes. | Nick Clifton | 2 | -3/+7 |
| 2015-09-28 | Patches for illegal ppc 500 instructions | Tom Rix | 2 | -7/+11 |
| 2015-09-25 | The FT32's disassembly of 10-bit literals has the incorrect mask. | jamesbowman | 1 | -1/+1 |
| 2015-09-23 | Fix compile time warnings generated when compiling with clang. | Nick Clifton | 11 | -44/+50 |
| 2015-09-22 | Enhance the RX disassembler to detect and report bad instructions. | Nick Clifton | 4 | -28/+57 |
| 2015-09-22 | opcodes/ppc-opc.c: Add dscr and ctrl SPR mnemonics | Anton Blanchard | 2 | -0/+8 |
| 2015-09-10 | S/390: Fix instruction format of crj*, clrj*, and clgrj*. | Andreas Krebbel | 1 | -3/+3 |
| 2015-09-10 | S/390: Remove F_20 and FE_20. Adjust comments. | Andreas Krebbel | 1 | -70/+66 |
| 2015-09-10 | S/390: Fix MASK_RIE_R0PI and MASK_RIE_R0PU. | Andreas Krebbel | 1 | -2/+2 |
| 2015-09-09 | S/390: Remove trailing zeros on 4-bytes opcodes. | Andreas Krebbel | 2 | -7/+9 |
| 2015-09-09 | S/390: Fix opcode of ppno. | Andreas Krebbel | 1 | -1/+1 |
| 2015-08-25 | Support for the sparc %pmcdper privileged register. | Jose E. Marchesi | 2 | -2/+11 |
| 2015-08-24 | Fix the partial disassembly of a broken three byte instruction at the end of ... | Jan Stancek | 2 | -2/+8 |
| 2015-08-21 | PR binutils/18257: Properly decode x86/Intel mask instructions. | Alexander Fomin | 2 | -59/+450 |
| 2015-08-17 | Trailing space in opcodes/ generated files | Alan Modra | 5 | -845/+835 |
| 2015-08-13 | Fixes for unpredictable nops and 26-bit versions of teq,tst,cmn,cmp. | Andre Vieira | 2 | -3/+19 |
| 2015-08-12 | [MIPS] Map 'move' to 'or'. | Simon Dardis | 3 | -3/+8 |
| 2015-08-12 | Remove trailing spaces in opcodes | H.J. Lu | 137 | -4012/+4012 |
| 2015-08-11 | Fix the disassembly of the AArch64 SIMD EXT instruction. | Nick Clifton | 2 | -1/+7 |
| 2015-08-10 | Add SIGRIE instruction for MIPS R6 | Robert Suchanek | 2 | -0/+5 |
| 2015-08-07 | Remove CpuFMA4 support from CPU_ZNVER1_FLAGS. | Amit Pawar | 3 | -2/+7 |
| 2015-07-30 | Properly disassemble movnti in Intel mode | H.J. Lu | 2 | -5/+20 |
| 2015-07-27 | Regenerate configure files | H.J. Lu | 2 | -2/+6 |
| 2015-07-23 | Fix ubsan signed integer overflow | Alan Modra | 2 | -3/+8 |
| 2015-07-22 | Fix memory operand size for vcvtt?ps2u?qq instructions | H.J. Lu | 2 | -4/+13 |
| 2015-07-16 | Updates the ARM disassembler's output of floating point constants to include ... | Alessandro Marzocchi | 2 | -2/+40 |
| 2015-07-14 | Sync config/warnings.m4 with GCC | H.J. Lu | 2 | -0/+16 |
