Age | Commit message (Collapse) | Author | Files | Lines |
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* sparc-opc.c: Added sparclite extended FP operations, and versions of v9
impdep* instructions permitting specification of the OPF field.
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explicitly specified sizes, instead of using sizeof() on host CPU types.
(INVALID_FLOAT): Cast first argument.
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* ns32k-dis.c: Deleted all code in "#ifdef GDB".
(invalid_float): Enabled general version, doesn't require running
on ns32k host.
Sun Jul 10 00:27:47 1994 Ian Dall (dall@hfrd.dsto.gov.au)
* opcodes/ns32k-dis.c: Semi-new file. Had apparently been dropped
from distribution. A ns32k-dis.c from a previous distribution has
been brought up to date and supports the new interface.
* disaaemble.c: define ARCH_ns32k and add case bfd_arch_ns32k.
* configure.in: add bfd_ns32k_arch target support.
* Makefile.in: add ns32k-dis.o to ALL_MACHINES.
Add ns32k-dis.c to CFILES. Add dependencies for ns32k-dis.o.
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opcodes to the first instruction with that opcode, to speed
disassembly of large files. From ralphc@pyramid.com (Ralph
Campbell).
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* mpw-config.in (target_arch): Compute from canonical target.
(m68k, mips, powerpc, sparc): Add architectures.
* mpw-make.in (disassemble.c.o): Add.
(ALL_CFLAGS): Remove special flags (-mc68020 -mc68881 -model far).
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* h8300-dis.c (bfd_h8_disassemble): Print 16bit rels correctly.
* sh-dis.c (print_insn_sh): Don't recur endlessly if delay
slot insn is in a delay slot.
* z8k-opc.h: (resflg): Fix patterns.
* h8500-opc.h Fix CR insn patterns.
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examined.
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(edelsohn@npac.syr.edu).
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immediate argument.
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removed, so don't initialize it. Set the PPC_OPERAND_SIGNED flag
instead. Add new operand SISIGNOPT.
(powerpc_opcodes): For lis, liu, addis, and cau use SISIGNOPT.
Based on patch from David Edelsohn (edelsohn@npac.syr.edu).
* ppc-dis.c (print_insn_powerpc): Check PPC_OPERAND_SIGNED rather
than signedp field.
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* mpw-xconfig.in (opcode/mips.h): Don't forward-include here.
(BFD_MACHINES): Set appropriately.
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* mpw-config.in (BFD_MACHINES): Set to a default value.
* mpw-make.in (BFD_MACHINES): Remove wired-in value.
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is a reserved word for dynix cc.
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rather than bfd/configure.in.
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* ppc-opc.c: Define POWER2 as short alias flag.
(powerpc_opcodes): Add POWER/2 opcodes lfq*, stfq*, fcir[z], and
fsqrt.
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* Makefile.in: Changed accordingly.
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(print_insn_m68k): If an instruction uses place 'i', it uses at
least four fixed bytes.
(print_insn_arg): Don't bump p by 2 for case 'I', place 'i'. For
extended float, convert to double using floatformat_to_double, not
ieee_extended_to_double, and fetch the data before converting it.
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davidj@ICSI.Berkeley.EDU (David Johnson).
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* mpw-make.in (CSEARCH): Add extra-include to search path.
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calling xmalloc.
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condition name index if this is for a negated condition.
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Floating point format for 'H' operand is backwards from normal
case (0 == double, 1 == single). For '4', '6', '7', '9', and '8'
operands (fmpyadd and fmpysub), handle bizarre register translation
correctly for single precision format.
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or 'I' operands if the next format specifier is 'M' (fcmp
condition completer).
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single number giving a bitmask for the MB and ME fields of an M
form instruction. Change NB to accept 32, and turn it into 0;
also turn 0 into 32 when disassembling. Seperated SH from NB.
(insert_mbe, extract_mbe): New functions.
(insert_nb, extract_nb): New functions.
(SC_MASK): Mask out SA and LK bits.
(powerpc_opcodes): Change "cal" to use RT, D, RA rather than RT,
RA, SI. Change "liu" and "cau" to use UI rather than SI. Mark
"bctr" and "bctrl" as accepted by POWER. Change "rlwimi",
"rlimi", "rlwimi.", "rlimi.", "rlwinm", "rlinm", "rlwinm.",
"rlinm.", "rlmi", "rlmi.", "rlwnm", "rlnm", "rlwnm.", "rlnm." to
use MBE rather than MB. Add "mfmq" and "mtmq" POWER instructions.
(powerpc_macros): Define table of macro definitions.
(powerpc_num_macros): Define.
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if PPC_OPERAND_NEXT is set.
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* mpw-xconfig.in (opcode/mips.h): Create using forward-include.
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* mpw-config.in (varargs.h): Don't create.
(sysdep.h): Create using forward-include.
* mpw-make.in (CSEARCH): Add include/mpw to search path.
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opcodes for POWER (RS/6000).
* ppc-dis.c: New file. PowerPC and Power (RS/6000) disassembler.
* Makefile.in (ALL_MACHINES): Add ppc-dis.o and ppc-opc.o.
(CFILES): Add ppc-dis.c.
(ppc-dis.o, ppc-opc.o): New targets.
* configure.in: Build ppc-dis.o and ppc-opc.o for bfd_rs6000_arch.
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No space before 'u', 'f', or 'N'.
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farther than we should.
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* mpw-make.in: Replace 8-bit chars with their names.
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* mpw-config.in: New file, MPW version of configure.in.
* mpw-make.in: New file, MPW version of Makefile.in.
Mon Jan 3 12:54:35 1994 Stan Shebs (shebs@andros.cygnus.com)
* mpw-xconfig.in: New file, mpw x mips configuration bits.
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FLOAT_MEMORY_FORMAT_CODE, FLOAT_BRANCH_FORMAT_CODE, correct
FLOAT_FORMAT_CODE to put out floating point register names.
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