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2017-03-27Implement ARC NPS-400 Ultra Ip and Miscellaneous instructions.Rinat Zelig3-350/+612
opcodes * arc-nps400-tbl.h: Add Ultra Ip and Miscellaneous instructions format. * arc-opc.c: Add defines. e.g. F_NJ, F_NM , F_NO_T, F_NPS_SR, F_NPS_M, F_NPS_CORE, F_NPS_ALL. (insert_nps_misc_imm_offset): New function. (extract_nps_misc imm_offset): New function. (arc_num_flag_operands): Add F_NJ, F_NM, F_NO_T. (arc_flag_special_cases): Add F_NJ, F_NM, F_NO_T. include * opcode/arc.h (insn_class_t): Add ULTRAIP and MISC class. gas * testsuite/gas/arc/nps400-12.s: New file. * testsuite/gas/arc/nps400-12.d: New file.
2017-03-21S/390: Remove vx2 facility flagAndreas Krebbel3-146/+147
This patch removes the vx2 facility flag. It will not be used by GCC and was a misnomer anyway. Committed to mainline and 2.28 branch. include/ChangeLog: 2017-03-21 Andreas Krebbel <krebbel@linux.vnet.ibm.com> * opcode/s390.h (S390_INSTR_FLAG_VX2): Remove. (S390_INSTR_FLAG_FACILITY_MASK): Adjust value. gas/ChangeLog: 2017-03-21 Andreas Krebbel <krebbel@linux.vnet.ibm.com> * config/tc-s390.c (s390_parse_cpu): Remove S390_INSTR_FLAG_VX2 from cpu_table. Remove vx2, and novx2 from cpu_flags. opcodes/ChangeLog: 2017-03-21 Andreas Krebbel <krebbel@linux.vnet.ibm.com> * s390-mkopc.c (main): Remove vx2 check. * s390-opc.txt: Remove vx2 instruction flags.
2017-03-21arc/nps400: Add cp16/cp32 instructions to opcodes libraryRinat Zelig3-3/+279
Instructions for loading or storing 16/32B data from one address type to another. gas/ChangeLog * testsuite/gas/arc/nps400-11.s: New file. * testsuite/gas/arc/nps400-11.d: New file. include/ChangeLog * opcode/arc.h (insn_class_t): Add DMA class. opcodes/ChangeLog * arc-nps400-tbl.h: Add cp32/cp16 instructions format. * arc-opc.c: Add F_NPS_NA, NPS_DMA_IMM_ENTRY, NPS_DMA_IMM_OFFSET. (insert_nps_imm_offset): New function. (extract_nps_imm_offset): New function. (insert_nps_imm_entry): New function. (extract_nps_imm_entry): New function.
2017-03-17E6500 spr mnemonicsAlan Modra2-8/+15
PR 21248 * ppc-opc.c (powerpc_opcodes): Enable mfivor32, mfivor33, mtivor32, and mtivor33 for e6500. Move mfibatl and mfibatu after those spr mnemonics they alias. Similarly for mtibatl, mtibatu.
2017-03-15RISC-V: Fix assembler for c.li, c.andi and c.addiwKito Cheng2-3/+9
- They can accept 0 in imm field 2017-03-14 Kito Cheng <kito.cheng@gmail.com> * riscv-opc.c (riscv_opcodes> <c.li>: Use the 'o' immediate encoding. <c.andi>: Likewise. <c.addiw> Likewise.
2017-03-15RISC-V: Fix assembler for c.addi, rd can be x0Kito Cheng2-1/+5
opcodes/ChangeLog: 2017-03-14 Kito Cheng <kito.cheng@gmail.com> * riscv-opc.c (riscv_opcodes) <c.addi>: Use match_opcode.
2017-03-14RISC-V: Fix [dis]assembly of srai/srliAndrew Waterman2-4/+11
These were simple copy/paste errors from the compressed left shift pattern, which can't have a 0-register.
2017-03-09X86: Add pseudo prefixes to control encodingH.J. Lu5-73/+183
Many x86 instructions have more than one encodings. Assembler picks the default one, usually the shortest one. Although the ".s", ".d8" and ".d32" suffixes can be used to swap register operands or specify displacement size, they aren't very flexible. This patch adds pseudo prefixes, {xxx}, to control instruction encoding. The available pseudo prefixes are {disp8}, {disp32}, {load}, {store}, {vex2}, {vex3} and {evex}. Pseudo prefixes are preferred over the ".s", ".d8" and ".d32" suffixes, which are deprecated. gas/ * config/tc-i386.c (_i386_insn): Add dir_encoding and vec_encoding. Remove swap_operand and need_vrex. (extra_symbol_chars): Add '}'. (md_begin): Mark '}' with LEX_BEGIN_NAME. Allow '}' in mnemonic. (build_vex_prefix): Don't use 2-byte VEX encoding with {vex3}. Check dir_encoding and load. (parse_insn): Check pseudo prefixes. Set dir_encoding. (VEX_check_operands): Likewise. (match_template): Check dir_encoding and load. (parse_real_register): Set vec_encoding instead of need_vrex. (parse_register): Likewise. * doc/c-i386.texi: Document {disp8}, {disp32}, {load}, {store}, {vex2}, {vex3} and {evex}. Remove ".s", ".d8" and ".d32" * testsuite/gas/i386/i386.exp: Run pseudos and x86-64-pseudos. * testsuite/gas/i386/pseudos.d: New file. * testsuite/gas/i386/pseudos.s: Likewise. * testsuite/gas/i386/x86-64-pseudos.d: Likewise. * testsuite/gas/i386/x86-64-pseudos.s: Likewise. opcodes/ * i386-gen.c (opcode_modifiers): Replace S with Load. * i386-opc.h (S): Removed. (Load): New. (i386_opcode_modifier): Replace s with load. * i386-opc.tbl: Add {disp8}, {disp32}, {swap}, {vex2}, {vex3} and {evex}. Replace S with Load. * i386-tbl.h: Regenerated.
2017-03-09Use CpuCET on rdsspqH.J. Lu3-2/+7
* i386-opc.tbl: Use CpuCET on rdsspq. * i386-tbl.h: Regenerated.
2017-03-08Update -maltivec and -mvsx options to only enable their oldest instructions.Peter Bergner2-2/+7
Currently, the -maltivec and -mvsx GAS options enable *all* of the altivec and vsx instructions respecitively that have ever been added. This is in constract to GCC's -maltivec and -mvsx options, which only enable the oldest (ie, first) set of altivec and vsx instructions. This patch changes GAS to mimic GCC's behaviour with respect to -maltivec and -mvsx and it solves a problem with trying to assemble the lxvx instruction which is different between POWER8 and POWER9. opcodes/ * ppc-dis.c (ppc_opts) <altivec>: Do not use PPC_OPCODE_ALTIVEC2; <vsx>: Do not use PPC_OPCODE_VSX3; gas/ * testsuite/gas/ppc/altivec2.d (as): Use the -mpower8 option. (objdump): Use the -Mpower8 option.
2017-03-08Add support for the new 'lnia' extended mnemonic.Peter Bergner2-0/+7
opcodes/ * ppc-opc.c (powerpc_opcodes) <lnia>: New extended mnemonic. gas/ * testsuite/gas/ppc/power9.d <lnia> New test. * testsuite/gas/ppc/power9.s: Likewise.
2017-03-06Add support for Intel CET instructionsH.J. Lu7-334/+681
Support Intel Control-flow Enforcement Technology (CET) instructions: https://software.intel.com/sites/default/files/managed/4d/2a/control-flow-enforcement-technology-preview.pdf gas/ * config/tc-i386.c (cpu_arch): Add .cet. * doc/c-i386.texi: Document cet. * testsuite/gas/i386/cet-intel.d: New file. * testsuite/gas/i386/cet.d: Likewise. * testsuite/gas/i386/cet.s: Likewise. * testsuite/gas/i386/x86-64-cet-intel.d: Likewise. * testsuite/gas/i386/x86-64-cet.d: Likewise. * testsuite/gas/i386/x86-64-cet.s: Likewise. * testsuite/gas/i386/i386.exp: Run Intel CET tests. opcodes/ * i386-dis.c (REG_0F1E_MOD_3): New enum. (MOD_0F1E_PREFIX_1): Likewise. (MOD_0F38F5_PREFIX_2): Likewise. (MOD_0F38F6_PREFIX_0): Likewise. (RM_0F1E_MOD_3_REG_7): Likewise. (PREFIX_MOD_0_0F01_REG_5): Likewise. (PREFIX_MOD_3_0F01_REG_5_RM_1): Likewise. (PREFIX_MOD_3_0F01_REG_5_RM_2): Likewise. (PREFIX_0F1E): Likewise. (PREFIX_MOD_0_0FAE_REG_5): Likewise. (PREFIX_0F38F5): Likewise. (dis386_twobyte): Use PREFIX_0F1E. (reg_table): Add REG_0F1E_MOD_3. (prefix_table): Add PREFIX_MOD_0_0F01_REG_5, PREFIX_MOD_3_0F01_REG_5_RM_1, PREFIX_MOD_3_0F01_REG_5_RM_2, PREFIX_0F1E, PREFIX_MOD_0_0FAE_REG_5 and PREFIX_0F38F5. Update PREFIX_0FAE_REG_6 and PREFIX_0F38F6. (three_byte_table): Use PREFIX_0F38F5. (mod_table): Use PREFIX_MOD_0_0F01_REG_5, PREFIX_MOD_0_0FAE_REG_5. Add MOD_0F1E_PREFIX_1, MOD_0F38F5_PREFIX_2, MOD_0F38F6_PREFIX_0. (rm_table): Add MOD_0F38F5_PREFIX_2, MOD_0F38F6_PREFIX_0, RM_0F1E_MOD_3_REG_7. Use PREFIX_MOD_3_0F01_REG_5_RM_1 and PREFIX_MOD_3_0F01_REG_5_RM_2. * i386-gen.c (cpu_flag_init): Add CPU_CET_FLAGS. (cpu_flags): Add CpuCET. * i386-opc.h (CpuCET): New enum. (CpuUnused): Commented out. (i386_cpu_flags): Add cpucet. * i386-opc.tbl: Add Intel CET instructions. * i386-init.h: Regenerated. * i386-tbl.h: Likewise.
2017-03-06Don't decode powerpc insns with invalid fieldsAlan Modra2-49/+168
Certain insns have restrictions on fields. For example, the insn mentioned in the PR, lqarx, must specify an even general purpose register as its destination and that register cannot appear in either of the base or index reg fields. This holds even when the RA0 field is 0 (meaning a zero rather than r0). PR 21124 * ppc-opc.c (extract_esync, extract_ls, extract_ral, extract_ram) (extract_raq, extract_ras, extract_rbx): New functions. (powerpc_operands): Use opposite corresponding insert function. (Q_MASK): Define. (powerpc_opcodes): Apply Q_MASK to all quad insns with even register restriction.
2017-02-28GDB: Add support for the new set/show disassembler-options commands.Peter Bergner6-218/+394
This commit adds support to GDB so that it can modify the disassembler-options value that is passed to the disassembler, similar to objdump's -M option. Currently, the only supported targets are ARM, PowerPC and S/390, but adding support for a new target(s) is not difficult. include/ * dis-asm.h (disasm_options_t): New typedef. (parse_arm_disassembler_option): Remove prototype. (set_arm_regname_option): Likewise. (get_arm_regnames): Likewise. (get_arm_regname_num_options): Likewise. (disassemble_init_s390): New prototype. (disassembler_options_powerpc): Likewise. (disassembler_options_arm): Likewise. (disassembler_options_s390): Likewise. (remove_whitespace_and_extra_commas): Likewise. (disassembler_options_cmp): Likewise. (next_disassembler_option): New inline function. (FOR_EACH_DISASSEMBLER_OPTION): New macro. opcodes/ * disassemble.c Include "safe-ctype.h". (disassemble_init_for_target): Handle s390 init. (remove_whitespace_and_extra_commas): New function. (disassembler_options_cmp): Likewise. * arm-dis.c: Include "libiberty.h". (NUM_ELEM): Delete. (regnames): Use long disassembler style names. Add force-thumb and no-force-thumb options. (NUM_ARM_REGNAMES): Rename from this... (NUM_ARM_OPTIONS): ...to this. Use ARRAY_SIZE. (get_arm_regname_num_options): Delete. (set_arm_regname_option): Likewise. (get_arm_regnames): Likewise. (parse_disassembler_options): Likewise. (parse_arm_disassembler_option): Rename from this... (parse_arm_disassembler_options): ...to this. Make static. Use new FOR_EACH_DISASSEMBLER_OPTION macro to scan over options. (print_insn): Use parse_arm_disassembler_options. (disassembler_options_arm): New function. (print_arm_disassembler_options): Handle updated regnames. * ppc-dis.c: Include "libiberty.h". (ppc_opts): Add "32" and "64" entries. (ppc_parse_cpu): Use ARRAY_SIZE and disassembler_options_cmp. (powerpc_init_dialect): Add break to switch statement. Use new FOR_EACH_DISASSEMBLER_OPTION macro. (disassembler_options_powerpc): New function. (print_ppc_disassembler_options): Use ARRAY_SIZE. Remove printing of "32" and "64". * s390-dis.c: Include "libiberty.h". (init_flag): Remove unneeded variable. (struct s390_options_t): New structure type. (options): New structure. (init_disasm): Rename from this... (disassemble_init_s390): ...to this. Add initializations for current_arch_mask and option_use_insn_len_bits_p. Remove init_flag. (print_insn_s390): Delete call to init_disasm. (disassembler_options_s390): New function. (print_s390_disassembler_options): Print using information from struct 'options'. * po/opcodes.pot: Regenerate. binutils/ * objdump.c (main): Use remove_whitespace_and_extra_commas. gdb/ * NEWS: Mention new set/show disassembler-options commands. * doc/gdb.texinfo: Document new set/show disassembler-options commands. * disasm.c: Include "arch-utils.h", "gdbcmd.h" and "safe-ctype.h". (prospective_options): New static variable. (gdb_disassembler::gdb_disassembler): Initialize m_di.disassembler_options. (gdb_buffered_insn_length_init_dis): Initilize di->disassembler_options. (get_disassembler_options): New function. (set_disassembler_options): Likewise. (set_disassembler_options_sfunc): Likewise. (show_disassembler_options_sfunc): Likewise. (disassembler_options_completer): Likewise. (_initialize_disasm): Likewise. * disasm.h (get_disassembler_options): New prototype. (set_disassembler_options): Likewise. * gdbarch.sh (gdbarch_disassembler_options): New variable. (gdbarch_verify_disassembler_options): Likewise. * gdbarch.c: Regenerate. * gdbarch.h: Likewise. * arm-tdep.c (num_disassembly_options): Delete. (set_disassembly_style): Likewise. (arm_disassembler_options): New static variable. (set_disassembly_style_sfunc): Convert short style name into long option name. Call set_disassembler_options. (show_disassembly_style_sfunc): New function. (arm_gdbarch_init): Call set_gdbarch_disassembler_options and set_gdbarch_verify_disassembler_options. (_initialize_arm_tdep): Delete regnames variable and update callers. (arm_disassembler_options): Initialize. (disasm_options): New variable. (num_disassembly_options): Rename from this... (num_disassembly_styles): ...to this. Compute by scanning through disasm_options. (valid_disassembly_styles): Initialize using disasm_options. Remove calls to parse_arm_disassembler_option, get_arm_regnames and set_arm_regname_option. Pass show_disassembly_style_sfunc to the "disassembler" setshow command. * rs6000-tdep.c (powerpc_disassembler_options): New static variable. (rs6000_gdbarch_init): Call set_gdbarch_disassembler_options and set_gdbarch_verify_disassembler_options. * s390-tdep.c (s390_disassembler_options): New static variable. (s390_gdbarch_init):all set_gdbarch_disassembler_options and set_gdbarch_verify_disassembler_options. gdb/testsuite/ * gdb.arch/powerpc-power.exp: Delete test. * gdb.arch/powerpc-power.s: Likewise. * gdb.disasm/disassembler-options.exp: New test. * gdb.arch/powerpc-altivec.exp: Likewise. * gdb.arch/powerpc-altivec.s: Likewise. * gdb.arch/powerpc-altivec2.exp: Likewise. * gdb.arch/powerpc-altivec2.s: Likewise. * gdb.arch/powerpc-altivec3.exp: Likewise. * gdb.arch/powerpc-altivec3.s: Likewise. * gdb.arch/powerpc-power7.exp: Likewise. * gdb.arch/powerpc-power7.s: Likewise. * gdb.arch/powerpc-power8.exp: Likewise. * gdb.arch/powerpc-power8.s: Likewise. * gdb.arch/powerpc-power9.exp: Likewise. * gdb.arch/powerpc-power9.s: Likewise. * gdb.arch/powerpc-vsx.exp: Likewise. * gdb.arch/powerpc-vsx.s: Likewise. * gdb.arch/powerpc-vsx2.exp: Likewise. * gdb.arch/powerpc-vsx2.s: Likewise. * gdb.arch/powerpc-vsx3.exp: Likewise. * gdb.arch/powerpc-vsx3.s: Likewise. * gdb.arch/arm-disassembler-options.exp: Likewise. * gdb.arch/powerpc-disassembler-options.exp: Likewise. * gdb.arch/s390-disassembler-options.exp: Likewise.
2017-02-28x86: fix handling of 64-bit operand size VPCMPESTR{I,M}Jan Beulich4-26/+170
Just like REX.W affects operand size of the implicit rAX/rDX inputs to PCMPESTR{I,M}, VEX.W does for VPCMPESTR{I,M}. Allow Q or L suffixes on the instructions. Similarly the disassembler needs to be adjusted to no longer require VEX.W to be zero for the instructions to be valid, and to emit proper suffixes. Note, however, that this doesn't address the problem of there being no way to control (at least) {,E}VEX.W for 32- or 16-bit code. Nor does it address the problem of the many WIG instructions not getting properly disassembled when VEX.W=1.
2017-02-24[AArch64] Additional SVE instructionsRichard Sandiford11-2089/+2815
This patch supports some additions to the SVE architecture prior to its public release. include/ * opcode/aarch64.h (AARCH64_OPND_SVE_ADDR_RI_S4x16) (AARCH64_OPND_SVE_IMM_ROT1, AARCH64_OPND_SVE_IMM_ROT2) (AARCH64_OPND_SVE_Zm3_INDEX, AARCH64_OPND_SVE_Zm3_22_INDEX) (AARCH64_OPND_SVE_Zm4_INDEX): New aarch64_opnds. opcodes/ * aarch64-tbl.h (OP_SVE_HMH, OP_SVE_VMU_HSD, OP_SVE_VMVU_HSD) (OP_SVE_VMVV_HSD, OP_SVE_VMVVU_HSD, OP_SVE_VM_HSD, OP_SVE_VUVV_HSD) (OP_SVE_VUV_HSD, OP_SVE_VU_HSD, OP_SVE_VVVU_H, OP_SVE_VVVU_S) (OP_SVE_VVVU_HSD, OP_SVE_VVV_D, OP_SVE_VVV_D_H, OP_SVE_VVV_H) (OP_SVE_VVV_HSD, OP_SVE_VVV_S, OP_SVE_VVV_S_B, OP_SVE_VVV_SD_BH) (OP_SVE_VV_BHSDQ, OP_SVE_VV_HSD, OP_SVE_VZVV_HSD, OP_SVE_VZV_HSD) (OP_SVE_V_HSD): New macros. (OP_SVE_VMU_SD, OP_SVE_VMVU_SD, OP_SVE_VM_SD, OP_SVE_VUVV_SD) (OP_SVE_VU_SD, OP_SVE_VVVU_SD, OP_SVE_VVV_SD, OP_SVE_VZVV_SD) (OP_SVE_VZV_SD, OP_SVE_V_SD): Delete. (aarch64_opcode_table): Add new SVE instructions. (aarch64_opcode_table): Use imm_rotate{1,2} instead of imm_rotate for rotation operands. Add new SVE operands. * aarch64-asm.h (ins_sve_addr_ri_s4): New inserter. (ins_sve_quad_index): Likewise. (ins_imm_rotate): Split into... (ins_imm_rotate1, ins_imm_rotate2): ...these two inserters. * aarch64-asm.c (aarch64_ins_imm_rotate): Split into... (aarch64_ins_imm_rotate1, aarch64_ins_imm_rotate2): ...these two functions. (aarch64_ins_sve_addr_ri_s4): New function. (aarch64_ins_sve_quad_index): Likewise. (do_misc_encoding): Handle "MOV Zn.Q, Qm". * aarch64-asm-2.c: Regenerate. * aarch64-dis.h (ext_sve_addr_ri_s4): New extractor. (ext_sve_quad_index): Likewise. (ext_imm_rotate): Split into... (ext_imm_rotate1, ext_imm_rotate2): ...these two extractors. * aarch64-dis.c (aarch64_ext_imm_rotate): Split into... (aarch64_ext_imm_rotate1, aarch64_ext_imm_rotate2): ...these two functions. (aarch64_ext_sve_addr_ri_s4): New function. (aarch64_ext_sve_quad_index): Likewise. (aarch64_ext_sve_index): Allow quad indices. (do_misc_decoding): Likewise. * aarch64-dis-2.c: Regenerate. * aarch64-opc.h (FLD_SVE_i3h, FLD_SVE_rot1, FLD_SVE_rot2): New aarch64_field_kinds. (OPD_F_OD_MASK): Widen by one bit. (OPD_F_NO_ZR): Bump accordingly. (get_operand_field_width): New function. * aarch64-opc.c (fields): Add new SVE fields. (operand_general_constraint_met_p): Handle new SVE operands. (aarch64_print_operand): Likewise. * aarch64-opc-2.c: Regenerate. gas/ * doc/c-aarch64.texi: Document that sve implies fp16, simd and compnum. * config/tc-aarch64.c (parse_vector_type_for_operand): Allow .q to be used with SVE registers. (parse_operands): Handle new SVE operands. (aarch64_features): Make "sve" require F16 rather than FP. Also require COMPNUM. * testsuite/gas/aarch64/sve.s: Add tests for new instructions. Include compnum tests. * testsuite/gas/aarch64/sve.d: Update accordingly. * testsuite/gas/aarch64/sve-invalid.s: Add tests for new instructions. * testsuite/gas/aarch64/sve-invalid.l: Update accordingly. Also update expected output for new FMOV and MOV alternatives.
2017-02-24[AArch64] Add a "compnum" featureRichard Sandiford2-6/+17
This patch adds a named "compnum" feature for the ARMv8.3-A FCADD and FCMLA extensions. include/ * opcode/aarch64.h (AARCH64_FEATURE_COMPNUM): New macro. (AARCH64_ARCH_V8_3): Include AARCH64_FEATURE_COMPNUM. opcodes/ * aarch64-tbl.h (aarch64_feature_simd_v8_3): Replace with... (aarch64_feature_compnum): ...this. (SIMD_V8_3): Replace with... (COMPNUM): ...this. (CNUM_INSN): New macro. (aarch64_opcode_table): Use it for the complex number instructions. gas/ * doc/c-aarch64.texi: Add a "compnum" entry. * config/tc-aarch64.c (aarch64_features): Likewise, * testsuite/gas/aarch64/advsimd-compnum.s: New test. * testsuite/gas/aarch64/advsimd-compnum.d: Likewise.
2017-02-24x86: also correctly support TEST opcode aliasesJan Beulich2-2/+6
Opcodes F6/1 and F7/1 are aliases of F6/0 and F7/0 in all modes. This complements commit 8b89fe14b5 ("X86: Decode opcode 0x82 as opcode 0x80 in 32-bit mode"), just that here 64-bit mode is also covered.
2017-02-23S/390: Add support for new cpu architecture - arch12.Andreas Krebbel3-79/+311
This adds support of new instructions to the S/390 specific parts. The important feature of the new instruction set is the support of single and extended precision floating point vector operations. Note: arch12 is NOT the official name of the new CPU. It just continues the series of archXX options supported as alternate names. The archXX terminology refers to the edition number of the Principle of Operations manual. The official CPU name will be added later while keeping support of the arch12 for backwards compatibility. No testsuite regressions. Committed to mainline. Bye, -Andreas- opcodes/ChangeLog: 2017-02-23 Andreas Krebbel <krebbel@linux.vnet.ibm.com> * s390-mkopc.c (main): Accept arch12 as cpu string and vx2 as facility. * s390-opc.c: Add new operand description macros, new instruction types, instruction masks, and new .insn instruction types. * s390-opc.txt: Add new arch12 instructions. include/ChangeLog: 2017-02-23 Andreas Krebbel <krebbel@linux.vnet.ibm.com> * opcode/s390.h (enum s390_opcode_cpu_val): New value S390_OPCODE_ARCH12. (S390_INSTR_FLAG_VX2): New macro definition. gas/ChangeLog: 2017-02-23 Andreas Krebbel <krebbel@linux.vnet.ibm.com> * config/tc-s390.c (s390_parse_cpu): New entry for arch12. * doc/as.texinfo: Document arch12 as cpu type. * doc/c-s390.texi: Likewise. * testsuite/gas/s390/s390.exp: Run arch12 specific tests. * testsuite/gas/s390/zarch-arch12.d: New test. * testsuite/gas/s390/zarch-arch12.s: New test. * testsuite/gas/s390/zarch-z13.d: Rename some mnemonics in the output patterns.
2017-02-23opcodes,gas: associate SPARC ASIs with an architecture level.Sheldon Lobo2-195/+196
With this change an architecture level bump due to assembly ASIs will show up as a warning/error depending on options passed to gas. Tested with sparc64-linux-gnu, and it does not introduce any regressions. gas/ChangeLog: Add support for associating SPARC ASIs with an architecture level. * config/tc-sparc.c (parse_sparc_asi): New encode SPARC ASIs. opcodes/ChangeLog: Add support for associating SPARC ASIs with an architecture level. * include/opcode/sparc.h (sparc_asi): New sparc_asi struct. * opcodes/sparc-opc.c (asi_table): Updated asi_table and encoding/ decoding of SPARC ASIs.
2017-02-23x86: drop stray VEX opcode 82 referencesJan Beulich2-4/+9
No such ModR/M-less opcode has ever existed in public documentation afaict, so I can't see why it had been added in the first place. Furthermore opcode 77 is special only with implied prefix 0F.
2017-02-22aarch64: actually copy first operand in convert_bfc_to_bfm()Jan Beulich2-2/+7
Commit 93562a343c ("[AArch64] PR target/20666, fix wrong encoding of new introduced BFC pseudo") changed the destination operand to 0, making the whole function invocation a no-op. We really want to copy operand 0 (a register) to operand 1 (an immediate before coming here), even if right now this likely is only a latent bug.
2017-02-15Add SFENCE.VMA instructionAndrew Waterman2-0/+8
include/ChangeLog: 2017-02-14 Andrew Waterman <andrew@sifive.com> * opcode/riscv-opc.h (MATCH_SFENCE_VMA): New define. (MASK_SFENCE_VMA): Likewise. (sfence_vma): Declare instruction. opcodes/ChangeLog: 2017-02-14 Andrew Waterman <andrew@sifive.com> * riscv-opc.c (riscv_opcodes): Add sfence.vma instruction and pseudoinstructions.
2017-02-15[AArch64] Add SVE system registersRichard Sandiford2-0/+21
This patch adds the SVE-specific system registers. opcodes/ * aarch64-opc.c (aarch64_sys_regs): Add SVE registers. (aarch64_sys_reg_supported_p): Handle them. gas/ * testsuite/gas/aarch64/sve-sysreg.s, testsuite/gas/aarch64/sve-sysreg.d, testsuite/gas/aarch64/sve-sysreg-invalid.d, testsuite/gas/aarch64/sve-sysreg-invalid.l: New tests.
2017-02-15[ARC] Fix assembler relaxation.Claudiu Zissulescu2-34/+75
Fix assembler relaxation step for add, ld, mov, mpy and sub instructions. Add tests to it. gas/ 2017-02-15 Claudiu Zissulescu <claziss@synopsys.com> * config/tc-arc.c (md_convert_frag): Remove @pcl relocation information from input expression. (assemble_insn): Make sure pcrel is correctly set. (arc_pcrel_adjust): Compensate for PCL rounding. * testsuite/gas/arc/relax-add01.d: New file. * testsuite/gas/arc/relax-add01.s: Likewise. * testsuite/gas/arc/relax-add02.d: Likewise. * testsuite/gas/arc/relax-add02.s: Likewise. * testsuite/gas/arc/relax-add03.d: Likewise. * testsuite/gas/arc/relax-add03.s: Likewise. * testsuite/gas/arc/relax-add04.d: Likewise. * testsuite/gas/arc/relax-add04.s: Likewise. * testsuite/gas/arc/relax-ld01.d: Likewise. * testsuite/gas/arc/relax-ld01.s: Likewise. * testsuite/gas/arc/relax-ld02.d: Likewise. * testsuite/gas/arc/relax-ld02.s: Likewise. * testsuite/gas/arc/relax-mov01.d: Likewise. * testsuite/gas/arc/relax-mov01.s: Likewise. * testsuite/gas/arc/relax-mov02.d: Likewise. * testsuite/gas/arc/relax-mov02.s: Likewise. * testsuite/gas/arc/relax-mpy01.d: Likewise. * testsuite/gas/arc/relax-mpy01.s: Likewise. * testsuite/gas/arc/relax-sub01.d: Likewise. * testsuite/gas/arc/relax-sub01.s: Likewise. * testsuite/gas/arc/relax-sub02.d: Likewise. * testsuite/gas/arc/relax-sub02.s: Likewise. * testsuite/gas/arc/relax-sub03.d: Likewise. * testsuite/gas/arc/relax-sub03.s: Likewise. * testsuite/gas/arc/relax-sub04.d: Likewise. * testsuite/gas/arc/relax-sub04.s: Likewise. opcodes/ 2017-02-15 Claudiu Zissulescu <claziss@synopsys.com> * arc-opc.c (UIMM6_20R): Define. (SIMM12_20): Use above. (SIMM12_20R): Define. (SIMM3_5_S): Use above. (UIMM7_A32_11R_S): Define. (UIMM7_9_S): Use above. (UIMM3_13R_S): Define. (SIMM11_A32_7_S): Use above. (SIMM9_8R): Define. (UIMM10_A32_8_S): Use above. (UIMM8_8R_S): Define. (W6): Use above. (arc_relax_opcodes): Use all above defines.
2017-02-15Distinguish some of the registers different on ARC700 and HS38 cpusVineet Gupta2-12/+41
opcodes * arc-regs.h: Distinguish some of the registers different on ARC700 and HS38 cpus. gas * testsuite/gas/arc/st.d: Update for 0xe having a name now
2017-02-14PowerPC register expression checksAlan Modra2-5/+11
This stops powerpc gas blithely accepting such nonsense as "addi %f4,%cr3,%r31". PR 21118 gas/ * NEWS: Mention powerpc register checks. * config/tc-ppc.c (struct pd_reg): Make value a short. Add flags. (pre_defined_registers): Delete fpscr and pmr entries. Set register type in flags. (cr_names): Set type in flags. (reg_name_search): Return pointer to struct pd_reg rather than value. (register_name): Adjust to suit. Set X_md from flags. (ppc_parse_name): Likewise. (ppc_optimize_expr): New function. (md_assemble): Verify expresion reg flags match operand. * config/tc-ppc.h (md_optimize_expr): Define. (ppc_optimize_expr): Declare. include/ * opcode/ppc.h (PPC_OPERAND_*): Reassign values, regs first. (PPC_OPERAND_SPR, PPC_OPERAND_GQR): Define. opcodes/ * ppc-opc.c (powerpc_operands): Flag SPR, SPRG and TBR entries with PPC_OPERAND_SPR. Flag PSQ and PSQM with PPC_OPERAND_GQR.
2017-02-11Fix use after free in cgen instruction lookupAlan Modra2-15/+20
* cgen-opc.c (cgen_lookup_insn): Delete buf and base_insn temps. Use insn_bytes_value and insn_int_value directly instead. Don't free allocated memory until function exit.
2017-02-10POWER9 add scv/rfscv instruction supportNicholas Piggin2-1/+7
opcodes/ * ppc-opc.c (powerpc_opcodes) <scv, rfscv>: New mnemonics. gas/ * testsuite/gas/ppc/power9.d <scv, rfscv>: New tests.
2017-02-06[ARC] Provide an interface to decode ARC instructions.Claudiu Zissulescu4-363/+609
gas/ 2017-02-06 Claudiu Zissulescu <claziss@synopsys.com> * config/tc-arc.c (parse_opcode_flags): Ignore implicit flags. include/ 2017-02-06 Claudiu Zissulescu <claziss@synopsys.com> Anton Kolesov <anton.kolesov@synopsys.com> * opcode/arc.h (insn_class_t): Add ENTER, LEAVE, POP, PUSH, BBIT0, BBIT1, BI, BIH, BRCC, EI, JLI, and SUB instruction classes. (flag_class_t): Add F_CLASS_WB, F_CLASS_ZZ, and F_CLASS_IMPLICIT flag classes. opcode/ 2017-02-06 Claudiu Zissulescu <claziss@synopsys.com> Anton Kolesov <anton.kolesov@synopsys.com> * arc-dis.c (arc_disassemble_info): New structure. (init_arc_disasm_info): New function. (find_format_from_table): Ignore implicit flags. (find_format): Update dissassembler private data. (print_flags): Likewise. (print_insn_arc): Likewise. (arc_opcode_to_insn_type): Consider the new added instruction classes. (arcAnalyzeInstr): Remove. (arc_insn_decode): New function. * arc-dis.h (arc_ldst_writeback_mode): New enum. (arc_ldst_data_size): Likewise. (arc_condition_code): Likewise. (arc_operand_kind): Likewise. (arc_insn_kind): New struct. (arc_instruction): Likewise. (arc_insn_decode): Declare function. (ARC_Debugger_OperandType): Deleted. (Flow): Likewise. (NullifyMode): Likewise. (allOperandsSize): Likewise. (arcDisState): Likewise. (arcAnalyzeInstr): Likewise. * arc-dis.c (arc_opcode_to_insn_type): Handle newly introduced insn_class_t enums. * arc-opc.c (F_SIZED): New define. (C_CC_EQ, C_CC_GE, C_CC_GT, C_CC_HI, C_CC_HS): Likewise. (C_CC_LE, C_CC_LO, C_CC_LS, C_CC_LT, C_CC_NE): Likewise. (C_CC_NE, C_AA_AB, C_AA_AW, C_ZZ_D, C_ZZ_H, C_ZZ_B): Likewise. (arc_flag_classes): Add F_CLASS_COND/F_CLASS_IMPLICIT flags. * opcodes/arc-tbl.h: Update instructions to include new F_CLASS_IMPLICIT flags. (bbit0, lp): Change class. (bbit1, bi, bih, br*, ei_s, jli_s): Likewsie
2017-02-03Fix compile time warning messages when compiling binutils with gcc 7.0.1.Nick Clifton3-5/+16
PR 21096 bfd * coffcode.h (coff_write_object_contents): Enlarge size of s_name_buf in order to avoid compile time warning about possible integer truncation. * elf32-nds32.c (nds32_elf_ex9_import_table): Mask off lower 32-bits of insn value before printing into buffer. opcodes * aarch64-opc.c (print_register_list): Ensure that the register list index will fir into the tb buffer. (print_register_offset_address): Likewise. * tic6x-dis.c (print_insn_tic6x): Increase size of func_unit_buf.
2017-01-27Fix disassembling of TIC6X parallel instructions where the previous fetch ↵Alexis Deruell2-2/+18
packet ended with a 32-bit insn. PR 21056 opcodes * tic6x-dis.c (print_insn_tic6x): Correct displaying of parallel instructions when the previous fetch packet ends with a 32-bit instruction. gas * testsuite/gas/tic6x/insns16-parallel.s: New test case. * testsuite/gas/tic6x/insns16-parallel.d: New test driver.
2017-01-25Clarify that include/opcode/ files are part of GNU opcodesDimitar Dimitrov2-2/+5
include/ChangeLog: 2017-01-25 Dimitar Dimitrov <dimitar@dinux.eu> * opcode/hppa.h: Clarify that file is part of GNU opcodes. * opcode/i860.h: Ditto. * opcode/nios2.h: Ditto. * opcode/nios2r1.h: Ditto. * opcode/nios2r2.h: Ditto. * opcode/pru.h: Ditto. opcodes/ChangeLog: 2017-01-25 Dimitar Dimitrov <dimitar@dinux.eu> * pru-opc.c: Remove vague reference to a future GDB port.
2017-01-20Updated Irish translation for the opcodes library.Nick Clifton2-458/+813
* po/ga.po: Updated Irish translation.
2017-01-18[ARM] Fix the decoding of indexed element VCMLA instructionSzabolcs Nagy2-4/+8
Bit 24 of the indexed element vcmla decode mask was incorrectly left unset. This could cause incorrect disassembly of some currently undefined instructions as vcmla. Rotatation immediates were not printed correctly in the disassembly (could print 170 and 280 instead of 180 and 270). opcodes/ * arm-dis.c (coprocessor_opcodes): Fix vcmla mask and disassembly. gas/ * testsuite/gas/arm/armv8_3-a-simd.s: Add vcmla tests. * testsuite/gas/arm/armv8_3-a-simd.d: Update.
2017-01-13Return -1 on memory error in print_insn_m68kYao Qi2-7/+19
m68k-dis.c:print_insn_m68k doesn't return -1 on memory error, but GDB expects it returning -1 on memory error. opcodes: 2017-01-13 Yao Qi <yao.qi@linaro.org> * m68k-dis.c (match_insn_m68k): Extend comments. Return -1 if FETCH_DATA returns 0. (m68k_scan_mask): Likewise. (print_insn_m68k): Update code to handle -1 return value.
2017-01-13Remove magic numbers in m68k-dis.c:print_insn_argYao Qi2-41/+72
When I inspect the return values of disassmblers, I happen to see various -1/-2/-3 magic numbers are used in m68k-dis.c. This patch is to replace them with enum. -1 and -2 is "clearly documented" in print_ins_arg's comments, but -3 isn't. In fact, -3 is returned when FETCH_DATA returns false, which means memory error (because fetch_data return 0 on memory error). So I name enum PRINT_INSN_ARG_MEMORY_ERROR for -3. This patch is a refactor patch, doesn't affect any functionality. opcodes: 2017-01-13 Yao Qi <yao.qi@linaro.org> * m68k-dis.c (enum print_insn_arg_error): New. (NEXTBYTE): Replace -3 with PRINT_INSN_ARG_MEMORY_ERROR. (NEXTULONG): Likewise. (NEXTSINGLE): Likewise. (NEXTDOUBLE): Likewise. (NEXTDOUBLE): Likewise. (NEXTPACKED): Likewise. (FETCH_ARG): Likewise. (FETCH_DATA): Update comments. (print_insn_arg): Update comments. Replace magic numbers with enum. (match_insn_m68k): Likewise.
2017-01-12Enable Intel AVX512_VPOPCNTDQ instructionsIgor Tsimbalist8-5344/+5432
gas/ 2017-01-12 Igor Tsimbalist <igor.v.tsimbalist@intel.com> * config/tc-i386.c (cpu_arch): Add .avx512_vpopcntdq. (cpu_noarch): Add noavx512_vpopcntdq. * doc/c-i386.texi: Document avx512_vpopcntdq, noavx512_vpopcntdq. * testsuite/gas/i386/i386.exp: Run AVX512_VPOPCNTDQ tests. * testsuite/gas/i386/avx512_vpopcntdqd-intel.d: New file. * testsuite/gas/i386/avx512_vpopcntdqd.d: Ditto. * testsuite/gas/i386/avx512_vpopcntdqd.s: Ditto. * testsuite/gas/i386/x86-64-avx512_vpopcntdqd-intel.d: Ditto. * testsuite/gas/i386/x86-64-avx512_vpopcntdqd.d: Ditto. * testsuite/gas/i386/x86-64-avx512_vpopcntdqd.s: Ditto. opcodes/ 2017-01-12 Igor Tsimbalist <igor.v.tsimbalist@intel.com> * i386-dis.c (enum): Add PREFIX_EVEX_0F3855, EVEX_W_0F3855_P_2. * i386-dis-evex.h (evex_table): Updated. * i386-gen.c (cpu_flag_init): Add CPU_AVX512_VPOPCNTDQ_FLAGS, CPU_ANY_AVX512_VPOPCNTDQ_FLAGS. Update CPU_ANY_AVX512F_FLAGS. (cpu_flags): Add CpuAVX512_VPOPCNTDQ. * i386-opc.h (enum): (AVX512_VPOPCNTDQ): New. (i386_cpu_flags): Add cpuavx512_vpopcntdq. * i386-opc.tbl: Add Intel AVX512_VPOPCNTDQ instructions. * i386-init.h: Regenerate. * i386-tbl.h: Ditto.
2017-01-12Return -1 on memory error in print_insn_msp430Yao Qi2-14/+99
Disassemblers in opcodes return -1 on memory error, but msp430 doesn't follow this convention. If I change GDB not to throw exception in disassemble_info.memory_error_func and rely on the return value of disassembler, I'll get the following output. (gdb) disassemble 0x0,+8 Dump of assembler code from 0x0 to 0x8: 0x00000000: .word 0xffff; ???? 0x00000002: .word 0xffff; ???? 0x00000004: .word 0xffff; ???? 0x00000006: .word 0xffff; ???? End of assembler dump. This patch teaches print_insn_msp430 and its callees to return -1 on memory error. opcodes: 2017-01-12 Yao Qi <yao.qi@linaro.org> * msp430-dis.c (msp430_singleoperand): Return -1 if msp430dis_opcode_signed returns false. (msp430_doubleoperand): Likewise. (msp430_branchinstr): Return -1 if msp430dis_opcode_unsigned returns false. (msp430x_calla_instr): Likewise. (print_insn_msp430): Likewise.
2017-01-05Prevent an abort in the FRV disassembler if the target bfd name is unknown.Nick Clifton2-3/+11
PR 20946 * frv-desc.c (lookup_mach_via_bfd_name): Return NULL if the name could not be matched. (frv_cgen_cpu_open): Allow for lookup_mach_via_bfd_name returning NULL.
2017-01-04[AArch64] Add separate feature flag for weaker release consistent load insnsSzabolcs Nagy2-3/+13
The weaker release consistency support of ARMv8.3-A is allowed as an optional extension for ARMv8.2-A, so separate command line option and feature flag is added: -march=armv8.2-a+rcpc turns LDAPR, LDAPRB, LDAPRH instructions on. opcodes/ * aarch64-tbl.h (RCPC, RCPC_INSN): Define. (aarch64_opcode_table): Use RCPC_INSN. include/ * opcode/aarch64.h (AARCH64_FEATURE_RCPC): Define. (AARCH64_ARCH_V8_3): Update. gas/ * config/tc-aarch64.c (aarch64_features): Add rcpc. * doc/c-aarch64.texi (AArch64 Extensions): Document rcpc. * testsuite/gas/aarch64/ldst-exclusive-armv8_3.d: Rename to ... * testsuite/gas/aarch64/ldst-rcpc.d: This. * testsuite/gas/aarch64/ldst-exclusive-armv8_3.s: Rename to ... * testsuite/gas/aarch64/ldst-rcpc.s: This. * testsuite/gas/aarch64/ldst-rcpc-armv8_2.d: New test.
2017-01-03Add support for the Q extension to the RISCV ISA.Kito Cheng2-0/+66
gas * config/tc-riscv.c (riscv_set_arch): Whitelist the "q" ISA extension. (riscv_after_parse_args): Set FLOAT_ABI_QUAD when the Q ISA is enabled and no other ABI is specified. include * opcode/riscv-opc.h: Add support for the "q" ISA extension. opcodes * riscv-opc.c (riscv-opcodes): Add support for the "q" ISA extension. * riscv-opcodes/all-opcodes: Likewise.
2017-01-03Add fall through comment.Dilyan Palauzov2-0/+5
* riscv-dis.c (print_insn_args): Add fall through comment.
2017-01-03Add new Serbian translation for the opcodes library.Nick Clifton4-2/+1515
* po/sr.po: New Serbian translation. * configure.ac (ALL_LINGUAS): Add sr. * configure: Regenerate.
2017-01-02Regen opcodes cgen filesAlan Modra27-0/+237
* epiphany-desc.h: Regenerate. * epiphany-opc.h: Regenerate. * fr30-desc.h: Regenerate. * fr30-opc.h: Regenerate. * frv-desc.h: Regenerate. * frv-opc.h: Regenerate. * ip2k-desc.h: Regenerate. * ip2k-opc.h: Regenerate. * iq2000-desc.h: Regenerate. * iq2000-opc.h: Regenerate. * lm32-desc.h: Regenerate. * lm32-opc.h: Regenerate. * m32c-desc.h: Regenerate. * m32c-opc.h: Regenerate. * m32r-desc.h: Regenerate. * m32r-opc.h: Regenerate. * mep-desc.h: Regenerate. * mep-opc.h: Regenerate. * mt-desc.h: Regenerate. * mt-opc.h: Regenerate. * or1k-desc.h: Regenerate. * or1k-opc.h: Regenerate. * xc16x-desc.h: Regenerate. * xc16x-opc.h: Regenerate. * xstormy16-desc.h: Regenerate. * xstormy16-opc.h: Regenerate.
2017-01-02Update year range in copyright notice of all files.Alan Modra275-278/+282
2017-01-02ChangeLog rotationAlan Modra2-2167/+2181
2016-12-31Fix riscv breakageAlan Modra2-0/+6
* disassemble.c (disassembler): Add break accidentally removed by PRU patch.
2016-12-31PRU Opcode PortDimitar Dimitrov9-1/+548
opcodes/ * Makefile.am: Add PRU source files. * configure.ac: Add PRU target. * disassemble.c (disassembler): Register PRU arch. * pru-dis.c: New file. * pru-opc.c: New file. * Makefile.in: Regenerate. * configure: Regenerate. Signed-off-by: Dimitar Dimitrov <dimitar@dinux.eu>
2016-12-29Return 'int' rather than 'unsigned short' in avrdis_opcodeYao Qi2-6/+23
avrdis_opcode return type is unsigned short, but -1 at the end of this function is returned. Additionally, print_insn_avr doesn't handle when -1 (in case of memory error) is returned from avrdis_opcode. This patch changes avrdis_opcode returning int indicating the error, and adds a new argument for instruction we got on success. The opcode is 16-bit, so I change local variables type to uint16_t, and include "bfd_stdint.h" as a result. On memory error, print_insn_avr returns -1, which is a common convention among most of print_insn_$ARCH functions. opcodes: 2016-12-29 Yao Qi <yao.qi@linaro.org> * avr-dis.c: Include "bfd_stdint.h" (avrdis_opcode): Change return type to int, add argument insn. Set *INSN on success. (print_insn_avr): Check return value of avrdis_opcode, and return -1 on error.
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