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2015-03-26powerpc: Add slbfee. instructionAnton Blanchard2-0/+6
2015-03-24Extend arm_feature_set struct to provide more bitsTerry Guo2-1294/+2543
2015-03-17Add znver1 processorGanesh Gopalasubramanian7-5283/+5339
2015-03-13MIPS: Fix constraint issues with the R6 beqc and bnec instructionsAndrew Bennett2-2/+7
2015-03-13Add support for MIPS R6 evp and dvp instructions.Andrew Bennett2-0/+8
2015-03-10S/390: Add more IBM z13 instructionsAndreas Krebbel3-0/+30
2015-03-10[AARCH64] Remove Load/Store register (unscaled immediate) alias.Jiong Wang5-490/+439
2015-03-03[ARM] Skip private symbol when doing objdumpJiong Wang2-2/+9
2015-02-25[SH] Fix clrs, sets, pref insn arch memberships.Oleg Endo2-3/+10
2015-02-23Adds a space between the operands of the RL78's MOV instruction for consisten...Vinay3-8/+14
2015-02-19Wrap a few opcodes headers in extern "C" for C++Pedro Alves2-0/+12
2015-02-11Fixes a problem with the RL78 disassembler which would incorrectly disassembl...Nick Clifton3-93/+93
2015-02-10opcodes/microblaze: Rename 'or', 'and', 'xor' to avoid C++ conflictPedro Alves3-4/+13
2015-01-29NDS32: Set branch instruction to relaxable.Kuan-Lin Chen1-1/+2
2015-01-28FT32 initial supportAlan Modra9-0/+292
2015-01-28NDS32/opcodes: Add new system registers.Kuan-Lin Chen2-2/+14
2015-01-16S/390: Add support for IBM z13.Andreas Krebbel5-530/+1203
2015-01-02Regenerate Makeile.in file for copyright updateAlan Modra1-1/+1
2015-01-02ChangeLog rotatation and copyright year updateAlan Modra265-1150/+1168
2014-12-27Limit moxie sto/ldo offsets to 16 bitsAnthony Green3-16/+22
2014-12-24Add mul.x and umul.x instructions to moxie portAnthony Green2-9/+14
2014-12-16Add in a JALRC alias and fix the NAL instruction.Matthew Fortune2-1/+7
2014-12-12Add zex instructions for moxie portAnthony Green2-2/+6
2014-12-06Add Visium support to opcodesEric Botcazou9-0/+886
2014-11-30Power4 should treat mftb as extended mfspr mnemonicAlan Modra2-6/+11
2014-11-28Remove broken nios2 assembler dwim support.Sandra Loosemore2-4/+9
2014-11-28Don't deprecate powerpc mftb insnAlan Modra2-7/+15
2014-11-24Update libtool.m4 from GCC trunkH.J. Lu2-2/+6
2014-11-17Add AVX512VBMI instructionsIlya Tocar8-5445/+5730
2014-11-17Add AVX512IFMA instructionsIlya Tocar8-5512/+5677
2014-11-17Add pcommit instructionIlya Tocar7-5262/+10575
2014-11-17Add clwb instructionIlya Tocar7-5260/+5310
2014-11-06Add mach parameter to nios2_find_opcode_hash.Sandra Loosemore2-3/+9
2014-11-03Import updated translations supplied by the Translation Project.Nick Clifton2-146/+372
2014-10-31MIPS: Add Octeon 3 supportNaveen H.S3-3/+29
2014-10-29Updated/new translations provided by the Translations Project.Nick Clifton2-270/+1059
2014-10-23Refactoring/cleanup of nios2 opcodes and assembler code.Sandra Loosemore3-451/+580
2014-10-21ppc: enable msgclr and msgsnd on Power8Jan Beulich2-2/+6
2014-10-17opcodes, elf: annotate instructions with HWCAP2_VIS3B.Jose E. Marchesi2-12/+13
2014-10-17opcodes: fix several misplaced hwcap entries.Jose E. Marchesi2-13/+18
2014-10-15Bump bfd version.Tristan Gingold2-10/+14
2014-10-09This is a series of patches that add support for the SPARC M7 cpu toJose E. Marchesi3-1441/+1507
2014-09-22Ignore MOD field for control/debug register moveH.J. Lu2-32/+19
2014-09-16NDS32/opcodes: Add audio ISA extension and modify the disassemble implemnt.Kuan-Lin Chen4-1842/+2327
2014-09-15Add support for MIPS R6.Andrew Bennett4-362/+786
2014-09-10Properly handle suffix for iret and sysretH.J. Lu2-21/+59
2014-09-03[PATCH/AArch64] Generic support for all system registers using mrs and msrJiong Wang3-101/+28
2014-09-03[PATCH/AArch64] Implement LSE featureJiong Wang10-223/+2033
2014-08-26MIPS: Make the CODE10 operand code consistent between ISAsMaciej W. Rozycki2-5/+11
2014-08-22ARM/opcodes: Fix negative hexadecimal offset disassemblyMaciej W. Rozycki2-0/+8
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