Age | Commit message (Collapse) | Author | Files | Lines |
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* ia64-opc-a.c (ia64_opcodes_a): Delete mov immediate pseudo for adds.
* ia64-asmtab.c: Regnerate.
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* ppc-opc.c (insert_fxm): Handle mfocrf and mtocrf.
(extract_fxm): Don't test dialect.
(XFXFXM_MASK): Include the power4 bit.
(XFXM): Add p4 param.
(powerpc_opcodes): Add mfocrf and mtocrf. Adjust mtcr.
gas/testsuite/
* gas/ppc/power4.d: Update.
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* disassemble.c (disassembler): Handle bfd_mach_h8300sxn.
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(powerpc_opcodes): Allow BH field on bclr, bclrl, bcctr, bcctrl.
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* i386.h (i386_optab): Remove fildd, fistpd and fisttpd.
opcodes/
* i386-dis.c (x_mode): Comment.
(two_source_ops): File scope.
(float_mem): Correct fisttpll and fistpll.
(float_mem_mode): New table.
(dofloat): Use it.
(OP_E): Correct intel mode PTR output.
(ptr_reg): Use open_char and close_char.
(PNI_Fixup): Handle possible suffix on sidt. Use op1out etc. for
operands. Set two_source_ops.
gas/testsuite/
* gas/i386/prescott.s: Remove fisttpd and fisttpq.
* gas/i386/prescott.d: Update.
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instead of _raw_size.
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* ia64-gen.c (in_iclass): Handle more postinc st
and ld variants.
* ia64-asmtab.c: Rebuilt.
gas/testsuite/
* gas/ia64/dv-raw-err.s: Add some new postinc tests.
* gas/ia64/dv-raw-err.l: Updated.
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lrv, lrvh, strv, ml, dl, alc, slb rll and mvclu are available
in the esa mode as well.
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bfd:
* Makefile.am: Regenerate dependencies.
* Makefile.in: Regenerate.
* archures.c: Add bfd_mach_sh3_nommu .
* bfd-in2.h: Regenerate.
* cpu-sh.c: Add sh3-nommu architecture.
(bfd_to_arch_table): Create new table.
(sh_get_arch_from_bfd_mach): Create new function.
(sh_get_arch_up_from_bfd_mach): Create new function.
(sh_merge_bfd_arch): Create new function.
* elf32-sh.c (sh_ef_bfd_table): Add table.
(sh_elf_check_relocs): Replace switch statement with
use of sh_ef_bfd_table .
(sh_elf_get_flags_from_mach): Add new function.
(sh_find_elf_flags): Likewise.
(sh_elf_copy_private_data): Replace most of non-elf contents
with a call to sh_merge_bfd_arch() .
gas:
* Makefile.am: Regenerate dependecies.
* Makefile.in: Regenerate.
* config/tc-sh.c (valid_arch): Make unsigned.
(preset_target_arch): Likewise.
(md_begin): Use new architecture flags system.
(get_specific): Likewise.
(assemble_ppi): Likewise.
(md_assemble): Likewise. Also fix error check for bad opcodes.
(md_parse_option): Likewise. Also generate -isa values according
to the table in bfd/cpu-sh.c instead of just constants. Also
allow <arch>-up ISA variants.
(sh_elf_final_processing): Replace if-else chain with a call to
sh_find_elf_flags().
* testsuite/gas/sh/arch: New directory.
* testsuite/gas/sh/arch/arch.exp: New test script.
* testsuite/gas/sh/arch/arch_expected.txt: New file.
* testsuite/gas/sh/arch/sh.s: New file.
* testsuite/gas/sh/arch/sh2.s: New file.
* testsuite/gas/sh/arch/sh-dsp.s: New file.
* testsuite/gas/sh/arch/sh2e.s: New file.
* testsuite/gas/sh/arch/sh3-nommu.s: New file.
* testsuite/gas/sh/arch/sh3.s: New file.
* testsuite/gas/sh/arch/sh3-dsp.s: New file.
* testsuite/gas/sh/arch/sh3e.s: New file.
* testsuite/gas/sh/arch/sh4-nommu-nofpu.s: New file.
* testsuite/gas/sh/arch/sh4-nofpu.s: New file.
* testsuite/gas/sh/arch/sh4.s: New file.
* testsuite/gas/sh/arch/sh4a-nofpu.s: New file.
* testsuite/gas/sh/arch/sh4al-dsp.s: New file.
* testsuite/gas/sh/arch/sh4a.s: New file.
include/elf:
* sh.h (EF_SH_HAS_DSP): Remove.
(EF_SH_HAS_FP): Remove.
(EF_SH_MERGE_MACH): Remove.
(EF_SH4_NOFPU): Convert to decimal.
(EF_SH4A_NOFPU): Likewise.
(EF_SH4_NOMMU_NOFPU): Likewise.
(EF_SH3_NOMMU): Add new macro.
(EF_SH_BFD_TABLE): Likewise.
(sh_find_elf_flags): Add prototype.
(sh_elf_get_flags_from_mach): Likewise.
opcodes:
* sh-dis.c (target_arch): Make unsigned.
(print_insn_sh): Replace (most of) switch with a call to
sh_get_arch_from_bfd_mach(). Also use new architecture flags system.
* sh-opc.h: Redefine architecture flags values.
Add sh3-nommu architecture.
Reorganise <arch>_up macros so they make more visual sense.
(SH_MERGE_ARCH_SET): Define new macro.
(SH_VALID_BASE_ARCH_SET): Likewise.
(SH_VALID_MMU_ARCH_SET): Likewise.
(SH_VALID_CO_ARCH_SET): Likewise.
(SH_VALID_ARCH_SET): Likewise.
(SH_MERGE_ARCH_SET_VALID): Likewise.
(SH_ARCH_SET_HAS_FPU): Likewise.
(SH_ARCH_SET_HAS_DSP): Likewise.
(SH_ARCH_UNKNOWN_ARCH): Likewise.
(sh_get_arch_from_bfd_mach): Add prototype.
(sh_get_arch_up_from_bfd_mach): Likewise.
(sh_get_bfd_mach_from_arch_set): Likewise.
(sh_merge_bfd_arc): Likewise.
ld:
* testsuite/ld-sh/arch/arch.exp: New test script.
* testsuite/ld-sh/arch/arch_expected.txt: New file.
* testsuite/ld-sh/arch/sh.s: New file.
* testsuite/ld-sh/arch/sh2.s: New file.
* testsuite/ld-sh/arch/sh-dsp.s: New file.
* testsuite/ld-sh/arch/sh2e.s: New file.
* testsuite/ld-sh/arch/sh3-nommu.s: New file.
* testsuite/ld-sh/arch/sh3.s: New file.
* testsuite/ld-sh/arch/sh3-dsp.s: New file.
* testsuite/ld-sh/arch/sh3e.s: New file.
* testsuite/ld-sh/arch/sh4-nommu-nofpu.s: New file.
* testsuite/ld-sh/arch/sh4-nofpu.s: New file.
* testsuite/ld-sh/arch/sh4.s: New file.
* testsuite/ld-sh/arch/sh4a-nofpu.s: New file.
* testsuite/ld-sh/arch/sh4al-dsp.s: New file.
* testsuite/ld-sh/arch/sh4a.s: New file.
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well as when -mpower4.
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* ppc-opc.c (XCMPL): Renmame to XOPL. Update users.
(powerpc_opcodes): Add "dbczl" instruction for PPC970.
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[testsuite]
* gas/ppc/power4.s: Add dcbz and dcbzl test cases.
* gas/ppc/power4.d: Update accordingly.
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* elf32-sh.c (sh_elf_plt_sym_val): New function.
(elf_backend_plt_sym_val): Define.
opcodes/
* sh-dis.c (print_insn_sh): Print the value in constant pool
as a symbol if it looks like a symbol.
gas/testsuite/
* gas/sh/pcrel2.d: Update.
* gas/sh/tlsd.d: Update.
* gas/sh/tlsnopic.d: Update.
* gas/sh/tlspic.d: Update.
ld/testsuite/
* ld-sh/tlsbin-1.d: Update
* ld-sh/tlspic-1.d: Update.
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variants.
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(fmovicc, fmovfcc, fmovcc): Remove fpsize argument, change opcode to
suffix. Use fmov*x macros, create all 3 fpsize variants in one
macro. Adjust all users.
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used.
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* config.in: Regenerate.
* configure: Regenerate.
* po/POTFILES.in: Regenerate.
* po/opcodes.pot: Regenerate.
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* ppc-dis.c (print_insn_powerpc): Don't print tabs. Handle
PPC_OPERANDS_GPR_0.
* ppc-opc.c (RA0): Define.
(RAQ, RAL, RAM, RAS, RSQ, RTQ, RSO): Use PPC_OPERAND_GPR_0.
(RAOPT): Rename from RAO. Update all uses.
(powerpc_opcodes): Use RA0 as appropriate. Add "lsdx", "lsdi",
"stsdx", "stsdi", "lmd" and "stmd" insns.
include/opcode/
* ppc.h (PPC_OPERAND_GPR_0): Define. Bump other operand defines.
gas/testsuite/
Update gas/ppc/.
ld/testsuite/
Update ld-powerpc/.
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* i386-dis.c (GRPPLOCK): Delete.
(grps): Detele GRPPLOCK entry.
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(M, Mp): Use OP_M.
(None, PADLOCK_SPECIAL, PADLOCK_0): Delete.
(GRPPADLCK): Define.
(dis386): Use NOP_Fixup on "nop".
(dis386_twobyte): Use GRPPADLCK on opcode 0xa7.
(twobyte_has_modrm): Set for 0xa7.
(padlock_table): Delete. Move to..
(grps): ..here, using OP_0f07. Use OP_Ofae on lfence, mfence
and clflush.
(print_insn): Revert PADLOCK_SPECIAL code.
(OP_E): Delete sfence, lfence, mfence checks.
* gas/i386/katmai.d: Revert last change.
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(INVLPG_Fixup): New function.
(PNI_Fixup): Remove ATTRIBUTE_UNUSED from sizeflag.
* opcode/i386.h (i386_optab): Remove CpuNo64 from sysenter and
sysexit.
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* gas/config/tc-i386.c (output_insn): Handle PadLock instructions.
* gas/config/tc-i386.h (CpuPadLock): New define.
(CpuUnknownFlags): Added CpuPadLock.
* include/opcode/i386.h (i386_optab): Added xstore/xcrypt insns.
* opcodes/i386-dis.c (PADLOCK_SPECIAL, PADLOCK_0): New defines.
(dis386_twobyte): Opcode 0xa7 is PADLOCK_0.
(padlock_table): New struct with PadLock instructions.
(print_insn): Handle PADLOCK_SPECIAL.
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* i386-dis.c (grps): Use clflush by default for 0x0fae/7.
(OP_E): Twiddle clflush to sfence here.
gas/testsuite/
* gas/i386/katmai.d: Adjust for clflush change.
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opcodes:
* sh-dis.c (print_insn_sh): Don't disassemble fp instructions in
nofpu mode. Add BFD type bfd_mach_sh4_nommu_nofpu.
* sh-opc.h: Add sh4_nommu_nofpu architecture and adjust instructions
accordingly.
bfd:
* archures.c: Add bfd_mach_sh4_nommu_nofpu.
* cpu-sh.c: Ditto.
* elf32-sh.c: Ditto.
* bfd-in2.h: Regenerate.
include/elf:
* sh.h: Add EF_SH4_NOMMU_NOFPU.
gas:
* config/tc-sh.c (md_parse_option): Add -isa=sh4-nofpu and
-isa=sh4-nommu-nofpu options. Adjust help messages accordingly.
(sh_elf_final_processing): Output BFD type sh4_nofpu if that is
the most general type or the user specifically requested it.
(md_assemble): Add a new error message for when an instruction
is understood, but is not allowed due to an -isa option.
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* frv.cpu (nsdiv, nudiv, nsdivi, nudivi): Remove fr400 profiling unit.
(scutss): Change unit to I0.
(calll, callil, ccalll): Add missing FR550-MAJOR and profile unit.
(mqsaths): Fix FR400-MAJOR categorization.
(media-quad-multiply-cross-acc, media-quad-cross-multiply-cross-acc)
(media-quad-cross-multiply-acc): Change unit from MDUALACC to FMALL.
* frv.opc (fr400_check_insn_major_constraints): Check for (M-2,M-1)
combinations.
opcodes/
* frv-desc.c, frv-opc.c: Regenerate.
sim/frv/
* cache.c (frv_cache_init): Change fr400 cache statistics to match
the fr405.
(non_cache_access): Add missing breaks.
* interrupts.c (set_exception_status_registers): Always set EAR15
for data_access_errors.
* memory.c (fr400_check_write_address): Remove redundant alignment
check.
* model.c: Regenerate.
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* frv.cpu (r-store, r-store-dual, r-store-quad): Delete.
(rstb, rsth, rst, rstd, rstq): Delete.
(rstbf, rsthf, rstf, rstdf, rstqf): Delete.
gas/testsuite/
* gas/frv/allinsn.s (rstb, rsth, rst, rstd, rstq): Replace with nops.
(rstbf, rsthf, rstf, rstdf, rstqf): Likewise.
* gas/frv/allinsn.d: Update accordingly.
opcodes/
* frv-desc.c, frv-opc.c, frv-opc.h: Regenerate.
sim/frv/
* decode.c, decode.h, model.c, sem.c: Regenerate.
sim/testsuite/
* sim/frv/{rstb,rsth,rst,rstd,rstq}.cgs: Delete.
* sim/frv/{rstbf,rsthf,rstf,rstdf,rstqf}.cgs: Delete.
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* sh-opc.h: Move fsca and fsrra instructions from sh4a to sh4.
Also correct mistake in the comment.
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gas:
* tc-sh.c (build_Mytes): Add REG_N_D and REG_N_B01
nibble types to assembler.
opcodes:
* sh-dis.c (print_insn_sh): Add REG_N_D nibble type to
ensure that double registers have even numbers.
Add REG_N_B01 for nn01 (binary 01) nibble to ensure
that reserved instruction 0xfffd does not decode the same
as 0xfdfd (ftrv).
* sh-opc.h: Add REG_N_D nibble type and use it whereever
REG_N refers to a double register.
Add REG_N_B01 nibble type and use it instead of REG_NM
in ftrv.
Adjust the bit patterns in a few comments.
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* ppc-opc.c (powerpc_opcodes): Move mfmcsrr0 before mfdc_dat.
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* ppc-opc.c (powerpc_opcodes): Add m*ivor35.
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mtivor32, mtivor33, mtivor34.
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* ppc-opc.c: Add mfmcar.
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* sh-opc.h (sh_table): "fsrra", not "fssra".
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