Age | Commit message (Collapse) | Author | Files | Lines |
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2005-05-25 Jan Beulich <jbeulich@novell.com>
* gas/i386/intelok.d: Account for 32-bit displacements being shown
in hex.
opcodes/
2005-05-25 Jan Beulich <jbeulich@novell.com>
* i386-dis.c (OP_E): In Intel mode, display 32-bit displacements in
hex (but retain it being displayed as signed). Remove redundant
checks. Add handling of displacements for 16-bit addressing in Intel
mode.
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2005-05-25 Jan Beulich <jbeulich@novell.com>
* i386-dis.c (prefix_name): Remove pointless mode_64bit check.
(OP_E): Remove redundant REX_EXTZ handling. Remove pointless
masking of 'rm' in 16-bit memory address handling.
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(print_ppc_disassembler_options): Document it.
* ppc-opc.c (SCV_LEV): Define.
(LEV): Allow optional operand.
(POWER5): Define.
(powerpc_opcodes): Extend "sc". Adjust "svc" and "svcl". Add
"hrfid", "popcntb", "fsqrtes", "fsqrtes.", "fre" and "fre.".
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* Makefile.in: Regenerate.
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* arm.h: Import complete list of official relocation names
and numbers from AAELF. Define FAKE_RELOCs for old names.
Remove a few old names no longer used anywhere.
bfd:
* elf32-arm.c: Wherever possible, use official reloc names
from AAELF.
(elf32_arm_howto_table, elf32_arm_tls_gd32_howto)
(elf32_arm_tls_ldo32_howto, elf32_arm_tls_ldm32_howto)
(elf32_arm_tls_le32_howto, elf32_arm_tls_ie32_howto)
(elf32_arm_vtinherit_howto, elf32_arm_vtentry_howto)
(elf32_arm_pc11_howto, elf32_arm_thm_pc9_howto, elf32_arm_got_prel)
(elf32_arm_r_howto): Replace with elf32_arm_howto_table_1,
elf32_arm_howto_table_2, and elf32_arm_howto_table_3.
Add many new relocations from AAELF.
(elf32_arm_howto_from_type): Update to match.
(elf32_arm_reloc_map): Add entries for R_ARM_THM_JUMP24,
R_ARM_THM_JUMP11, R_ARM_THM_JUMP19, R_ARM_THM_JUMP8,
R_ARM_THM_JUMP6, R_ARM_GNU_VTINHERIT, and R_ARM_GNU_VTENTRY.
(elf32_arm_reloc_type_lookup): Use elf32_arm_howto_from_type.
(elf32_arm_final_link_relocate): Add support for
R_ARM_THM_JUMP24, R_ARM_THM_JUMP19, R_ARM_THM_JUMP6. Remove
case entries redundant with default.
* reloc.c: Reorganize ARM relocations. Add Thumb
assembler-internal relocations BFD_RELOC_ARM_T32_OFFSET_U8,
BFD_RELOC_ARM_T32_OFFSET_IMM, BFD_RELOC_ARM_T32_IMMEDIATE.
Add visible relocations BFD_RELOC_THUMB_PCREL_BRANCH7,
BFD_RELOC_THUMB_BRANCH20, BFD_RELOC_THUMB_BRANCH25.
Delete unused relocations BFD_RELOC_ARM_GOT12, BFD_RELOC_ARM_COPY.
* bfd-in2.h, libbfd.h: Regenerate.
opcodes:
* arm-dis.c (thumb_opcodes): Add disassembly for V6T2 16-bit
instructions. Adjust disassembly of some opcodes to match
unified syntax.
(thumb32_opcodes): New table.
(print_insn_thumb): Rename print_insn_thumb16; don't handle
two-halfword branches here.
(print_insn_thumb32): New function.
(print_insn): Choose among print_insn_arm, print_insn_thumb16,
and print_insn_thumb32. Be consistent about order of
halfwords when printing 32-bit instructions.
gas:
* hash.c (hash_lookup): Add len parameter. All callers changed.
(hash_find_n): New interface.
* hash.h: Prototype hash_find_n.
* sb.c: Include as.h.
(scrub_from_sb, sb_to_scrub, scrub_position): New statics.
(sb_scrub_and_add_sb): New interface.
* sb.h: Prototype sb_scrub_and_add_sb.
* input-scrub.c (input_scrub_include_sb): Use sb_scrub_and_add_sb.
* config/tc-arm.h (TC_FORCE_RELOCATION_LOCAL): Remove
reference to BFD_RELOC_ARM_GOT12 which is never generated.
* config/tc-arm.c: Rewrite, adding Thumb-2 support.
gas/testsuite:
* gas/arm/arm.exp: Convert all existing "gas_test" tests to
"run_dump_test" tests. Run more tests unconditionally. Run new tests.
* gas/arm/arch4t.s, gas/arm/arch6zk.s, gas/arm/arm3.s, gas/arm/arm6.s
* gas/arm/arm7dm.s, gas/arm/bignum1.s, gas/arm/float.s
* gas/arm/immed.s, gas/arm/iwmmxt.s, gas/arm/offset.s, gas/arm/thumb.s:
Adjust to work as a dump test.
* gas/arm/arch4t.d, gas/arm/arch6zk.d, gas/arm/arm3.d, gas/arm/arm6.d
* gas/arm/arm7dm.d, gas/arm/bignum1.d, gas/arm/float.d
* gas/arm/immed.d, gas/arm/iwmmxt.d, gas/arm/offset.d, gas/arm/thumb.d:
New files.
* gas/arm/armv1-bad.l, gas/arm/armv1-bad.s: Remove tests for
diagnostics that don't happen in the first pass anymore.
* gas/arm/iwmmxt-bad.l, gas/arm/r15-bad.l, gas/arm/req.l
* gas/arm/vfp-bad.l:
Update expected diagnostics.
* gas/arm/pic.d: Update expected reloc name.
* gas/arm/thumbv6.d: CPY no longer appears in disassembly.
* gas/arm/r15-bad.s: Avoid two-argument mul.
* gas/arm/req.s: Adjust comments.
* gas/arm/maverick.d, gas/arm/maverick.s: Avoid inappropriate
use of PC.
* gas/arm/macro-1.d, gas/arm/macro1.s
* gas/arm/t16-bad.l, gas/arm/t16-bad.s
* gas/arm/tcompat.d, gas/arm/tcompat.s
* gas/arm/tcompat2.d, gas/arm/tcompat2.s
* gas/arm/thumb32.d, gas/arm/thumb32.s
New test pair.
ld/testsuite:
* ld-arm/mixed-app.d: Adjust expected disassembly a little.
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2005-05-07 H.J. Lu <hongjiu.lu@intel.com>
PR 843
* gas/i386/i386.exp: Add x86-64-branch.
* gas/i386/x86-64-branch.d: New.
* gas/i386/x86-64-branch.s: New.
opcodes/
2005-05-07 H.J. Lu <hongjiu.lu@intel.com>
PR 843
* i386-dis.c (branch_v_mode): New.
(indirEv): Use branch_v_mode instead of v_mode.
(OP_E): Handle branch_v_mode.
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* d10v-dis.c (dis_2_short): Support 64bit host.
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* ia64-opc.c: Include sysdep.h before libiberty.h.
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* configure: Regenerate.
* po/vi.po: New.
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* configure: Regenerate.
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(powerpc_opcodes <tlbsx, tlbsx., tlbre>): Combine PPC403 and BOOKE
entries to suit PPC440.
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* config/tc-i386.c (md_begin): Allow hyphens in mnemonics.
include/opcode/ChangeLog:
* i386.h: Insert hyphens into selected VIA PadLock extensions.
Add xcrypt-ctr. Provide aliases without hyphens.
opcodes/ChangeLog:
* i386-dis.c: Insert hyphens into selected VIA PadLock extensions.
Add xcrypt-ctr.
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* configure.in (ALL_LINGUAS): Add fi.
* configure: Regenerate.
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* Makefile.am (NO_WERROR): Define.
* warning.m4: New file
* acinclude.m4: Include warning.m4.
* configure.in: Invoke AM_BINUTILS_WARNINGS.
* Makefile.in: Regenerate.
* configure: Regenerate.
bfd/doc/
* Makefile.in: Regenerate.
binutils/
* Makefile.am (NO_WERROR): Define. Use instead of -Wno-error.
* configure.in: Include ../bfd/warning.m4 contents.
* Makefile.in: Regenerate.
* configure: Regenerate.
* doc/Makefile.in: Regenerate.
gas/
* Makefile.am (NO_WERROR): Define. Use instead of -Wno-error.
* acinclude.m4: Include ../bfd/warning.m4.
* configure.in: Invoke AM_BINUTILS_WARNINGS.
* Makefile.in: Regenerate.
* configure: Regenerate.
* doc/Makefile.in: Regenerate.
gprof/
* Makefile.am (NO_WERROR): Define.
* acinclude.m4: Include ../bfd/warning.m4.
* configure.in: Invoke AM_BINUTILS_WARNINGS.
* Makefile.in: Regenerate.
* aclocal.m4: Regenerate.
* configure: Regenerate.
ld/
* Makefile.am (NO_WERROR): Define. Use instead of -Wno-error.
* configure.in: Include ../bfd/warning.m4 contents.
* Makefile.in: Regenerate.
* configure: Regenerate.
opcodes/
* Makefile.am (NO_WERROR): Define.
* configure.in: Invoke AM_BINUTILS_WARNINGS.
* Makefile.in: Regenerate.
* aclocal.m4: Regenerate.
* configure: Regenerate.
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2005-04-01 Jan Beulich <jbeulich@novell.com>
* i386-dis.c (PNI_Fixup): Neither mwait nor monitor have any
visible operands in Intel mode. The first operand of monitor is
%rax in 64-bit mode.
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2005-04-01 Jan Beulich <jbeulich@novell.com>
* i386.h (i386_optab): Add rdtscp.
opcodes/
2005-04-01 Jan Beulich <jbeulich@novell.com>
* i386-dis.c (INVLPG_Fixup): Decode rdtscp; change code to allow for
easier future additions.
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* configure: Regenerate.
* config.in: Ditto.
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2005-03-29 H.J. Lu <hongjiu.lu@intel.com>
* gas/i386/i386.exp: Run segment and inval-seg for i386. Run
x86-64-segment and x86-64-inval-seg for x86-64.
* gas/i386/intel.d: Expect movw for moving between memory and
segment register.
* gas/i386/naked.d: Likewise.
* gas/i386/opcode.d: Likewise.
* gas/i386/x86-64-opcode.d: Likewise.
* gas/i386/opcode.s: Use movw for moving between memory and
segment register.
* gas/i386/x86-64-opcode.s: Likewise.
* : Likewise.
* gas/i386/inval-seg.l: New.
* gas/i386/inval-seg.s: New.
* gas/i386/segment.l: New.
* gas/i386/segment.s: New.
* gas/i386/x86-64-inval-seg.l: New.
* gas/i386/x86-64-inval-seg.s: New.
* gas/i386/x86-64-segment.l: New.
* gas/i386/x86-64-segment.s: New.
include/opcode/
2005-03-29 H.J. Lu <hongjiu.lu@intel.com>
* i386.h (i386_optab): Don't allow the `l' suffix for moving
moving between memory and segment register. Allow movq for
moving between general-purpose register and segment register.
opcodes/
2005-03-29 H.J. Lu <hongjiu.lu@intel.com>
* i386-dis.c (SEG_Fixup): New.
(Sv): New.
(dis386): Use "Sv" for 0x8c and 0x8e.
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address, and add code to test this new option.
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* cris-dis.c (print_with_operands): Use ~31L for long instead
of ~31.
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* mmix-opc.c (O): Revert the last change.
(Z): Likewise.
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* mmix-opc.c (O): Use 24UL instead of 24 for unsigned long.
(Z): Likewise.
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latter confuses xgettext into thinking that it is a C printf formating directive,
which prevents proper translation.
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for compatibility with gcc.
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BOOKE.
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... >"
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* config/tc-arm.c (tinsns): Add ARMv6K instructions sev, wfe,
wfi, yield.
opcodes:
* arm-dis.c (thumb_opcodes): Add ARMv6K instructions nop, sev,
wfe, wfi, yield.
gas/testsuite:
* gas/arm/thumbv6k.d, gas/arm/thumbv6k.s: New dump test.
* gas/arm/arm.exp: Run it.
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* opcode/arm.h: Adjust comments for ARM_EXT_V4T and ARM_EXT_V5T.
Add ARM_EXT_V6T2, ARM_ARCH_V6T2, ARM_ARCH_V6KT2, ARM_ARCH_V6ZT2,
and ARM_ARCH_V6ZKT2.
opcodes:
* arm-dis.c (arm_opcodes): Document %E and %V.
Add entries for v6T2 ARM instructions:
bfc bfi mls strht ldrht ldrsht ldrsbt movw movt rbit ubfx sbfx.
(print_insn_arm): Add support for %E and %V.
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* ppc-opc.c (insert_sprg, extract_sprg): New Functions.
(powerpc_operands <SPRG>): Call the above. Bit field is 5 bits.
(SPRG_MASK): Delete.
(XSPRG_MASK): Mask off extra bits now part of sprg field.
(powerpc_opcodes): Asjust mfsprg and mtsprg to suit new mask. Move
mfsprg4..7 after msprg and consolidate.
gas/testsuite
* gas/ppc/booke.s: Add new m[t,f]sprg testcases.
* gas/ppc/booke.d: Likewise.
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(print_insn_vax): Decode function entry mask.
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* opcodes/arc-dis.c:Add enum a4_decoding_class.
(dsmOneArcInst): Use the enum values for the decoding class
Remove redundant case in the switch for decodingClass value 11
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2005-03-02 Jan Beulich <jbeulich@novell.com>
* config/tc-i386.c (build_modrm_byte): Add lock prefix for cr8...15
accesses.
(parse_register): Allow cr8...15 in all modes.
gas/testsuite/
2005-03-02 Jan Beulich <jbeulich@novell.com>
* gas/i386/cr-err.[ls]: New.
* gas/i386/crx.[ds]: New.
* gas/i386/i386.exp: Run new tests.
opcodes/
2005-03-02 Jan Beulich <jbeulich@novell.com>
* i386-dis.c (print_insn): Suppress lock prefix printing for cr8...15
accesses.
(OP_C): Consider lock prefix in non-64-bit modes.
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* crx-dis.c (make_instruction): Warning fix.
* frv-asm.c: Regenerate.
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all of its fields are initialised before they are used.
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* arc-ext.h: Likewise.
* cgen-opc.c: Likewise.
* ia64-gen.c: Likewise.
* maxq-dis.c: Likewise.
* ns32k-dis.c: Likewise.
* w65-dis.c: Likewise.
* ia64-asmtab.c: Regenerate.
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* Makefile.in: Regenerate.
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