aboutsummaryrefslogtreecommitdiff
path: root/opcodes
AgeCommit message (Collapse)AuthorFilesLines
1996-10-03 * Makefile.in (MOSTLYCLEAN): Move config.log to distclean.Jason Molenda2-17/+21
1996-10-03 * mn10x00-opc.c, mn10x00-dis.c: New files for MatsushitaJeff Law6-18/+129
MN10x00 processors. * disassemble (ARCH_mn10x00): Define. (disassembler): Handle bfd_arch_mn10x00. * configure.in: Recognize bfd_mn10x00_arch. * configure: Rebuilt. Continue stubbing out for Matsushita work.
1996-10-03Add missing copyright.Jeff Law1-5/+23
1996-10-01 * i386-dis.c (op_rtn): Change to be a pointer. Adjust usesIan Lance Taylor1-0/+23
accordingly. Don't declare functions using op_rtn. Remove ANSI C constructs.
1996-09-17 * mips-opc.c: Add a case for "div" and "divu" with two registersIan Lance Taylor1-0/+5
and a destination of $0. PR 10654.
1996-09-11 * mips-dis.c (print_insn_arg): Add prototype.Fred Fish1-0/+5
(_print_insn_mips): Ditto.
1996-09-09 * mips-dis.c (print_insn_arg): Print condition code registers asIan Lance Taylor2-31/+85
$fccN.
1996-09-03 * v850-dis.c (disassemble): Make static. Provide prototype.Jeff Law1-0/+9
1996-09-02whoops--typoIan Lance Taylor1-0/+27
1996-09-02file was really removed a long time agoIan Lance Taylor2-32/+0
1996-08-31 * v850-dis.c (disassemble): Handle insertion of ',', '[' andJeff Law2-80/+89
']' characters into the output stream. * v850-opc.c (v850_opcodes: Remove size field from all opcodes. Add "memop" field to all opcodes (for the disassembler). Reorder opcodes so that "nop" comes before "mov" and "jr" comes before "jarl". Should give us a functional disassembler.
1996-08-31 * v850-dis.c (print_insn_v850): Properly handle disassemblingJeff Law2-2/+21
a two byte insn at the end of a memory region when the memory region's size is only two byte aligned.
1996-08-31 * v850-dis.c (v850_cc_names): Fix stupid thinkos.Jeff Law2-2/+3
1996-08-31 * v850-dis.c (v850_reg_names): Define.Jeff Law3-3/+62
(v850_sreg_names, v850_cc_names): Likewise. (disassemble): Very rough cut at printing operands (unformatted). One step at a time. * v850-opc.c (BOP_MASK): Fix. (v850_opcodes): Fix mask for jarl and jr. Bugs exposed by disassembler testing.
1996-08-31 * v850-dis.c: New file. Skeleton for disassembler support.Jeff Law1-0/+78
* Makefile.in Remove v850 references, they're not needed here and they weren't being sanitized away. * configure.in: Add v850-dis.o when building v850 toolchains. * configure: Rebuilt. * disassemble.c (disassembler): Call v850 disassembler.
1996-08-31 * v850-dis.c: New file. Skeleton for disassembler support.Jeff Law2-2/+9
* Makefile.in Remove v850 references, they're not needed here and they weren't being sanitized away. * configure.in: Add v850-dis.o when building v850 toolchains. * configure: Rebuilt. * disassemble.c (disassembler): Call v850 disassembler. Skeleton support for V850 disassembler.
1996-08-31 * v850-opc.c (insert_d8_7, extract_d8_7): New functions.Jeff Law2-19/+90
(insert_d8_6, extract_d8_6): New functions. (v850_operands): Rename D7S to D7; operand for D7 is unsigned. Rename D8 to D8_7, use {insert,extract}_d8_7 routines. Add D8_6. (IF4A, IF4B): Use "D7" instead of "D7S". (IF4C, IF4D): Use "D8_7" instead of "D8". (IF4E, IF4F): New. Use "D8_6". (v850_opcodes): Use IF4A/IF4B for sld.b/sst.b. Use IF4C/IF4D for sld.h/sst.h. Use IF4E/IF4F for sld.w/sst.w. So we can assemble sst/sld instructions correctly.
1996-08-31 * v850-opc.c (insert_d16_15, extract_d16_15): New functions.Jeff Law2-11/+52
(v850_operands): Change D16 to D16_15, use special insert/extract routines. New new D16 that uses the generic insert/extract code. (IF7A, IF7B): Use D16_15. (IF7C, IF7D): New. Use D16. (v850_opcodes): Use IF7C and IF7D for ld.b and st.b.
1996-08-31 * v850-opc.c (insert_d9, insert_d22): Slightly improve errorJeff Law2-1/+10
message. Issue an error if the branch offset is odd.
1996-08-31 * v850-opc.c: Add notes about needing special insert/extractJeff Law2-0/+9
for all the load/store insns, except "ld.b" and "st.b". So we don't forget!
1996-08-31 * v850-opc.c (insert_d22, extract_d22): New functions.Jeff Law2-2/+33
(v850_operands): Use insert_d22 and extract_d22 for D22 operands. (insert_d9): Fix range check.
1996-08-31* v850-opc.c (v850_operands): Add V850_OPERAND_SIGNED flagJ.T. Conklin2-2/+7
and set bits field to D9 and D22 operands.
1996-08-30 * v850-opc.c (v850_operands): Define SR2 operand.Jeff Law2-1/+9
(v850_opcodes): "ldsr" uses R1,SR2. ldsr is kinda weird.
1996-08-29 * v850-opc.c (v850_opcodes): Fix opcode specs forJeff Law2-5/+10
sld.w, sst.b, sst.h, sst.w, and nop.
1996-08-28 * v850-opc.c (v850_opcodes): Add null opcode to mark theJeff Law2-5/+31
end of the opcode table. For the simulator
1996-08-26Remove v850-opc.c from things-to-keepJ.T. Conklin1-1/+0
1996-08-23 * v850-opc.c (v850_operands): Define EP operand.Jeff Law2-5/+12
(IF4A, IF4B, IF4C, IF4D): Use EP.
1996-08-23 * v850-opc.c (v850_opcodes): Fix opcode numbers for "mov"Jeff Law2-7/+7
with immediate operand, "movhi". Tweak "ldsr". More fixes.
1996-08-23 * v850-opc.c (v850_opcodes): Get ld.[bhw] and st.[bhw]Jeff Law2-9/+12
correct. Get sld.[bhw] and sst.[bhw] closer.
1996-08-23 * v850-opc.c (v850_operands): "not" is a two byte insn.Jeff Law2-1/+3
1996-08-23 * v850-opc.c (v850_opcodes): Correct bit pattern for setf.Jeff Law2-1/+3
1996-08-23 * v850-opc.c (v850_operands): D16 inserts at offset 16!Jeff Law2-1/+3
1996-08-23 * v850-opc.c (two): Get order of words correct.Jeff Law2-1/+3
1996-08-23 * v850-opc.c (v850_operands): I16 inserts at offset 16!Jeff Law2-1/+3
Should get immediate 16bit operands into the right place
1996-08-23 * v850-opc.c (v850_operands): Add "SR1" and "SR2" for systemJeff Law2-2/+12
register source and destination operands. (v850_opcodes): Use SR1 and SR2 for "ldsr" and "stsr". More parsing fixes.
1996-08-23 * v850-opc.c (v850_opcodes): Fix thinko in "jmp" opcode. FixJeff Law2-2/+3
same thinko in "trap" opcode.
1996-08-23 * v850-opc.c (v850_opcodes): Fix thinko in "jmp" opcode.Jeff Law2-1/+3
1996-08-23 * v850-opc.c (v850_opcodes): Add initializer for size fieldJeff Law2-84/+87
on all opcodes.
1996-08-23 * v850-opc.c (v850_operands): D6 -> DS7. References changed.Jeff Law2-15/+29
Add D8 for 8-bit unsigned field in short load/store insns. (IF4A, IF4D): These both need two registers. (IF4C, IF4D): Define. Use 8-bit unsigned field. (v850_opcodes): For "sld.h", "sld.w", "sst.h", "sst.w", use IF4C & IF4D. For "trap" use I5U, not I5. Add IF1 operand for "ldsr" and "stsr". * v850-opc.c (v850_operands): 3-bit immediate for bit insns is unsigned. Fixing up the parser again.
1996-08-23 * v850-opc.c (v850_operansd): 3-bit immediate for bit insnsJeff Law2-1/+4
is unsigned.
1996-08-23Add V850_OPERAND_SIGNED flag as appropriate, create new unsigned IMM5 operandJ.T. Conklin1-8/+11
1996-08-23 * v850-opc.c (v850_opcodes): Correct short store half (sst.h) andJeff Law2-1/+6
short store word (sst.w).
1996-08-23start writing functions for extracting and inserting unusual operandsJ.T. Conklin1-6/+37
1996-08-23* v850-opc.c (v850_operands): Added insert and extract fields,J.T. Conklin2-15/+22
pointers to functions that handle unusual operand encodings.
1996-08-22 * v850-opc.c (v850_opcodes): Enable "trap".Jeff Law2-2/+2
1996-08-22 * v850-opc.c (v850_opcodes): Fix order of displacementJeff Law2-4/+9
and register for "set1", "clr1", "not1", and "tst1".
1996-08-22minimal setf supportJ.T. Conklin1-1/+3
1996-08-22Stub in load and store insns. Fix order of jarl operandsJ.T. Conklin1-5/+19
1996-08-22Arggh. B3. shift counts are from the start of each half-word apparently.Jeff Law1-1/+1
1996-08-22Fix thinko in B3.Jeff Law1-1/+1
generated by cgit v1.1 at 2025-01-13 16:20:51 +0000