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2024-10-07m68k: Support for jump visualization in disassemblyAndreas Schwab1-0/+27
opcodes/ * m68k-dis.c (m68k_opcode_to_insn_type): Define. (match_insn_m68k): Call it to set insn_type. (print_insn_arg) [case 'B']: Set branch target address. (print_insn_m68k): Set insn_info_valid.
2024-09-27RISC-V: correct alignment directive handling for text sectionsJan Beulich1-1/+1
.insn or data emitted inside text sections can lead to positions not being at insn granularity. In such situations using alignment directives should reliably enforce the requested alignment. Specifically requests to align back to insn granularity may not be ignored (where, as a subcase thereof, the ordering of ".option norvc" and e.g. ".p2align 2" should not matter; so far the alignment directive needs to come first to have any effect). Similarly ahead of emitting NOPs alignment first needs to be forced back to insn granularity. The new testcases actually point out a corner case issue in the disassembler as well, which is being corrected at the same time: We don't want to print "0x" without any subsequent digits.
2024-09-27x86: optimize {,V}INSERTPS with certain immediatesJan Beulich2-7/+7
They are equivalent to simple moves or xors, which are up to 3 bytes shorter to encode (and maybe/likely also cheaper to execute).
2024-09-27x86: optimize {,V}EXTRACT{F,I}{128,32x{4,8},64x{2,4}} with immediate 0Jan Beulich2-20/+20
They, too, are equivalent to simple moves, which are up to 3 bytes shorter to encode (and maybe also cheaper to execute).
2024-09-27x86: optimize {,V}EXTRACTPS with immediate 0Jan Beulich2-12/+12
They are equivalent to simple moves, which are up to 2 bytes shorter to encode (and maybe also cheaper to execute).
2024-09-26x86: templatize SIMD narrowing-move templatesJan Beulich2-72/+32
Once again to reduce redundancy.
2024-09-26x86: templatize SIMD sign-/zero-extension templatesJan Beulich2-251/+220
Yet again to reduce redundancy.
2024-09-26x86: templatize SIMD FP binary-logic templatesJan Beulich2-282/+271
Once more to reduce redundancy.
2024-09-26x86: further templatize FMA templatesJan Beulich2-349/+339
Further reduce redundancy, in preparation of the addition of counterparts for AVX10.2.
2024-09-26x86: templatize SIMD FP arithmetic templatesJan Beulich2-1135/+1100
Reduce redundancy, in preparation of the addition of further counterparts for AVX10.2. Provide the "ne" parameter needed there right away, even if unused for now.
2024-09-18x86/APX: Don't promote AVX/AVX2 instructions out of APX specH.J. Lu2-337/+197
V{BROADCAST,EXTRACT,INSERT}{F,I}128 and VROUND{P,S}{S,D} aren't promoted to support EGPR in APX spec. Don't promote them out of APX spec. This commit effectively reverted: ec3babb8c10 x86/APX: V{BROADCAST,EXTRACT,INSERT}{F,I}128 can also be expressed 5a635f1f59a x86/APX: VROUND{P,S}{S,D} encodings require AVX512{F,VL} eea4357967b x86/APX: VROUND{P,S}{S,D} can generally be encoded gas/ PR gas/32171 * testsuite/gas/i386/x86-64-apx-egpr-promote-inval.s: Add V{BROADCAST,EXTRACT,INSERT}{F,I}128 tests with EGPR. * testsuite/gas/i386/x86-64-apx-evex-promoted.s: Remove V{BROADCAST,EXTRACT,INSERT}{F,I}128 and VROUND{P,S}{S,D} tests with EGPR. * testsuite/gas/i386/x86-64-apx-egpr-inval.l: Updated. * testsuite/gas/i386/x86-64-apx-egpr-promote-inval.l: Likewise. * testsuite/gas/i386/x86-64-apx-evex-promoted-intel.d: Likewise. * testsuite/gas/i386/x86-64-apx-evex-promoted-wig.d: Likewise. * testsuite/gas/i386/x86-64-apx-evex-promoted.d: Likewise. opcodes/ PR gas/32171 * i386-opc.tbl: Remove V{BROADCAST,EXTRACT,INSERT}{F,I}128 and VROUND{P,S}{S,D} entries with EGPR. * i386-tbl.h: Regenerated. Signed-off-by: H.J. Lu <hjl.tools@gmail.com>
2024-09-12s390: Relax risbg[n]z, risb{h|l}gz, {rns|ros|rxs}bgt operand constraintsJens Remus1-15/+9
This leverages commit ("s390: Simplify (dis)assembly of insn operands with const bits") to relax the operand constraints of the immediate operand that contains the constant Z- or T-bit of the following extended mnemonics: risbgz, risbgnz, risbhgz, risblgz, rnsbgt, rosbgt, rxsbgt Previously those instructions were the only ones where the assembler on s390 restricted the specification of the subject I3/I4 operand values exactly according to their specification to an unsigned 6- or 5-bit unsigned integer. For any other instructions the assembler allows to specify any operand value allowed by the instruction format, regardless of whether the instruction specification is more restrictive. Allow to specify the subject I3/I4 operand as unsigned 8-bit integer with the constant operand bits being ORed during assembly. Relax the instructions subject significant operand bit masks to only consider the Z/T-bit as significant, so that the instructions get disassembled as their *z or *t flavor regardless of whether any reserved bits are set in addition to the Z/T-bit. Adapt the rnsbg, rosbg, and rxsbg test cases not to inadvertently set the T-bit in operand I3, as they otherwise get disassembled as their rnsbgt, rosbgt, and rxsbgt counterpart. This aligns GNU Assembler to LLVM Assembler. opcodes/ * s390-opc.c (U6_18, U5_27, U6_26): Remove. (INSTR_RIE_RRUUU2, INSTR_RIE_RRUUU3, INSTR_RIE_RRUUU4): Define as INSTR_RIE_RRUUU while retaining insn fmt mask. (MASK_RIE_RRUUU2, MASK_RIE_RRUUU3, MASK_RIE_RRUUU4): Treat only Z/T-bit of I3/I4 operand as significant. gas/testsuite/ * gas/s390/zarch-z10.s (rnsbg, rosbg, rxsbg): Do not set T-bit. Reported-by: Dominik Steenken <dost@de.ibm.com> Suggested-by: Ulrich Weigand <ulrich.weigand@de.ibm.com> Signed-off-by: Jens Remus <jremus@linux.ibm.com>
2024-09-12s390: Simplify (dis)assembly of insn operands with const bitsJens Remus2-23/+17
Simplify assembly and disassembly of extended mnemonics with operands with constant ORed bits: Their instruction template already contains the respective constant operand bits, as they are significant to distinguish the extended from their base mnemonic. Operands are ORed into the instruction template. Therefore it is not necessary to OR the constant bits into the operand value during assembly in s390_insert_operand. Additionally the constant operand bits from the instruction template can be used to mask them from the operand value during disassembly in s390_print_insn_with_opcode. For now do so for non-length unsigned integer operands only. The separate instruction formats need to be retained, as their masks differ, which is relevant during disassembly to distinguish the base and extended mnemonics from each other. This affects the following extended mnemonics: - vfaebs, vfaehs, vfaefs - vfaezb, vfaezh, vfaezf - vfaezbs, vfaezhs, vfaezfs - vstrcbs, vstrchs, vstrcfs - vstrczb, vstrczh, vstrczf - vstrczbs, vstrczhs, vstrczfs - wcefb, wcdgb - wcelfb, wcdlgb - wcfeb, wcgdb - wclfeb, wclgdb - wfisb, wfidb, wfixb - wledb, wflrd, wflrx include/ * opcode/s390.h (S390_OPERAND_OR1, S390_OPERAND_OR2, S390_OPERAND_OR8): Remove. opcodes/ * s390-opc.c (U4_OR1_24, U4_OR2_24, U4_OR8_28): Remove. (INSTR_VRR_VVV0U1, INSTR_VRR_VVV0U2, INSTR_VRR_VVV0U3): Define as INSTR_VRR_VVV0U0 while retaining respective insn fmt mask. (INSTR_VRR_VV0UU8): Define as INSTR_VRR_VV0UU while retaining respective insn fmt mask. (INSTR_VRR_VVVU0VB1, INSTR_VRR_VVVU0VB2, INSTR_VRR_VVVU0VB3): Define as INSTR_VRR_VVVU0VB while retaining respective insn fmt mask. * s390-dis.c (s390_print_insn_with_opcode): Mask constant operand bits set in insn template of non-length unsigned integer operands. gas/ * config/tc-s390.c (s390_insert_operand): Do not OR constant operand value bits. Signed-off-by: Jens Remus <jremus@linux.ibm.com>
2024-09-11x86/APX: correct disassembly for EVEX.B4Jan Beulich1-2/+3
EVEX.B4 is used only for GPR (or addressing of memory) operands. SIMD registers encoded via ModR/M.rm (when ModR/M.mod == 3) have their top bit in EVEX.X3. Supposedly (doc version 004) EVEX.B4 is ignored when unused, hence also don't flag such encodings as invalid.
2024-09-09s390: Align opcodes to lower-caseJens Remus1-1/+1
opcodes/ * s390-opc.txt (rdp): Change opcode to lower-case. Signed-off-by: Jens Remus <jremus@linux.ibm.com>
2024-09-06x86/APX: use D for 2-operand CFCMOVccJan Beulich2-577/+276
There's no need to have 30 redundant templates when we can easily take care of the operand swapping like we do for various other insns.
2024-09-06x86/APX: optimize certain reg-only CFCMOVcc formsJan Beulich2-31/+31
Along the lines of 2513312930b2 ("x86/APX: apply NDD-to-legacy transformation to further CMOVcc forms") these can similarly be converted to the shorter legacy-encoded CMOVcc.
2024-09-06x86: templatize VNNI templatesJan Beulich2-46/+37
Reduce redundancy, in preparation of the addition of further counterparts for AVX10.2.
2024-09-03RISC-V: Add support for XCVsimd extension in CV32E40PMary Bennett2-0/+231
Spec: https://docs.openhwgroup.org/projects/cv32e40p-user-manual/en/latest/instruction_set_extensions.html Contributors: Mary Bennett <mary.bennett682@gmail.com> Nandni Jamnadas <nandni.jamnadas@embecosm.com> Pietra Ferreira <pietra.ferreira@embecosm.com> Charlie Keaney Jessica Mills Craig Blackmore <craig.blackmore@embecosm.com> Simon Cook <simon.cook@embecosm.com> Jeremy Bennett <jeremy.bennett@embecosm.com> Helene Chelin <helene.chelin@embecosm.com> bfd/ChangeLog: * elfxx-riscv.c (riscv_multi_subset_supports): Add `xcvsimd` instruction class. (riscv_multi_subset_supports_ext): Likewise. gas/ChangeLog: * NEWS: Updated. * config/tc-riscv.c (validate_riscv_insn): Add custom operands. (riscv_ip): Likewise. * doc/c-riscv.texi: Note XCVsimd as an additional ISA extension for CORE-V. * testsuite/gas/riscv/march-help.l: Add xcvsimd. * testsuite/gas/riscv/x-cv-simd.d: New test. * testsuite/gas/riscv/x-cv-simd.s: New test. * testsuite/gas/riscv/x-cv-simd-fail.d: New test. * testsuite/gas/riscv/x-cv-simd-fail.l: New test. * testsuite/gas/riscv/x-cv-simd-fail.s: New test. include/ChangeLog: * opcode/riscv-opc.h: Add corresponding MATCH and MASK macros for XCVsimd. * opcode/riscv.h: Add corresponding EXTRACT and ENCODE macros for XCVsimd. (enum riscv_insn_class): Add the XCVsimd instruction class. opcodes/ChangeLog: * riscv-dis.c (print_insn_args): Add custom operands. * riscv-opc.c: Add XCVsimd instructions.
2024-09-02Support ymm rounding control for Intel AVX10.2Haochen Jiang6-629/+666
In the patch, in order to support ymm rounding for AVX10.2, we derive evex attribute for all cases instead of only for rc_none to encode U bit. Also changed some bad_opcode return due to the share of U bit with APX_F. gas/ChangeLog: * config/tc-i386.c (cpu_flags_match): Handle AVX10_2. (build_evex_prefix): Handle U bit. Derive evex attribute for all cases. (check_VecOperands): Handle AVX10.2 and ymm roundings. * doc/c-i386.texi: Document .avx10.2. * testsuite/gas/i386/i386.exp: Run AVX10.2 tests. * testsuite/gas/i386/x86-64.exp: Ditto. * testsuite/gas/i386/avx10_2-rounding-intel.d: New test. * testsuite/gas/i386/avx10_2-rounding-inval.l: Ditto. * testsuite/gas/i386/avx10_2-rounding-inval.s: Ditto. * testsuite/gas/i386/avx10_2-rounding.d: Ditto. * testsuite/gas/i386/avx10_2-rounding.s: Ditto. * testsuite/gas/i386/x86-64-avx10_2-rounding-intel.d: Ditto. * testsuite/gas/i386/x86-64-avx10_2-rounding.d: Ditto. * testsuite/gas/i386/x86-64-avx10_2-rounding.s: Ditto. opcodes/ChangeLog: * i386-dis.c (struct instr_info): Add U bit. (get_valid_dis386): Handle U bit. * i386-gen.c (isa_dependencies): Add AVX10.2. (cpu_flags): Ditto. * i386-init.h: Regenerated. * i386-opc.h (CpuAVX10_2): New. (i386_cpu_flags): Add cpuavx10_2. * i386-opc.tbl: Add rounding to old entries which do not permit rounding previously. Also eliminate the redundant RegXMM for vcvtps2uqq. * i386-tbl.h: Regenerated.
2024-08-30x86/APX: drop %SW disassembler macro againJan Beulich2-17/+19
Not the least due to its extremely rare use I didn't really like that macro's introduction. Adjust swap_operand() accordingly instead.
2024-08-30x86: limit RegRex64 useJan Beulich2-48/+48
The special property really only applies to the "extended" byte regs having legacy word/dword counterparts. While touching involved code also drop redundant byte checks from a conditional in establish_rex(): The other remaining RegRex64 uses only exist on registers which can't be used as register operands anyway. Hence RegRex64 as an attribute of a (valid) register operand implies that it's a byte reg.
2024-08-27RISC-V: PR32036, Support Zcmp cm.mva01s and cm.mvsa01 instructions.Jiawei2-0/+28
This patch supports Zcmp instruction 'cm.mva01s' and 'cm.mvsa01'. All disassemble instructions use the sreg format. Co-Authored by: Charlie Keaney <charlie.keaney@embecosm.com> Co-Authored by: Mary Bennett <mary.bennett@embecosm.com> Co-Authored by: Nandni Jamnadas <nandni.jamnadas@embecosm.com> Co-Authored by: Sinan Lin <sinan.lin@linux.alibaba.com> Co-Authored by: Simon Cook <simon.cook@embecosm.com> Co-Authored by: Shihua Liao <shihua@iscas.ac.cn> Co-Authored by: Yulong Shi <yulong@iscas.ac.cn> gas/ChangeLog: PR 32036 * NEWS: Updated. * config/tc-riscv.c (validate_riscv_insn): New operators. (riscv_ip): Ditto. * testsuite/gas/riscv/zcmp-mv.d: New test. * testsuite/gas/riscv/zcmp-mv.s: New test. include/ChangeLog: PR 32036 * opcode/riscv-opc.h (MATCH_CM_MVA01S): New opcode. (MASK_CM_MVA01S): New mask. (MATCH_CM_MVSA01): New opcode. (MASK_CM_MVSA01): New mask. (DECLARE_INSN): New declarations. * opcode/riscv.h (OP_MASK_SREG1): New mask. (OP_SH_SREG1): New operand code. (OP_MASK_SREG2): New mask. (OP_SH_SREG2): New operand code. (X_A0): New reg number. (X_A1): Ditto. (X_S7): Ditto. (RISCV_SREG_0_7): New macro function. opcodes/ChangeLog: PR 32036 * riscv-dis.c (riscv_zcmp_get_sregno): New function. (print_insn_args): New operators. * riscv-opc.c (match_sreg1_not_eq_sreg2): New match function.
2024-08-16opcodes/cgen: drop trailing whitespace also for crisJan Beulich2-48/+48
While 919b75f7e289 ("Trailing space in opcodes/ generated files") took care of permanently zapping trailing whitespace, 547112801156 ("opcodes: cris: move desc & opc files from sim/") then didn't enhance the newly added code accordingly.
2024-08-12Revert "gas: have scrubber retain more whitespace"H.J. Lu14-447/+234
This reverts commit 6ae8a30d44f016cafb46a75843b5109316eb1996. This fixes PR gas/32073.
2024-08-09gas: have scrubber retain more whitespaceJan Beulich14-234/+447
According to the description of the state machine, the expectation appears to be that (leaving aside labels) any insn mnemonic or directive would be followed by a comma separated list of operands. That may have been true very long ago, but the latest with the advent of more elaborate macros this isn't rhe case anymore. Neither macro parameters in macro definitions nor macro arguments in macro invocations are required to be separated by commas. Hence whitespace serves a crucial role there. Plus even without "real" macros issues exist, in e.g. .irp n, ... insn\n\(suffix) operand1, operand2 .endr Whitespace following the closing parenthesis would have been removed (ahead of even processing the .irp), as the "opcode" was deemed to have ended earlier already. Therefore, squash the distinction between "opcode" and operands, i.e. fold state 10 back into state 3. Also drop most of the distinction between "symbol chars" and "relatively normal" ones. Not entirely unexpectedly this results in the need to skip whitespace in a few more places in arch-specific code (and quite likely more changes are needed for insn forms not covered by the testsuite). As a result the D10V special case is no longer necessary. In config/tc-sparc.c also move a comment to be next to the code being commented. In opcodes/cgen-asm.in some further cleanup is done, following the local var adjustments.
2024-08-09gas: sparc: Fix faligndatai assembly and disassemblyRichard Henderson1-1/+1
The first operand is a general register, not an fp register; the third operand is encoded into RS2, not RS3; the second operand must match the destination operand.
2024-08-06RISC-V: map zext.h to pack/packw if Zbkb is enabledHau Hsu1-2/+2
The `zext.h` is zero-extend halfword instruction that belongs to Zbb. Currently `zext.h` falls back to 2 shifts if Zbb is not enabled. However, the encoding and operation is a special case of `pack/packw rd, rs1, rs2`, which belongs to Zbkb. The instructions pack the low halves of rs1 and rs2 into rd. When rs2 is zero (x0), they behave like zero-extend instruction, and the encoding are exactly the same as zext.h. Thus we can map `zext.h` to `pack` or `packw` (rv64) if Zbkb is enabled, instead of 2 shifts. This reduces one instruction. This patch does this by making `zext.h` also available for Zbkb. opcodes/ * riscv-opc.c (riscv_opcodes): Update `zext.h` entries to use `ZBB_OR_ZBKB` instruction class. gas/ * testsuite/gas/riscv/zext-to-pack.s: Add test for mapping zext to pack/packw encoding. * testsuite/gas/riscv/zext-to-pack-encoding.d: Likewise. * testsuite/gas/riscv/zext-to-packw-encoding.d: Likewise.
2024-08-06RISC-V: Add support for XCvBitmanip extension in CV32E40PMary Bennett2-0/+27
Spec: https://docs.openhwgroup.org/projects/cv32e40p-user-manual/en/latest/instruction_set_extensions.html Contributors: Mary Bennett <mary.bennett682@gmail.com> Nandni Jamnadas <nandni.jamnadas@embecosm.com> Pietra Ferreira <pietra.ferreira@embecosm.com> Charlie Keaney Jessica Mills Craig Blackmore <craig.blackmore@embecosm.com> Simon Cook <simon.cook@embecosm.com> Jeremy Bennett <jeremy.bennett@embecosm.com> Helene Chelin <helene.chelin@embecosm.com> bfd/ChangeLog: * elfxx-riscv.c (riscv_multi_subset_supports): Add `xcvbitmanip` instruction class. (riscv_multi_subset_supports_ext): Likewise. gas/ChangeLog: * config/tc-riscv.c (validate_riscv_insn): Add custom operands `Xc6` and `Xc7`. (riscv_ip): Likewise. * doc/c-riscv.texi: Note XCVbitmanip as an additional ISA extension for CORE-V. * testsuite/gas/riscv/march-help.l: Add xcvbitmanip. * testsuite/gas/riscv/x-cv-bitmanip-fail.d: New Test. * testsuite/gas/riscv/x-cv-bitmanip-fail.l: New Test. * testsuite/gas/riscv/x-cv-bitmanip-fail.s: New Test. * testsuite/gas/riscv/x-cv-bitmanip.d: New Test. * testsuite/gas/riscv/x-cv-bitmanip.s: New Test. include/opcode/ChangeLog: * riscv-opc.h: Add corresponding MATCH and MASK macros for XCVbitmanip. * riscv.h: Add corresponding EXTRACT and ENCODE macros for XCVbitmanip. (enum riscv_insn_class): Add the XCVbitmanip instruction class. opcodes/ChangeLog: * riscv-dis.c (print_insn_args): Add custom operands `Xc6` and `Xc7`. * riscv-opc.c: Add XCvBitmanip instructions.
2024-08-06RISC-V: Add support for Zcmop extensionXiao Zeng1-0/+10
This implements the Zcmop (Compressed Zimop) extension, as of version 1.0. View detailed information in: <https://github.com/riscv/riscv-isa-manual/blob/main/src/zimop.adoc> The Zcmop extension requires the Zca extension. bfd/ChangeLog: * elfxx-riscv.c (riscv_multi_subset_supports): Handle Zcmop. (riscv_multi_subset_supports_ext): Ditto. gas/ChangeLog: * NEWS: Updated. * testsuite/gas/riscv/march-help.l: Ditto. * testsuite/gas/riscv/zcmop.d: New test. * testsuite/gas/riscv/zcmop.s: New test. include/ChangeLog: * opcode/riscv-opc.h (DECLARE_INSN): New declarations for Zcmop. (MATCH_C_MOP_1, MATCH_C_MOP_3, MATCH_C_MOP_5, MATCH_C_MOP_7, MATCH_C_MOP_9, MATCH_C_MOP_11, MATCH_C_MOP_13, MATCH_C_MOP_15): Define. (MASK_C_MOP_1, MASK_C_MOP_3, MASK_C_MOP_5, MASK_C_MOP_7, MASK_C_MOP_9, MASK_C_MOP_11, MASK_C_MOP_13, MASK_C_MOP_15): Ditto. * opcode/riscv.h (enum riscv_insn_class): Add INSN_CLASS_ZCMOP. opcodes/ChangeLog: * riscv-opc.c: Add Zcmop instructions.
2024-08-06RISC-V: Add support for Zimop extensionXiao Zeng1-0/+42
This implements the Zimop (May-Be-Operations) extension, as of version 1.0. View detailed information in: <https://github.com/riscv/riscv-isa-manual/blob/main/src/zimop.adoc> bfd/ChangeLog: * elfxx-riscv.c (riscv_multi_subset_supports): Handle Zimop (riscv_multi_subset_supports_ext): Ditto. gas/ChangeLog: * NEWS: Updated. * testsuite/gas/riscv/march-help.l: Ditto. * testsuite/gas/riscv/zimop.d: New test. * testsuite/gas/riscv/zimop.s: New test. include/ChangeLog: * opcode/riscv-opc.h (DECLARE_INSN): New declarations for Zimop. (MATCH_MOP_R_0, MATCH_MOP_R_1, MATCH_MOP_R_2, MATCH_MOP_R_3, MATCH_MOP_R_4, MATCH_MOP_R_5, MATCH_MOP_R_6, MATCH_MOP_R_7, MATCH_MOP_R_8, MATCH_MOP_R_9, MATCH_MOP_R_10, MATCH_MOP_R_11, MATCH_MOP_R_12, MATCH_MOP_R_13, MATCH_MOP_R_14, MATCH_MOP_R_15, MATCH_MOP_R_16, MATCH_MOP_R_17, MATCH_MOP_R_18, MATCH_MOP_R_19, MATCH_MOP_R_20, MATCH_MOP_R_21, MATCH_MOP_R_22, MATCH_MOP_R_23, MATCH_MOP_R_24, MATCH_MOP_R_25, MATCH_MOP_R_26, MATCH_MOP_R_27, MATCH_MOP_R_28, MATCH_MOP_R_29, MATCH_MOP_R_30, MATCH_MOP_R_31, MATCH_MOP_RR_0, MATCH_MOP_RR_1, MATCH_MOP_RR_2, MATCH_MOP_RR_3, MATCH_MOP_RR_4, MATCH_MOP_RR_5, MATCH_MOP_RR_6, MATCH_MOP_RR_7): Define. (MASK_MOP_R_0, MASK_MOP_R_1, MASK_MOP_R_2, MASK_MOP_R_3, MASK_MOP_R_4, MASK_MOP_R_5, MASK_MOP_R_6, MASK_MOP_R_7, MASK_MOP_R_8, MASK_MOP_R_9, MASK_MOP_R_10, MASK_MOP_R_11, MASK_MOP_R_12, MASK_MOP_R_13, MASK_MOP_R_14, MASK_MOP_R_15, MASK_MOP_R_16, MASK_MOP_R_17, MASK_MOP_R_18, MASK_MOP_R_19, MASK_MOP_R_20, MASK_MOP_R_21, MASK_MOP_R_22, MASK_MOP_R_23, MASK_MOP_R_24, MASK_MOP_R_25, MASK_MOP_R_26, MASK_MOP_R_27, MASK_MOP_R_28, MASK_MOP_R_29, MASK_MOP_R_30, MASK_MOP_R_31, MASK_MOP_RR_0, MASK_MOP_RR_1, MASK_MOP_RR_2, MASK_MOP_RR_3, MASK_MOP_RR_4, MASK_MOP_RR_5, MASK_MOP_RR_6, MASK_MOP_RR_7): Ditto. * opcode/riscv.h (enum riscv_insn_class): Add INSN_CLASS_ZIMOP. opcodes/ChangeLog: * riscv-opc.c: Add Zimop instructions.
2024-07-29Updated translations for the bfd, binutils, gas, ld and opcodes directoriesNick Clifton3-557/+573
2024-07-26microMIPS: Add MT ASE instruction set supportYunQiang Su2-1/+61
Add the MT ASE instruction operand types and encodings to the microMIPS opcode table and enable the assembly of these instructions in GAS from MIPSr2 onwards. Update the binutils and GAS testsuites accordingly. References: "MIPS Architecture for Programmers, Volume IV-f: The MIPS MT Module for the microMIPS32 Architecture", MIPS Technologies, Inc., Document Number: MD00768, Revision 1.12, July 16, 2013 Co-Authored-By: Maciej W. Rozycki <macro@redhat.com>
2024-07-26x86/APX: optimize certain {nf}-form insns to BMI2 onesJan Beulich2-27/+27
..., as those leave EFLAGS untouched anyway. That's a shorter encoding, available as long as no eGPR is in use anywhere.
2024-07-26ARM print_insn_mve assertionAlan Modra1-17/+2
This corrects objdump -d -m armv8.1-m.main output for a testcase found by oss-fuzz, .inst 0xee2fee79, which hits an assertion. Obviously the switch case constants should be binary, not hex. Correcting that is enough to cure this assertion, but I don't see any point in singling out the invalid case 0b10. In fact, it is just plain wrong to print "undefined instruction: size equals zero undefined instruction: size equals two". I also don't see the need for defensive programming here as is done elsewhere in checking that "value" is in range before indexing mve_vec_sizename. There is exactly one MVE_VSHLL_T2 entry in mve_opcodes. It is easy to verify that "value" is only two bits.
2024-07-24opcodes/x86: fix minor missed styling caseAndrew Burgess1-2/+2
I noticed that the x86 instruction: sar $1,%rsi would fail to style the '$0x1' as an immediate. This commit fixes that case.
2024-07-20Change version to 2.43.50Nick Clifton2-193/+195
2024-07-20Add markers for 2.43 branch/releaseNick Clifton1-0/+4
2024-07-19MIPS/opcodes: Replace "y" microMIPS operand code with "x"Maciej W. Rozycki1-2/+2
Replace the "y" microMIPS operand code, used with ALNV.PS only, with "x" so as to make "y" available for microMIPS MT use.
2024-07-19MIPS/opcodes: Mark MT thread context move assembly idioms as aliasesMaciej W. Rozycki1-38/+38
A number of instructions in the regular MIPS opcode table are assembly idioms for the MT thread context move MFTR and MTTR instructions, so mark them as aliases accordingly. Add suitable test cases, which also cover the PAUSE assembly idiom.
2024-07-19MIPS/opcodes: Mark PAUSE as an aliasMaciej W. Rozycki1-1/+1
PAUSE is an assembly idiom for 'sll $0,$0,5', so mark it as an alias in the regular MIPS opcode table, matching the microMIPS opcode table. A test case will be supplied separately.
2024-07-19MIPS/opcodes: Reorder coprocessor moves alphabeticallyMaciej W. Rozycki2-58/+62
A number of coprocessor move encodings have been randomly sprinkled over the regular MIPS and microMIPS opcode tables rather than where they'd be expected following the alphabetic order. Fix the ordering, taking into account precedence where it has to be observed for correct disassembly. No functional change.
2024-07-19MIPS/opcodes: Make AL a shorthand for INSN2_ALIASMaciej W. Rozycki2-56/+60
Make AL a shorthand for INSN2_ALIAS with the regular MIPS and microMIPS opcode tables, just as with the MIPS16 opcode table, and use it throughout. No functional change.
2024-07-19MIPS/opcodes: Rename the AL membership shorthand to ALXMaciej W. Rozycki1-88/+88
Make room for AL as a shorthand for INSN2_ALIAS with the regular MIPS opcode table, just as with the MIPS16 opcode table. No functional change.
2024-07-19MIPS/opcodes: Remove the regular MIPS "+t" operand codeYunQiang Su1-2/+1
The semantics of the regular MIPS "+t" operand code is exactly the same as that of the "E" operand code, so replace the former with the latter in the single MFTC0 instruction with implicit 'sel' == 0 encoding where it's used, matching the encoding with explicit 'sel' as well as other instructions.
2024-07-19MIPS/opcodes: Output thread context registers numerically with MFTR/MTTRMaciej W. Rozycki1-2/+2
We print MFTR and MTTR instructions' thread context register operand in disassembly using the ABI name the register number would correspond to should the targeted register be a general-purpose register. However in most cases it is wrong, because general-purpose registers are only referred when the 'u' and 'sel' operands are 1 and 0 respectively. And even in these cases the MFGPR and MTGPR aliases take precedence over the corresponding generic instruction encodings, so you won't see the valid case to normally trigger. Conversely decoding the thread context register operand numerically is always valid, so switch to using it. Adjust test coverage accordingly.
2024-07-19MIPS/opcodes: Exclude $0 from "-x" R6 operand typeMaciej W. Rozycki1-1/+1
The "-x" operand type is used for the reverse encoding of the BOVC and BNVC instructions, where 'rs' and 'rt' have been supplied as the second and the first operand respectively rather than the order the instruction expects. In this case we require the register associated with the "-x" operand to have a higher number than the register associated with the preceding "t" operand, which precludes the use of $0. The case where 'rs' and 'rt' both refer to the same register is handled by the straight encoding of the BOVC and BNVC instructions, which come in the opcode table ahead of the corresponding reverse encoding. Therefore clear the ZERO_OK flag for the "-x" operand. No need for an extra test case as the encodings involved are already covered by "r6" and its associated GAS tests.
2024-07-18opcodes: aarch64: enforce checks on subclass flags in aarch64-gen.cIndu Bhagat1-0/+19
Enforce some checks on the newly added subclass flags: - If a subclass is set of one insn of an iclass, every insn of that iclass must have non-zero subclass field. - For all other iclasses, the subclass bits are zero for all insns. include/ * opcode/aarch64.h (enum aarch64_insn_class): Identify the maximum iclass enum value. opcodes/ * aarch64-gen.c (iclass_has_subclasses_p): New array of bool. (read_table): Enforce checks on subclass flags.
2024-07-18opcodes: aarch64: denote subclasses for insns of iclass dp_2srcIndu Bhagat1-24/+24
For detecting irg, add a subclass to identify it in the set of instructions of iclass dp_2src. opcodes/ * aarch64-tbl.h: Add subclass flag F_DP_TAG_ONLY for irg insn.
2024-07-18opcodes: aarch64: add flags to denote subclasses of uncond branchesIndu Bhagat1-19/+19
Use the two new subclass flags: F_BRANCH_CALL, F_BRANCH_RET, to indicate call to and return from subroutine respectively. opcodes/ * aarch64-tbl.h: Use the new F_BRANCH_* flags.
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