| Age | Commit message (Expand) | Author | Files | Lines |
|---|
| 2022-11-28 | RISC-V: Better support for long instructions (disassembler) | Tsukasa OI | 1 | -5/+9 |
| 2022-11-24 | x86: widen applicability and use of CheckRegSize | Jan Beulich | 2 | -14/+14 |
| 2022-11-24 | x86: add missing CheckRegSize | Jan Beulich | 2 | -6/+6 |
| 2022-11-24 | x86: correct handling of LAR and LSL | Jan Beulich | 3 | -6/+50 |
| 2022-11-24 | PR16995, m68k coldfire emac immediate to macsr incorrect disassembly | Alan Modra | 1 | -2/+2 |
| 2022-11-22 | opcodes: Correct address for ARC's "isa_config" aux reg | Shahab Vahedi | 2 | -1/+7 |
| 2022-11-17 | opcodes: Define NoSuf in i386-opc.tbl | H.J. Lu | 1 | -1847/+1848 |
| 2022-11-17 | i386: Move i386_seg_prefixes to gas | H.J. Lu | 2 | -11/+0 |
| 2022-11-17 | RISC-V: Add T-Head Int vendor extension | Christoph Müllner | 1 | -0/+4 |
| 2022-11-17 | RISC-V: Add T-Head Fmv vendor extension | Christoph Müllner | 1 | -0/+4 |
| 2022-11-15 | Add AMD znver4 processor support | Tejas Joshi | 6 | -4052/+4129 |
| 2022-11-14 | aarch64: Add support for Common Short Sequence Compression extension | Andre Vieira | 6 | -49/+166 |
| 2022-11-14 | x86: fold special-operand insn attributes into a single enum | Jan Beulich | 4 | -11219/+11210 |
| 2022-11-12 | PowerPC64 paddi -Mraw | Alan Modra | 1 | -10/+10 |
| 2022-11-11 | x86: drop stray IsString from PadLock insns | Jan Beulich | 2 | -32/+32 |
| 2022-11-10 | [opcodes/arm] Fix potential null pointer dereferences | Luis Machado | 1 | -1/+5 |
| 2022-11-09 | RISC-V: xtheadfmemidx: Use fp register in mnemonics | Christoph Müllner | 1 | -8/+8 |
| 2022-11-08 | PowerPC: Add XSP operand define | Peter Bergner | 1 | -5/+6 |
| 2022-11-08 | x86: Correct wrong comments in vex_w_table | Haochen Jiang | 1 | -1/+1 |
| 2022-11-08 | Support Intel RAO-INT | Kong Lingling | 6 | -4174/+4278 |
| 2022-11-04 | opcodes/arm: silence compiler warning about uninitialized variable use | Andrew Burgess | 1 | -1/+3 |
| 2022-11-04 | Support Intel AVX-NE-CONVERT | konglin1 | 6 | -4169/+4397 |
| 2022-11-04 | i386: Rename <xy> template. | konglin1 | 1 | -17/+18 |
| 2022-11-02 | x86: drop bogus Tbyte | Jan Beulich | 2 | -4/+4 |
| 2022-11-02 | Support Intel MSRLIST | Hu, Lin1 | 6 | -4161/+4237 |
| 2022-11-02 | Support Intel WRMSRNS | Hu, Lin1 | 6 | -4160/+4212 |
| 2022-11-02 | Support Intel CMPccXADD | Haochen Jiang | 6 | -4150/+4805 |
| 2022-11-02 | Support Intel AVX-VNNI-INT8 | Cui,Lili | 6 | -456/+612 |
| 2022-11-02 | Support Intel AVX-IFMA | Hongyu Wang | 7 | -4145/+4224 |
| 2022-11-01 | opcodes/arm: don't pass non-string literal to printf like function | Andrew Burgess | 1 | -2/+3 |
| 2022-11-01 | opcodes/arm: silence compiler warning about uninitialized variable use | Andrew Burgess | 1 | -1/+3 |
| 2022-11-01 | opcodes/arm: add disassembler styling for arm | Andrew Burgess | 2 | -1002/+1631 |
| 2022-11-01 | opcodes/arm: use '@' consistently for the comment character | Andrew Burgess | 1 | -48/+48 |
| 2022-10-31 | x86: minor improvements to optimize_imm() (part III) | Jan Beulich | 2 | -6/+0 |
| 2022-10-31 | Updated Romainain translation for the binutils sub-directory and Swedish tran... | Nick Clifton | 1 | -399/+475 |
| 2022-10-31 | Support Intel PREFETCHI | Cui, Lili | 6 | -4141/+4263 |
| 2022-10-31 | RX assembler: switch arguments of thw MVTACGU insn. | Yoshinori Sato | 3 | -8/+13 |
| 2022-10-28 | RISC-V: Output mapping symbols with ISA string. | Nelson Chu | 1 | -0/+9 |
| 2022-10-27 | PowerPC: Add support for RFC02658 - MMA+ Outer-Product Instructions | Peter Bergner | 1 | -1/+38 |
| 2022-10-27 | PowerPC: Add support for RFC02653 - Dense Math Facility | Peter Bergner | 2 | -26/+191 |
| 2022-10-24 | x86: emit {evex} prefix when disassembling ambiguous AVX512VL insns | Jan Beulich | 6 | -235/+271 |
| 2022-10-21 | Support Intel AMX-FP16 | Cui,Lili | 6 | -4088/+4139 |
| 2022-10-20 | x86: re-work AVX-VNNI support | Jan Beulich | 4 | -7025/+7021 |
| 2022-10-18 | x86: Disable AVX-VNNI when disabling AVX2 | H.J. Lu | 2 | -3/+3 |
| 2022-10-18 | x86: correct CPU_AMX_{BF16,INT8}_FLAGS | Jan Beulich | 2 | -4/+4 |
| 2022-10-17 | Allow explicit size specifier for predicate operand of {sq, uq, }{incp, decp} | CaiJingtao | 2 | -7/+17 |
| 2022-10-17 | aarch64: Tweak handling of F_STRICT | Richard Sandiford | 1 | -17/+8 |
| 2022-10-17 | x86: properly decode EVEX.W for AVX512_4{FMAPS,VNNIW} insns | Jan Beulich | 1 | -6/+6 |
| 2022-10-17 | x86: fold AVX512-VNNI disassembler entries with AVX-VNNI ones | Jan Beulich | 3 | -15/+22 |
| 2022-10-16 | PowerPC se_rfmci and VLE, SPE2 and LSP insns with -many | Alan Modra | 2 | -1/+9 |
