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2022-10-20x86: re-work AVX-VNNI supportJan Beulich4-7025/+7021
By putting the templates after their AVX512 counterparts, the AVX512 flavors will be picked by default. That way the need to always use {vex} ceases to exist once respective CPU features (AVX512-VNNI or AVX512VL as a whole) have been disabled. This way the need for the PseudoVexPrefix attribute also disappears.
2022-10-18x86: Disable AVX-VNNI when disabling AVX2H.J. Lu2-3/+3
Since AVX-VNNI requires AVX2, disable AVX-VNNI when disabling AVX2. * i386-gen.c (cpu_flag_init): Add CpuAVX_VNNI to CPU_ANY_AVX2_FLAGS. * i386-init.h: Regenerate.
2022-10-18x86: correct CPU_AMX_{BF16,INT8}_FLAGSJan Beulich2-4/+4
AMX-TILE is a prereq to these, as already correctly expressed by CPU_ANY_AMX_TILE_FLAGS. Express the dependency also in the reverse ("positive") direction.
2022-10-17Allow explicit size specifier for predicate operand of {sq, uq, }{incp, decp}CaiJingtao2-7/+17
Omitting predicate size specifier in vector form of {sq, uq, }{decp, incp} is deprecated and will be prohibited in a future release of the aarch64, see https://developer.arm.com/documentation/ddi0602/2021-09/SVE-Instructions/DECP--vector---Decrement-vector-by-count-of-true-predicate-elements-. This allows explicit size specifier, e.g. `decp z0.h, p0.h`, for predicate operand of these SVE instructions. The existing behaviour of not requiring the specifier is preserved. And the disasembly is with the specifier with this patch. The GAS tests passed under our local tests. opcodes/ * aarch64-asm.c: Modify `sve_size_hsd` encoding. * aarch64-tbl.h (aarch64_opcode_table): Add QUALS's type OP_SVE_Vv_HSD for decp, incp, sqdecp, sqincp, uqdecp and uqincp. gas/ * testsuite/gas/aarch64/sve-movprfx_23.s: Update movprfx_23 testcase's test_sametwo macro, where take the predicate size specifier. * testsuite/gas/aarch64/sve-movprfx_23.d: Update movprfx_23 testcase's expected disassembly. * testsuite/gas/aarch64/sve-movprfx_23.l: Update movprfx_23 testcase's expected assembler messages. * testsuite/gas/aarch64/sve.s: Add sve testcase's instructions for decp, incp, sqdecp, sqincp, uqdecp and uqincp, which take the predicate size specifier. * testsuite/gas/aarch64/sve.d: Update sve testcase's expected disassembly. Signed-off-by: CaiJingtao <caijingtao@huawei.com>
2022-10-17aarch64: Tweak handling of F_STRICTRichard Sandiford1-17/+8
Current F_STRICT qualifier checking is enforced after the fact rather than as part of the match. This makes it impossible to have, e.g.: QLF2(S_D, S_D) QLF2(S_D, NIL) in the same list. opcodes/ * aarch64-opc.c (aarch64_find_best_match): Handle F_STRICT here rather than... (match_operands_qualifier): ...here.
2022-10-17x86: properly decode EVEX.W for AVX512_4{FMAPS,VNNIW} insnsJan Beulich1-6/+6
These require EVEX.W=0. Use %XS to facilitate the checking, even if for the AVX512_4VNNIW ones this is kind of an abuse (as 's' there stands for "signed", not "single"). While there also correct the 3rd operand for the AVX512_4VNNIW entries: Only the memory form is allowed (just like for AVX512_4FMAPS, where the correct type is already in use).
2022-10-17x86: fold AVX512-VNNI disassembler entries with AVX-VNNI onesJan Beulich3-15/+22
Make %XV also print the separating blank in the VEX case, while making it do nothing for EVEX-encoded insns. This way the AVX-VNNI entries can be re-used for AVX512-VNNI, at the same time fixing the lack of EVEX.W decoding. For the AVX-VNNI ones further make sure only VEX.66 forms are actually decoded.
2022-10-16PowerPC se_rfmci and VLE, SPE2 and LSP insns with -manyAlan Modra2-1/+9
I noticed recently that se_rfmci, a VLE mode instruction, was being accepted by non-VLE cpus, and also that se_rfmci by itself in a section did not cause SHF_PPC_VLE to be set. ie. both testcases added by this patch fail without the changes to tc-ppc.c here. Also, VLE, SPE2 and LSP insns were not accepted by the assembler with -many nor were SPE2 and LSP being disassembled with -Many. gas/ * config/tc-ppc.c (ppc_setup_opcodes): Wrap long lines. Add vle_opcodes when PPC_OPCODE_VLE or PPC_OPCODE_ANY. Simplify disassembler index segment checks. Add LSP and SPE2 opcodes when PPC_OPCODE_ANY too. (md_assemble): Correct logic adding PPC_APUINFO_VLE and SHF_PPC_VLE. * testsuite/gas/ppc/se_rfmci.s * testsuite/gas/ppc/se_rfmci.d, * testsuite/gas/ppc/se_rfmci_bad.d: New tests. * testsuite/gas/ppc/ppc.exp: Run them. opcodes/ * ppc-dis.c (print_insn_powerpc): Disassemble SPE2 and LSP insn when -Many. * ppc-opc.c (vle_opcodes <se_rfmci>): Comment.
2022-10-14PowerPC SPE disassembly and testsAlan Modra1-2/+2
Where sub and subf forms of an instruction exist we generally disassemble to the extended insn sub form rather than the underlying machine subf instruction. Do so for SPE evsubw and evsubiw too. spe_ambiguous.d always was a bit too optimistic. There is no sensible way to disassemble identical bytes back to different and original source. Instead change the test to check -Mraw results. gas/ * testsuite/gas/ppc/ppc.exp: Run spe_ambiguous test. * testsuite/gas/ppc/spe.d: Expect evsubw and evsubiw rather than evsubfw and evsubifw. * testsuite/gas/ppc/spe_ambiguous.s: Test evnor form equivalent to evnot. * testsuite/gas/ppc/spe_ambiguous.d: Test Mraw. opcodes/ * ppc-opc.c (powerpc_opcodes): Move evsubw before evsubfw and evsubiw before evsubifw and mark EXT.
2022-10-14e200 LSP supportAlan Modra2-337/+411
It has bothered me for a long time that we have disabled LSP (and SPE) tests. Also the LSP test comment indicating there is something wrong with get_powerpc_dialect. I don't think there is. Decoding of a VLE instruction depends on whether the processor is in VLE mode (some processors support both VLE and standard PPC) which we flag per section with SHF_PPC_VLE for decoding when disassembling. Background: Some versions of powerpc e200 have "Lightweight Signal Processing" support, examples being e200z215 and e200z425. As far as I can tell, LSP and SPE are mutually exclusive. This seems to be borne out by insn encoding, for example LSP "zvaddih" and SPE "evaddw" have the same encoding. So none of the processor descriptions in ppc_opts ought to have both PPC_OPCODE_LSP and PPC_OPCODE_SPE/2, if we want disassembly to work. I also could not find anything to suggest that the LSP insns are enabled only in VLE mode, which means the LSP insns should not be in vle_opcodes. Fix all this by moving the LSP insns to their own table, and add a new e200z2 cpu entry with LSP support, removing LSP from -me200z4 and from -mvle. (Yes, I know, as I said above some of the e200z4 processors have LSP. Others have SPE. It's hard to choose good options. Think of z2 as meaning earlier, z4 as later.) Also add -mlsp to allow adding the LSP insn set. include/ * opcode/ppc.h (lsp_opcodes, lsp_num_opcodes): Declare. (LSP_OP_TO_SEG): Define. binutils/ * doc/binutils.texi: Update ppc docs. gas/ * config/tc-ppc.c (ppc_setup_opcodes): Add lsp opcodes to ppc_hash. * doc/c-ppc.texi: Document e200 and lsp. * testsuite/gas/ppc/lsp-checks.d: Assemble with -me200z2. * testsuite/gas/ppc/lsp.d: Likewise, disassembly too. * testsuite/gas/ppc/ppc.exp: Don't xfail lsp test. opcodes/ * ppc-dis.c (ppc_opts): Add e200z2 and lsp. Don't set PPC_OPCODE_LSP for e200z4 or vle. (ppc_parse_cpu): Mutually exclude LSP and SPE. (LSP_OPCD_SEGS): Define. (lsp_opcd_indices): New array. (disassemble_init_powerpc): Init lsp_opcd_indices. (lookup_lsp): New function. (print_insn_powerpc): Call it. * ppc-opc.c: Include libiberty.h for ARRAY_SIZE and use throughout. (vle_opcodes): Move LSP opcodes to.. (lsp_opcodes): ..here, and sort. (lsp_num_opcodes): New.
2022-10-14opcodes/riscv-dis.c: Remove last_map_stateTsukasa OI1-3/+0
Before changing the core disassembler, we take care of minor code clarity issues and improve readability. This commit removes unused variable last_map_state (set by the print_insn_riscv function but not read anywhere else). opcodes/ChangeLog: * riscv-dis.c (last_map_state): Remove. (print_insn_riscv): Remove setting last_map_state.
2022-10-14opcodes/riscv-dis.c: Make XLEN variable staticTsukasa OI1-1/+1
Before changing the core disassembler, we take care of minor code clarity issues and improve readability. Since xlen variable is not (and should not) used outside riscv-dis.c, this commit makes this variable static. opcodes/ChangeLog: * riscv-dis.c (xlen): Make this variable static.
2022-10-14opcodes/riscv-dis.c: Use bool type whenever possibleTsukasa OI1-5/+5
Before changing the core disassembler, we take care of minor code clarity issues and improve readability. This commit replaces uses of int with bool whenever possible. opcodes/ChangeLog: * riscv-dis.c (no_aliases) Change type to bool. (set_default_riscv_dis_options): Use boolean. (parse_riscv_dis_option_without_args): Likewise. (riscv_disassemble_insn): Use boolean keywords.
2022-10-14opcodes/riscv-dis.c: Tidying with spacingTsukasa OI1-1/+1
Before changing the core disassembler, we take care of minor code clarity issues and improve readability. This commit takes care of improper spacing for code clarity. opcodes/ChangeLog: * riscv-dis.c (riscv_disassemble_insn): Tidying with spacing.
2022-10-14opcodes/riscv-dis.c: Tidying with comments/clarityTsukasa OI1-4/+21
Before changing the core disassembler, we take care of minor code clarity issues and improve readability. First, we need to clarify the roles of variables and code portions. opcodes/ChangeLog: * riscv-dis.c (xlen): Move before default_isa_spec. Add comment. (default_isa_spec, default_priv_spec): Add comment. (riscv_gpr_names, riscv_fpr_names): Likewise. (parse_riscv_dis_option_without_args): Likewise. (parse_riscv_dis_option, parse_riscv_dis_options): Likewise. (maybe_print_address): Likewise. (riscv_disassemble_insn): Fix comment about the Zfinx "extension". Add comment about the riscv_multi_subset_supports call.
2022-10-14RISC-V: Move standard hints before all instructionsTsukasa OI1-4/+8
Because all standard hints must be placed before corresponding instruction for the disassembler, they may taint basic RVI instruction section. This commit moves all standard hints before all basic RVI instructions to improve maintainability. opcodes/ChangeLog: * riscv-opc.c (riscv_opcodes): Move all standard hints before all standard instructions.
2022-10-14RISC-V: Move certain arrays to riscv-opc.cTsukasa OI1-0/+13
This is a part of small tidying (declare tables in riscv-opc.c). include/ChangeLog: * opcode/riscv.h (riscv_rm, riscv_pred_succ): Move declarations to opcodes/riscv-opc.c. New non-static definitions. opcodes/ChangeLog: * riscv-opc.c (riscv_rm, riscv_pred_succ): Move from include/opcode/riscv.h. Add description.
2022-10-06RISC-V: Print XTheadMemPair literal as "immediate"Tsukasa OI1-1/+1
The operand type "Xl(...)" denotes that (...) is a literal. Specifically, they are intended to be a constant immediate value. This commit prints "Xl(...)" operand with dis_style_immediate style, not dis_style_text. opcodes/ChangeLog: * riscv-dis.c (print_insn_args): Use dis_style_immediate on the constant literal of the "Xl..." operand.
2022-10-06RISC-V: Fix T-Head immediate types on printingTsukasa OI1-4/+4
This commit fixes two minor typing-related issues for T-Head immediate operands. 1. A signed type must be specified when printing with %i. 2. unsigned/signed int is not portable enough for max 32-bit immediates. Instead, we should use unsigned/signed long. The format string is changed accordingly. opcodes/ChangeLog: * riscv-dis.c (print_insn_args): Fix T-Head immediate types on printing.
2022-10-06RISC-V: Print comma and tabs as the "text" styleTsukasa OI1-11/+20
On the RISC-V disassembler, some separators have non-text style when printed with another word with another style. This commit splits those, making sure that those comma and tabs are printed with the "text" style. opcodes/ChangeLog: * riscv-dis.c (print_insn_args): Split and print the comma as text. (riscv_disassemble_insn): Split and print tabs as text. (riscv_disassemble_data): Likewise.
2022-10-06RISC-V: Optimize riscv_disassemble_data printfTsukasa OI1-6/+4
This commit makes types of printf arguments on riscv_disassemble_data as small as possible (as long as we can preserve the portability) to reduce the cost of printf (especially on 32-bit host). opcodes/ChangeLog: * riscv-dis.c (riscv_disassemble_data): Use smallest possible type to printing data.
2022-10-06RISC-V: Fix printf argument types corresponding %xTsukasa OI1-7/+7
"%x" format specifier requires unsigned type, not int. This commit fixes this issue on the RISC-V disassembler. opcodes/ChangeLog: * riscv-dis.c (print_insn_args): Fix printf argument types where the format specifier is "%x".
2022-10-06RISC-V: Fix immediates to have "immediate" styleTsukasa OI1-5/+5
This commit fixes certain print calls on immediate operands to have dis_style_immediate. opcodes/ChangeLog: * riscv-dis.c (print_insn_args): Fix immediates to have "immediate" style. (riscv_disassemble_data): Likewise.
2022-10-05Arm64: support CLEARBHB aliasJan Beulich4-1576/+1579
While the Arm v8 ARM (rev I-a) still doesn't mention this alias, it is (typically via a macro) already in use in kernels and alike.
2022-10-04RISC-V: Fix buffer overflow on print_insn_riscvTsukasa OI1-1/+1
Because riscv_insn_length started to support instructions up to 176-bit, we need to increase packet buffer size to 176-bit in size. include/ChangeLog: * opcode/riscv.h (RISCV_MAX_INSN_LEN): Max instruction length for use in buffer size. opcodes/ChangeLog: * riscv-dis.c (print_insn_riscv): Increase buffer size for max 176-bit length instructions.
2022-10-04RISC-V: Renamed INSN_CLASS for floating point in integer extensions.Nelson Chu1-222/+222
Just added suffix _INX for those INSN_CLASS should be enough to represent their fpr can be replaced by gpr.
2022-10-04opcodes/riscv: style csr names as registersAndrew Burgess1-1/+2
While reviewing another patch I noticed that RISC-V CSR names are given the text style, not the register style. This patch fixes this mistake.
2022-10-03RISC-V: Move supervisor instructions after all unprivileged onesTsukasa OI1-32/+32
This location of supervisor instructions is out of place (because many other privileged instructions are located at the tail but after the supervisor instructions, we have many unprivileged instructions including bit manipulation / crypto / vector instructions). Not only that, this is harmful to implement pseudoinstructions in the latest 'P'-extension proposal (CLROV and RDOV). This commit moves supervisor instructions after all unprivileged instructions. opcodes/ChangeLog: * riscv-opc.c (riscv_opcodes): Adjust indents. Move supervisor instructions after all unprivileged instructions.
2022-09-30RISC-V: Relax "fmv.[sdq]" requirementsTsukasa OI1-3/+3
This commit relaxes requirements to "fmv.s" instructions from 'F' to ('F' or 'Zfinx'). The same applies to "fmv.d" and "fmv.q". Note that 'Zhinx' extension already contains "fmv.h" instruction (as well as 'Zfh'). gas/ChangeLog: * testsuite/gas/riscv/zfinx.s: Add "fmv.s" instruction. * testsuite/gas/riscv/zfinx.d: Likewise. * testsuite/gas/riscv/zdinx.s: Add "fmv.d" instruction. * testsuite/gas/riscv/zdinx.d: Likewise. * testsuite/gas/riscv/zqinx.d: Add "fmv.q" instruction. * testsuite/gas/riscv/zqinx.s: Likewise. opcodes/ChangeLog: * riscv-opc.c (riscv_opcodes): Relax requirements to "fmv.[sdq]" instructions to support those in 'Zfinx'/'Zdinx'/'Zqinx'.
2022-09-30RISC-V: fix build after "Add support for arbitrary immediate encoding formats"Jan Beulich1-2/+2
Pre- and post-increment/decrement are side effects, the behavior of which is undefined when combined with passing an address of the accessed variable in the same function invocation. There's no need for the increments here - simply adding 1 achieves the intended effect without triggering compiler diagnostics (which are fatal with -Werror).
2022-09-30RISC-V: drop stray INSN_ALIAS flagsJan Beulich1-3/+3
FENCE.TSO isn't an alias. ZIP and UNZIP in the long run likely are, but presently they aren't. This fixes disassembly of these insns with -Mno-aliases.
2022-09-30RISC-V: re-arrange opcode table for consistent alias handlingJan Beulich1-38/+38
For disassembly to pick up aliases in favor of underlying insns (helping readability in the common case), the aliases need to come ahead of the "base" insns. Slightly more code movement is needed because of insns with the same name needing to stay next to each other. Note that the "rorw" alias entry also has the missing INSN_ALIAS added here. Clone a few testcases to exercise -Mno-aliases some more, better covering the differences between the default and that disassembly mode.
2022-09-30x86: correct build dependencies in opcodes/Jan Beulich2-12/+16
With the command in the rule merely being "echo", i386-tbl.h won't be rebuilt if missing, when at the same time i386-init.h is present and up-to-date. Use a pattern rule instead to express the multiple targets correctly (the &: rule separator is supported only by GNU make 4.3 and newer). Note that now, for the opposite case to work (i386-tbl.h is up-to-date but i386-init.h is missing), i386-init.h also needs mentioning as a dependency somewhere: Add a fake dependency for i386-opc.lo ("fake" because i386-opc.c doesn't include that header). At the same time use $(AM_V_GEN) in the actual rule, replacing the earlier (open-coded) "echo". And while there also drop a duplicate dependency of i386-gen.o on i386-opc.h.
2022-09-30x86/Intel: restrict suffix derivationJan Beulich4-7481/+7463
While in some cases deriving an AT&T-style suffix from an Intel syntax memory operand size specifier is necessary, in many cases this is not only pointless, but has led to the introduction of various workarounds: Excessive use of IgnoreSize and NoRex64 as well as the ToDword and ToQword attributes. Suppress suffix derivation when we can clearly tell that the memory operand's size isn't going to be needed to infer the possible need for the low byte/word opcode bit or an operand size prefix (0x66 or REX.W). As a result ToDword and ToQword can be dropped entirely, plus a fair number of IgnoreSize and NoRex64 can also be got rid of. Note that IgnoreSize needs to remain on legacy encoded SIMD insns with GPR operand, to avoid emitting an operand size prefix in 16-bit mode. (Since 16-bit code using SIMD insns isn't well tested, clone an existing testcase just enough to cover a few insns which are potentially problematic but are being touched here.) Note that while folding the VCVT{,T}S{S,D}2SI templates, VCVT{,T}SH2SI isn't included there. This is to fulfill the request of not allowing L and Q suffixes there, despite the inconsistency with VCVT{,T}S{S,D}2SI.
2022-09-30PR29626, Segfault when disassembling ARM codeAlan Modra1-63/+61
PR 29626 * arm-dis.c (mapping_symbol_for_insn): Return false on zero symtab_size. Delete later symtab_size test.
2022-09-23RISC-V: Add Zawrs ISA extension supportChristoph Müllner1-0/+4
This patch adds support for the Zawrs ISA extension ("wrs.nto" and "wrs.sto" instructions). The specification can be found here: https://github.com/riscv/riscv-zawrs/blob/main/zawrs.adoc Signed-off-by: Christoph Müllner <christoph.muellner@vrull.eu>
2022-09-22RISC-V: Add T-Head MemPair vendor extensionChristoph Müllner1-0/+24
T-Head has a range of vendor-specific instructions. Therefore it makes sense to group them into smaller chunks in form of vendor extensions. This patch adds the XTheadMemPair extension, a collection of T-Head specific two-GP-register memory operations. The 'th' prefix and the "XTheadMemPair" extension are documented in a PR for the RISC-V toolchain conventions ([1]). [1] https://github.com/riscv-non-isa/riscv-toolchain-conventions/pull/19 Co-developed-by: Lifang Xia <lifang_xia@linux.alibaba.com> Signed-off-by: Christoph Müllner <christoph.muellner@vrull.eu>
2022-09-22RISC-V: Add support for literal instruction argumentsChristoph Müllner1-0/+9
This patch introduces support for arbitrary literal instruction arguments, that are not encoded in the opcode. A typical use case for this feature would be an instruction that applies an implicit shift by a constant value on an immediate (that is a real operand). With this patch it is possible to make this shift visible in the dissasembly and support such artificial parameter as part of the asssembly code. Co-developed-by: Lifang Xia <lifang_xia@linux.alibaba.com> Signed-off-by: Christoph Müllner <christoph.muellner@vrull.eu>
2022-09-22RISC-V: Add T-Head MemIdx vendor extensionChristoph Müllner1-0/+60
T-Head has a range of vendor-specific instructions. Therefore it makes sense to group them into smaller chunks in form of vendor extensions. This patch adds the XTheadMemIdx extension, a collection of T-Head specific GPR memory access instructions. The 'th' prefix and the "XTheadMemIdx" extension are documented in a PR for the RISC-V toolchain conventions ([1]). In total XTheadCmo introduces the following 44 instructions (BU,HU,WU only for loads (zero-extend instead of sign-extend)): * {L,S}{D,W,WU,H,HU,B,BU}{IA,IB} rd, rs1, imm5, imm2 * {L,S}R{D,W,WU,H,HU,B,BU} rd, rs1, rs2, imm2 * {L,S}UR{D,W,WU,H,HU,B,BU} rd, rs1, rs2, imm2 [1] https://github.com/riscv-non-isa/riscv-toolchain-conventions/pull/19 Co-developed-by: Lifang Xia <lifang_xia@linux.alibaba.com> Signed-off-by: Christoph Müllner <christoph.muellner@vrull.eu>
2022-09-22RISC-V: Add T-Head FMemIdx vendor extensionChristoph Müllner1-0/+10
T-Head has a range of vendor-specific instructions. Therefore it makes sense to group them into smaller chunks in form of vendor extensions. This patch adds the XTheadFMemIdx extension, a collection of T-Head-specific floating-point memory access instructions. The 'th' prefix and the "XTheadFMemIdx" extension are documented in a PR for the RISC-V toolchain conventions ([1]). [1] https://github.com/riscv-non-isa/riscv-toolchain-conventions/pull/19 Co-developed-by: Lifang Xia <lifang_xia@linux.alibaba.com> Signed-off-by: Christoph Müllner <christoph.muellner@vrull.eu>
2022-09-22RISC-V: Add T-Head MAC vendor extensionChristoph Müllner1-0/+8
T-Head has a range of vendor-specific instructions. Therefore it makes sense to group them into smaller chunks in form of vendor extensions. This patch adds the XTheadMac extension, a collection of T-Head-specific multiply-accumulate instructions. The 'th' prefix and the "XTheadMac" extension are documented in a PR for the RISC-V toolchain conventions ([1]). [1] https://github.com/riscv-non-isa/riscv-toolchain-conventions/pull/19 Co-developed-by: Lifang Xia <lifang_xia@linux.alibaba.com> Signed-off-by: Christoph Müllner <christoph.muellner@vrull.eu>
2022-09-22RISC-V: Add T-Head CondMov vendor extensionChristoph Müllner1-0/+4
T-Head has a range of vendor-specific instructions. Therefore it makes sense to group them into smaller chunks in form of vendor extensions. This patch adds the XTheadCondMov extension, a collection of T-Head-specific conditional move instructions. The 'th' prefix and the "XTheadCondMov" extension are documented in a PR for the RISC-V toolchain conventions ([1]). [1] https://github.com/riscv-non-isa/riscv-toolchain-conventions/pull/19 Co-developed-by: Lifang Xia <lifang_xia@linux.alibaba.com> Signed-off-by: Christoph Müllner <christoph.muellner@vrull.eu>
2022-09-22RISC-V: Add T-Head Bitmanip vendor extensionChristoph Müllner1-0/+17
T-Head has a range of vendor-specific instructions. Therefore it makes sense to group them into smaller chunks in form of vendor extensions. This patch adds the XThead{Ba,Bb,Bs} extensions, a collection of T-Head-specific bitmanipulation instructions. The 'th' prefix and the "XThead{Ba,Bb,Bs}" extension are documented in a PR for the RISC-V toolchain conventions ([1]). [1] https://github.com/riscv-non-isa/riscv-toolchain-conventions/pull/19 Co-developed-by: Lifang Xia <lifang_xia@linux.alibaba.com> Signed-off-by: Christoph Müllner <christoph.muellner@vrull.eu>
2022-09-22RISC-V: Add support for arbitrary immediate encoding formatsChristoph Müllner1-0/+34
This patch introduces support for arbitrary signed or unsigned immediate encoding formats. The formats have the form "XsN@S" and "XuN@S" with N being the number of bits and S the LSB position. For example an immediate field of 5 bytes that encodes a signed value and is stored in the bits 24-20 of the instruction word can use the format specifier "Xs5@20". Co-developed-by: Lifang Xia <lifang_xia@linux.alibaba.com> Signed-off-by: Christoph Müllner <christoph.muellner@vrull.eu>
2022-09-22RISC-V: Add T-Head SYNC vendor extensionChristoph Müllner1-0/+7
T-Head has a range of vendor-specific instructions. Therefore it makes sense to group them into smaller chunks in form of vendor extensions. This patch adds the XTheadSync extension, a collection of T-Head-specific multi-processor synchronization instructions. The 'th' prefix and the "XTheadSync" extension are documented in a PR for the RISC-V toolchain conventions ([1]). [1] https://github.com/riscv-non-isa/riscv-toolchain-conventions/pull/19 Co-developed-by: Lifang Xia <lifang_xia@linux.alibaba.com> Signed-off-by: Christoph Müllner <christoph.muellner@vrull.eu>
2022-09-22RISC-V: Add T-Head CMO vendor extensionChristoph Müllner1-0/+25
T-Head has a range of vendor-specific instructions. Therefore it makes sense to group them into smaller chunks in form of vendor extensions. This patch adds the XTheadCmo extension, a collection of T-Head specific cache management operations. The 'th' prefix and the "XTheadCmo" extension are documented in a PR for the RISC-V toolchain conventions ([1]). In total XTheadCmo introduces the following 21 instructions: * DCACHE.{C,CI,I}ALL * DCACHE.{C,CI,I}{PA,VA,SW} rs1 * DCACHE.C{PAL1,VAL1} rs1 * ICACHE.I{ALL,ALLS} * ICACHE.I{PA,VA} rs1 * L2CACHE.{C,CI,I}ALL Contrary to Zicbom, the XTheadCmo instructions don't have a constant displacement, therefore we have a different syntax for the arguments. To clarify this is intended behaviour, there is a set of negative test for Zicbom-style arguments in x-thead-cmo-fail.s. [1] https://github.com/riscv-non-isa/riscv-toolchain-conventions/pull/19 v2: - Add missing DECLARE_INSN() list - Fix ordering Co-developed-by: Lifang Xia <lifang_xia@linux.alibaba.com> Signed-off-by: Christoph Müllner <christoph.muellner@vrull.eu>
2022-09-22opcodes: SH fix bank register disassemble.Yoshinori Sato2-0/+7
* sh-dis.c (print_insn_sh): Enforce bit7 of LDC Rm,Rn_BANK and STC Rm_BANK,Rn is always 1.
2022-09-22RISC-V: Remove "b" operand type from disassemblerTsukasa OI1-1/+0
There are a few operand types not used by any RISC-V instructions. - Cx - Vf - Ve - [ - ] - b But most of them has a reasoning to keep them: - Cx : Same as "Ct" except it has a constraint to have rd == rs2 (similar to "Cw"). Although it hasn't used, its role is clear enough to implement a new instruction with this operand type. - Vf, Ve : Used by vector AMO instructions (not ratified and real instructions are not upstreamed yet). - [, ] : Unused tokenization symbols. Reserving them is not harmful and a vendor may use this symbol for special purposes. ... except "b". I could not have found any reference to this operand type except it works like the "s" operand type. Historically, it seems... it's just unused from the beginning. Its role is not clear either. On such cases, we should vacate this room for the new operand type with much clearer roles. opcodes/ChangeLog: * riscv-dis.c (print_insn_args): Remove 'b' operand type.
2022-09-14bfd: Stop using -Wstack-usage=262144 when built with ClangTsukasa OI1-0/+18
Some components of GNU Binutils will pass "-Wstack-usage=262144" when "GCC >= 5.0" is detected. However, Clang does not support "-Wstack-usage", despite that related configuration part in bfd/warning.m4 handles the latest Clang (15.0.0 as of this writing) as "GCC >= 5.0". The option "-Wstack-usage" was ignored when the first version of Clang is released but even this "ignoring" behavior is removed before Clang 4.0.0. So, if we give Clang "-Wstack-usage=262144", it generates a warning, making the build failure. This commit checks "__clang__" macro to prevent adding the option if the compiler is identified as Clang. bfd/ChangeLog: * warning.m4: Stop appending "-Wstack-usage=262144" option when compiled with Clang. * configure: Regenerate. binutils/ChangeLog: * configure: Regenerate. gas/ChangeLog: * configure: Regenerate. gold/ChangeLog: * configure: Regenerate. gprof/ChangeLog: * configure: Regenerate. ld/ChangeLog: * configure: Regenerate. opcodes/ChangeLog: * configure: Regenerate.
2022-09-14ubsan: arm-dis.c index out of boundsAlan Modra1-1/+1
We are way off in the weeds with this one, and will be printing <UNPREDICTABLE> for S > 10. * arm-dis.c (print_insn_cde): Wrap 'T' value.
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