| Age | Commit message (Expand) | Author | Files | Lines |
|---|
| 2017-05-12 | MIPS16/opcodes: Make the handling of BREAK and SDBBP consistent | Maciej W. Rozycki | 2 | -1/+9 |
| 2017-05-12 | MIPS/opcodes: Mark descriptive SYNC mnemonics as aliases | Maciej W. Rozycki | 3 | -14/+22 |
| 2017-05-10 | [ARC] Object attributes. | Claudiu Zissulescu | 4 | -29/+37 |
| 2017-05-04 | RISC-V: Fix disassemble for c.li, c.andi and c.addiw | Kito Cheng | 2 | -0/+5 |
| 2017-05-02 | RISC-V: Change CALL macro to use ra as the temporary address register | Michael Clark | 2 | -1/+6 |
| 2017-05-02 | MIPS16/opcodes: Keep the LSB of PC-relative offsets in disassembly | Maciej W. Rozycki | 2 | -3/+9 |
| 2017-05-02 | Fix value in comment of disassembled ARM type A opcodes. | Bernd Edlinger | 2 | -2/+6 |
| 2017-04-25 | [ARC] Enhance enter/leave mnemonics. | Claudiu Zissulescu | 4 | -4/+44 |
| 2017-04-25 | [ARC] Prefer NOP instead of MOV 0,0 | Claudiu Zissulescu | 2 | -3/+7 |
| 2017-04-25 | MIPS16/opcodes: Add `-M no-aliases' disassembler option help text | Maciej W. Rozycki | 2 | -0/+8 |
| 2017-04-25 | MIPS16/opcodes: Annotate instruction aliases | Maciej W. Rozycki | 2 | -5/+13 |
| 2017-04-24 | Fix snafu in aarch64 opcodes debugging statement. | Tamar Christina | 2 | -2/+7 |
| 2017-04-22 | PowerPC VLE insn set additions | Alan Modra | 2 | -7/+19 |
| 2017-04-21 | opcodes: mark SPARC RETT instructions as v6notv9. | Jose E. Marchesi | 2 | -7/+11 |
| 2017-04-21 | Fix detection of illegal AArch64 opcodes that resemble LD1R, LD2R, LD3R and L... | Nick Clifton | 2 | -8/+14 |
| 2017-04-13 | Regen cgen files | Alan Modra | 14 | -24/+53 |
| 2017-04-11 | Reorder PPC_OPCODE_* and set PPC_OPCODE_TMR for e6500 | Alan Modra | 3 | -6/+7 |
| 2017-04-11 | Bye bye PPC_OPCODE_HTM and -mhtm | Alan Modra | 3 | -9/+8 |
| 2017-04-11 | Bye Bye PPC_OPCODE_VSX3 | Alan Modra | 3 | -7/+8 |
| 2017-04-11 | Bye bye PPC_OPCODE_ALTIVEC2 | Alan Modra | 3 | -7/+13 |
| 2017-04-10 | Tidy ppc476 opcodes | Alan Modra | 3 | -43/+50 |
| 2017-04-10 | WebAssembly disassembler support | Pip Cet | 2 | -3/+7 |
| 2017-04-07 | Remove E6500 insns from PPC_OPCODE_ALTIVEC2 | Alan Modra | 2 | -25/+33 |
| 2017-04-06 | Add support for disassembling WebAssembly opcodes. | Pip Cet | 9 | -3/+569 |
| 2017-04-05 | -Wwrite-strings: Constify struct disassemble_info's disassembler_options field | Pedro Alves | 5 | -6/+13 |
| 2017-04-04 | RISC-V: Resurrect GP-relative disassembly hints | Palmer Dabbelt | 2 | -1/+6 |
| 2017-03-30 | Add support for the WebAssembly file format and the wasm32 ELF conversion to ... | Pip Cet | 4 | -158/+189 |
| 2017-03-29 | opcodes: sparc: support missing SPARC ASIs from UA2005, UA2007, OSA2011, & OS... | Jose E. Marchesi | 2 | -0/+34 |
| 2017-03-29 | PowerPC -Mraw disassembly | Alan Modra | 2 | -10/+26 |
| 2017-03-27 | PR21303, objdump doesn't show e200z4 insns | Alan Modra | 2 | -2/+19 |
| 2017-03-27 | Implement ARC NPS-400 Ultra Ip and Miscellaneous instructions. | Rinat Zelig | 3 | -350/+612 |
| 2017-03-21 | S/390: Remove vx2 facility flag | Andreas Krebbel | 3 | -146/+147 |
| 2017-03-21 | arc/nps400: Add cp16/cp32 instructions to opcodes library | Rinat Zelig | 3 | -3/+279 |
| 2017-03-17 | E6500 spr mnemonics | Alan Modra | 2 | -8/+15 |
| 2017-03-15 | RISC-V: Fix assembler for c.li, c.andi and c.addiw | Kito Cheng | 2 | -3/+9 |
| 2017-03-15 | RISC-V: Fix assembler for c.addi, rd can be x0 | Kito Cheng | 2 | -1/+5 |
| 2017-03-14 | RISC-V: Fix [dis]assembly of srai/srli | Andrew Waterman | 2 | -4/+11 |
| 2017-03-09 | X86: Add pseudo prefixes to control encoding | H.J. Lu | 5 | -73/+183 |
| 2017-03-09 | Use CpuCET on rdsspq | H.J. Lu | 3 | -2/+7 |
| 2017-03-08 | Update -maltivec and -mvsx options to only enable their oldest instructions. | Peter Bergner | 2 | -2/+7 |
| 2017-03-08 | Add support for the new 'lnia' extended mnemonic. | Peter Bergner | 2 | -0/+7 |
| 2017-03-06 | Add support for Intel CET instructions | H.J. Lu | 7 | -334/+681 |
| 2017-03-06 | Don't decode powerpc insns with invalid fields | Alan Modra | 2 | -49/+168 |
| 2017-02-28 | GDB: Add support for the new set/show disassembler-options commands. | Peter Bergner | 6 | -218/+394 |
| 2017-02-28 | x86: fix handling of 64-bit operand size VPCMPESTR{I,M} | Jan Beulich | 4 | -26/+170 |
| 2017-02-24 | [AArch64] Additional SVE instructions | Richard Sandiford | 11 | -2089/+2815 |
| 2017-02-24 | [AArch64] Add a "compnum" feature | Richard Sandiford | 2 | -6/+17 |
| 2017-02-24 | x86: also correctly support TEST opcode aliases | Jan Beulich | 2 | -2/+6 |
| 2017-02-23 | S/390: Add support for new cpu architecture - arch12. | Andreas Krebbel | 3 | -79/+311 |
| 2017-02-23 | opcodes,gas: associate SPARC ASIs with an architecture level. | Sheldon Lobo | 2 | -195/+196 |
