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2020-07-10x86: Add support for Intel AMX instructionsLili Cui8-14326/+15063
2020-07-08x86: various XOP insns lack L and/or W bit decodingJan Beulich2-123/+630
2020-07-08x86: FMA4 scalar insns ignore VEX.LJan Beulich4-101/+58
2020-07-08x86: re-work operand swapping for XOP shift/rotate insnsJan Beulich2-74/+32
2020-07-08x86: re-work operand handling for 5-operand XOP insnsJan Beulich2-194/+19
2020-07-08x86: re-work operand swapping for FMA4 and 4-operand XOP insnsJan Beulich2-65/+49
2020-07-07arc: Update vector instructions.Claudiu Zissulescu3-77/+103
2020-07-07x86: introduce %BW to avoid going through vex_w_table[]Jan Beulich4-77/+27
2020-07-06x86: adjust/correct VFRCZ{P,S}{S,D} decodingJan Beulich2-12/+48
2020-07-06x86: use %LW / %XW instead of going through vex_w_table[]Jan Beulich4-192/+77
2020-07-06x86: most VBROADCAST{F,I}{32,64}x* only accept memory operandsJan Beulich5-24/+90
2020-07-06x86: adjust/correct V*{F,I}{32x8,64x4}Jan Beulich2-14/+22
2020-07-06x86: drop EVEX table entries that can be made served by VEX onesJan Beulich5-165/+92
2020-07-06x86: AVX512 VPERM{D,Q,PS,PD} insns need to honor EVEX.L'LJan Beulich5-4/+47
2020-07-06x86: AVX512 extract/insert insns need to honor EVEX.L'LJan Beulich5-9/+76
2020-07-06x86: honor VEX.W for VCVT{PH2PS,PS2PH}Jan Beulich5-15/+27
2020-07-06x86: drop EVEX table entries that can be served by VEX onesJan Beulich5-713/+185
2020-07-06x86: replace EXqScalarS by EXqVexScalarSJan Beulich3-3/+8
2020-07-06x86: replace EX{d,q}Scalar by EXxmm_m{d,q}Jan Beulich3-47/+48
2020-07-06Fix spelling mistakes in some of the binutils sub-directories.Nick Clifton3-3/+9
2020-07-06Updated translations for various binutils sub-directoriesNick Clifton3-603/+634
2020-07-04Update version to 2.35.50 and regenerate filesNick Clifton3-122/+127
2020-07-04Add markers for binutils 2.35 branchNick Clifton1-0/+4
2020-07-02x86: Add SwapSourcesH.J. Lu5-3987/+4001
2020-06-30RISC-V: Support debug and float CSR as the unprivileged ones.Nelson Chu2-3/+11
2020-06-29C++ commentsAlan Modra8-10/+19
2020-06-26i386-opc.tbl: Add a blank lineH.J. Lu2-0/+5
2020-06-26x86: Correct VexSIB128 to VecSIB128H.J. Lu2-29/+29
2020-06-26x86: Rename VecSIB to SIB for Intel AMXH.J. Lu4-85/+106
2020-06-26x86: make I disassembler macro available for new useJan Beulich2-13/+17
2020-06-26x86: fix processing of -M disassembler optionJan Beulich2-3/+8
2020-06-25x86: make J disassembler macro available for new useJan Beulich2-12/+13
2020-06-25x86: drop left-over 4-way alternative disassembler templatesJan Beulich2-2/+6
2020-06-25x86: fix SYSRET disassembly, improve {,V}CVTSI2S{S,D} and PTWRITEJan Beulich2-6/+14
2020-06-22RISC-V: Report warning when linking the objects with different priv specs.Nelson Chu3-50/+6
2020-06-18x86: also test alternative VMGEXIT encodingJan Beulich2-0/+6
2020-06-17x86: Delete incorrect vmgexit entry in prefix_tableCui,Lili2-2/+4
2020-06-14x86: Correct xsusldtrk mnemonicH.J. Lu4-3/+10
2020-06-12RISC-V: Drop the privileged spec v1.9 support.Nelson Chu2-1/+4
2020-06-11[PATCH]: aarch64: Refactor representation of system registersAlex Coplan2-623/+471
2020-06-09i386-dis.c: Fix a typo in commentsH.J. Lu2-1/+5
2020-06-09x86: consistently print prefixes explicitly which are invalid with VEX etcJan Beulich2-13/+11
2020-06-09x86: fix {,V}MOV{L,H}PD disassemblyJan Beulich2-23/+48
2020-06-09x86: utilize X macro in EVEX decodingJan Beulich6-411/+127
2020-06-09x86: correct decoding of packed-FP-only AVX encodingsJan Beulich2-31/+39
2020-06-09x86: correct mis-named MOD_0F51 enumeratorJan Beulich2-3/+8
2020-06-08[PATCH] arm: Add DFB instruction for ARMv8-RAlex Coplan2-0/+13
2020-06-08x86: restrict use of register aliasesJan Beulich2-1/+5
2020-06-06Power10 tidiesAlan Modra2-0/+9
2020-06-05bpf stack smashing detectedAlan Modra2-5/+11
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