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AgeCommit message (Expand)AuthorFilesLines
2021-04-06Return symbol from symbol_at_address_funcAlan Modra3-23/+14
2021-04-05C99 opcodes configuryAlan Modra8-1248/+528
2021-04-01Remove strneq macro and use startswith.Martin Liska5-18/+9
2021-04-01PR27675, PowerPC missing extended mnemonic mfummcr2Alan Modra2-0/+7
2021-03-31Use bool in opcodesAlan Modra49-1573/+1591
2021-03-31Remove bfd_stdint.hAlan Modra12-11/+25
2021-03-30x86: drop seg_entryJan Beulich3-21/+17
2021-03-30x86: drop REGNAM_{AL,AX,EAX}Jan Beulich2-5/+4
2021-03-30x86: adjust st(<N>) parsingJan Beulich4-12/+13
2021-03-29x86: move some opcode table entriesJan Beulich3-489/+500
2021-03-29x86: VPSADBW's source operands are also commutativeJan Beulich3-6/+12
2021-03-29x86: fold SSE2AVX and their base MMX/SSE templatesJan Beulich4-924/+645
2021-03-29x86: undo Prefix_0X<nn> use in opcode tableJan Beulich3-375/+383
2021-03-29x86: shrink some struct insn_template fieldsJan Beulich2-4/+10
2021-03-29x86: derive opcode encoding space attribute from base opcodeJan Beulich3-1601/+1641
2021-03-29TRUE/FALSE simplificationAlan Modra5-54/+68
2021-03-29opcodes int vs bfd_boolean fixesAlan Modra3-10/+15
2021-03-26x86-64: don't accept supposedly disabled MOVQ formsJan Beulich3-4/+10
2021-03-25[NIOS2] Fix disassembly of br.n instruction.Hafiz Abid Qadeer2-1/+6
2021-03-25x86: flag bad S/G insn operand combinationsJan Beulich3-16/+86
2021-03-25x86: flag as bad AVX512 insns with EVEX.z set but EVEX.aaa clearJan Beulich2-0/+12
2021-03-25x86: fix AMD Zen3 insnsJan Beulich3-4/+66
2021-03-25PR27647 PowerPC extended conditional branch mnemonicsAlan Modra2-476/+486
2021-03-24x86: derive opcode length from opcode valueJan Beulich5-7463/+7468
2021-03-24x86: derive mandatory prefix attribute from base opcodeJan Beulich3-5027/+5028
2021-03-24x86: don't use opcode_length to identify pseudo prefixesJan Beulich5-34/+40
2021-03-23x86: re-number PREFIX_0X<nn>Jan Beulich3-153/+160
2021-03-23x86: re-order two fields of struct insn_templateJan Beulich4-12106/+12112
2021-03-23x86: split opcode prefix and opcode space representationJan Beulich5-9314/+9341
2021-03-22Add startswith function and use it instead of CONST_STRNEQ.Martin Liska11-68/+86
2021-03-16RISC-V : Support bitmanip-0.93 ZBA/ZBB/ZBC instructionsKuan-Lin Chen2-4/+53
2021-03-12aarch64: Add few missing system registersPrzemyslaw Wirkus2-0/+15
2021-03-12Re: x86: correct decoding of nop/reserved space (0f18 ... 0x1f)Alan Modra2-1/+5
2021-03-11x86: re-order logic in OP_XMM()Jan Beulich2-35/+35
2021-03-11x86: drop a few redundant EVEX-related checksJan Beulich2-4/+10
2021-03-11x86: remove stray uses of xmmq_modeJan Beulich2-4/+6
2021-03-10x86/Intel: correct AVX512 S/G disassemblyJan Beulich6-114/+42
2021-03-10x86: re-arrange enumerator and table entry orderJan Beulich2-77/+100
2021-03-10x86: reuse further VEX entries for EVEXJan Beulich6-98/+46
2021-03-10x86: reuse VEX entries for EVEX vperm{q,pd}Jan Beulich5-22/+20
2021-03-10x86: re-arrange order of decode for various EVEX opcodesJan Beulich7-439/+249
2021-03-10x86: re-arrange order of decode for various mask reg opcodesJan Beulich2-600/+427
2021-03-10x86: re-arrange order of decode for various VEX opcodesJan Beulich2-154/+104
2021-03-10x86: re-arrange order of decode for various legacy opcodesJan Beulich2-70/+43
2021-03-10x86: correct decoding of nop/reserved space (0f18 ... 0x1f)Jan Beulich2-48/+61
2021-03-09x86: fold some prefix related attributes into a single oneJan Beulich5-7503/+7517
2021-03-09x86-64: make SYSEXIT handling similar to SYSRET'sJan Beulich4-3/+10
2021-03-03x86: infer operand count of templatesJan Beulich3-3453/+3447
2021-02-19RISC-V: PR27158, fixed UJ/SB types and added CSS/CL/CS types for .insn.Nelson Chu3-32/+54
2021-02-18RISC-V: Add bfd/cpu-riscv.h to support all spec versions controlling.Nelson Chu3-95/+20
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