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2020-10-26CSKY: Fix and add some instructions for VDSPV1.Cooper Qu3-39/+231
gas/ * config/tc-csky.c (get_operand_value): Add handler for OPRND_TYPE_IMM5b_VSH and OPRND_TYPE_VREG_WITH_INDEX. * testsuite/gas/csky/csky_vdsp.d : Fix the disassembling for vector register. opcodes/ * csky-dis.c (csky_output_operand): Add handler for OPRND_TYPE_IMM5b_VSH and OPRND_TYPE_VREG_WITH_INDEX. * csky-opc.h (OPRND_TYPE_VREG_WITH_INDEX): New enum. (OPRND_TYPE_IMM5b_VSH): New enum. (csky_v2_opcodes): Fix and add some instructions for VDSPV1. Change-Id: Ia5675d7b716fe5c331e6121ad8f83061ef6454bb
2020-10-26Change avxvnni disassembler output from {vex3} to {vex}Cui,Lili2-1/+4
gas/ * testsuite/gas/i386/avx-vnni.d: Change psuedo prefix from {vex3} to {vex} * testsuite/gas/i386/x86-64-avx-vnni.d: Likewise. opcodes/ * i386-dis.c: Change "XV" to print "{vex}" pseudo prefix.
2020-10-22[PATCH][GAS][AArch64] Define BRBE system registersPrzemyslaw Wirkus1-0/+106
This patch introduces BRBE (Branch Record Buffer Extension) system registers. Note: as this is register only extension we do not want to hide these registers behind -march flag going forward (they should be enabled by default). gas/ChangeLog: 2020-10-08 Przemyslaw Wirkus <przemyslaw.wirkus@arm.com> * NEWS: Docs update. * testsuite/gas/aarch64/brbe-invalid.d: New test. * testsuite/gas/aarch64/brbe-invalid.l: New test. * testsuite/gas/aarch64/brbe-invalid.s: New test. * testsuite/gas/aarch64/brbe.d: New test. * testsuite/gas/aarch64/brbe.s: New test. opcodes/ChangeLog: 2020-10-08 Przemyslaw Wirkus <przemyslaw.wirkus@arm.com> * aarch64-opc.c: Add BRBE system registers.
2020-10-22aarch64: Define CSRE system registersPrzemyslaw Wirkus1-0/+13
This patch introduces CSRE (Call Stack Recorder Extension) system registers. Note: as this is register only extension we do not want to hide these registers behind -march flag going forward (they should be enabled by default). CSRE feature adds CSR PDEC (Decrements Call stack pointer by the size of a Call stack record) instruction. This instruction will be added in a following, separate patch. This change only adds CSRE system registers. gas/ChangeLog: 2020-10-08 Przemyslaw Wirkus <przemyslaw.wirkus@arm.com> * NEWS: Docs update. * testsuite/gas/aarch64/csre-invalid.d: New test. * testsuite/gas/aarch64/csre-invalid.l: New test. * testsuite/gas/aarch64/csre-invalid.s: New test. * testsuite/gas/aarch64/csre.d: New test. * testsuite/gas/aarch64/csre.s: New test. opcodes/ChangeLog: 2020-10-08 Przemyslaw Wirkus <przemyslaw.wirkus@arm.com> * aarch64-opc.c: New CSRE system registers defined.
2020-10-22opcodes/po/es.po: Remove the duplicated entryH.J. Lu2-8/+4
Remove the duplicated entry in opcodes/po/es.po: binutils-gdb/opcodes/po/es.po:749: duplicate message definition... binutils-gdb/opcodes/po/es.po:742: ...this is the location of the first definition * po/es.po: Remove the duplicated entry.
2020-10-22Fix printf formatting errors where "0x" is used as a prefix for a decimal ↵Dr. David Alan Gilbert2-2/+6
number. bfd * po/es.po: Fix printf format binutils * windmc.c: Fix printf format gas * config/tc-arc.c: Fix printf format opcodes * po/es.po: Fix printf format sim * arm/armos.c: Fix printf format * ppc/emul_netbsd.c: Fix printf format -- Dr. David Alan Gilbert / dgilbert@redhat.com / Manchester, UK
2020-10-20Add AMD znver3 processor supportGanesh Gopalasubramanian7-4213/+4494
gas/ * config/tc-i386.c (cpu_arch): Add CPU_ZNVER3_FLAGS flags. (i386_align_code): Add PROCESSOR_ZNVER cases. * doc/c-i386.texi: Add znver3, snp, invlpgb and tlbsync. * gas/i386/i386.exp: Add new znver3 test cases. * gas/i386/arch-14-znver3.d: New. * gas/i386/arch-14.d: New. * gas/i386/arch-14.s: New. * gas/i386/invlpgb.d: New. * gas/i386/invlpgb64.d: New. * gas/i386/invlpgb.s: New. * gas/i386/snp.d: New. * gas/i386/snp64.d: New. * gas/i386/snp.s: New. * gas/i386/tlbsync.d: New. * gas/i386/tlbsync.s: New. * gas/i386/x86-64-arch-4-znver3.d: New. * gas/i386/x86-64-arch-4.d: New. * gas/i386/x86-64-arch-4.s: New. opcodes/ * i386-dis.c (rm_table): Add tlbsync, snp, invlpgb. * i386-gen.c (cpu_flag_init): Add new CPU_INVLPGB_FLAGS, CPU_TLBSYNC_FLAGS, and CPU_SNP_FLAGS. Add CPU_ZNVER3_FLAGS. (cpu_flags): Add CpuINVLPGB, CpuTLBSYNC, CpuSNP. * i386-opc.h: Add CpuINVLPGB, CpuTLBSYNC, CpuSNP. * i386-opc.tbl: Add invlpgb, tlbsync, psmash, pvalidate, rmpupdate, rmpadjust. * i386-init.h: Re-generated. * i386-tbl.h: Re-generated.
2020-10-16Enhancement for avx-vnni patchCui,Lili6-11428/+11439
1. Rename CpuVEX_PREFIX to PseudoVexPrefix and move it from cpu_flags to opcode_modifiers. 2. Delete {vex2} invalid test. 3. Use VexW0 and VexVVVV in the AVX-VNNI instructions. gas/ * config/tc-i386.c: Move Pseudo Prefix check to match_template. * testsuite/gas/i386/avx-vnni-inval.l: New file. * testsuite/gas/i386/avx-vnni-inval.s: Likewise. * testsuite/gas/i386/avx-vnni.d: Delete invalid {vex2} test. * testsuite/gas/i386/avx-vnni.s: Likewise. * testsuite/gas/i386/i386.exp: Add AVX VNNI invalid tests. * testsuite/gas/i386/x86-64-avx-vnni-inval.l: New file. * testsuite/gas/i386/x86-64-avx-vnni-inval.s: Likewise. * testsuite/gas/i386/x86-64-avx-vnni.d: Delete invalid {vex2} test. * testsuite/gas/i386/x86-64-avx-vnni.s: Likewise. opcodes/ * i386-opc.tbl: Rename CpuVEX_PREFIX to PseudoVexPrefix and move it from cpu_flags to opcode_modifiers. Use VexW0 and VexVVVV in the AVX-VNNI instructions. * i386-gen.c: Likewise. * i386-opc.h: Likewise. * i386-opc.h: Likewise. * i386-init.h: Regenerated. * i386-tbl.h: Likewise.
2020-10-14x86: Support Intel AVX VNNIH.J. Lu7-4539/+4705
Intel AVX VNNI instructions are marked with CpuVEX_PREFIX. Without the pseudo {vex} prefix, mnemonics of Intel VNNI instructions are encoded with the EVEX prefix. The pseudo {vex} prefix can be used to encode mnemonics of Intel VNNI instructions with the VEX prefix. gas/ * NEWS: Add Intel AVX VNNI. * config/tc-i386.c (cpu_arch): Add .avx_vnni and noavx_vnni. (cpu_flags_match): Support CpuVEX_PREFIX. * doc/c-i386.texi: Document .avx_vnni, noavx_vnni and how to encode Intel VNNI instructions with VEX prefix. * testsuite/gas/i386/avx-vnni.d: New file. * testsuite/gas/i386/avx-vnni.s: Likewise. * testsuite/gas/i386/x86-64-avx-vnni.d: Likewise. * testsuite/gas/i386/x86-64-avx-vnni.s: Likewise. * testsuite/gas/i386/i386.exp: Run AVX VNNI tests. opcodes/ * i386-dis.c (PREFIX_VEX_0F3850): New. (PREFIX_VEX_0F3851): Likewise. (PREFIX_VEX_0F3852): Likewise. (PREFIX_VEX_0F3853): Likewise. (VEX_W_0F3850_P_2): Likewise. (VEX_W_0F3851_P_2): Likewise. (VEX_W_0F3852_P_2): Likewise. (VEX_W_0F3853_P_2): Likewise. (prefix_table): Add PREFIX_VEX_0F3850, PREFIX_VEX_0F3851, PREFIX_VEX_0F3852 and PREFIX_VEX_0F3853. (vex_table): Add VEX_W_0F3850_P_2, VEX_W_0F3851_P_2, VEX_W_0F3852_P_2 and VEX_W_0F3853_P_2. (putop): Add support for "XV" to print "{vex3}" pseudo prefix. * i386-gen.c (cpu_flag_init): Clear the CpuAVX_VNNI bit in CPU_UNKNOWN_FLAGS. Add CPU_AVX_VNNI_FLAGS and CPU_ANY_AVX_VNNI_FLAGS. (cpu_flags): Add CpuAVX_VNNI and CpuVEX_PREFIX. * i386-opc.h (CpuAVX_VNNI): New. (CpuVEX_PREFIX): Likewise. (i386_cpu_flags): Add cpuavx_vnni and cpuvex_prefix. * i386-opc.tbl: Add Intel AVX VNNI instructions. * i386-init.h: Regenerated. * i386-tbl.h: Likewise.
2020-10-14x86: Add support for Intel HRESET instructionLili Cui7-4467/+4558
gas/ * NEWS: Add Intel HRESET. * config/tc-i386.c (cpu_arch): Add .hreset. (cpu_noarch): Likewise. * doc/c-i386.texi: Document .hreset, nohreset. * testsuite/gas/i386/i386.exp: Run HRESET tests. * testsuite/gas/i386/hreset.d: New file. * testsuite/gas/i386/x86-64-hreset.d: Likewise. * testsuite/gas/i386/hreset.s: Likewise. opcodes/ * i386-dis.c (PREFIX_0F3A0F): New. (MOD_0F3A0F_PREFIX_1): Likewise. (REG_0F3A0F_PREFIX_1_MOD_3): Likewise. (RM_0F3A0F_P_1_MOD_3_REG_0): Likewise. (prefix_table): Add PREFIX_0F3A0F. (mod_table): Add MOD_0F3A0F_PREFIX_1. (reg_table): Add REG_0F3A0F_PREFIX_1_MOD_3. (rm_table): Add RM_0F3A0F_P_1_MOD_3_REG_0. * i386-gen.c (cpu_flag_init): Add HRESET_FLAGS, CPU_ANY_HRESET_FLAGS. (cpu_flags): Add CpuHRESET. (output_i386_opcode): Allow 4 byte base_opcode. * i386-opc.h (enum): Add CpuHRESET. (i386_cpu_flags): Add cpuhreset. * i386-opc.tbl: Add Intel HRESET instruction. * i386-init.h: Regenerate. * i386-tbl.h: Likewise.
2020-10-14x86: Support Intel UINTRLili Cui7-4203/+8587
gas/ * NEWS: Add Intel UINTR. * config/tc-i386.c (cpu_arch): Add .uintr. (cpu_noarch): Likewise. * doc/c-i386.texi: Document .uintr and nouintr. * testsuite/gas/i386/i386.exp: Run UINTR tests. * testsuite/gas/i386/x86-64-uintr.d: Likewise. * testsuite/gas/i386/x86-64-uintr.s: Likewise. opcodes/ * i386-dis.c (enum): Add PREFIX_MOD_3_0F01_REG_5_RM_4, PREFIX_MOD_3_0F01_REG_5_RM_5, PREFIX_MOD_3_0F01_REG_5_RM_6, PREFIX_MOD_3_0F01_REG_5_RM_7, X86_64_0F01_REG_5_MOD_3_RM_4_PREFIX_1, X86_64_0F01_REG_5_MOD_3_RM_5_PREFIX_1, X86_64_0F01_REG_5_MOD_3_RM_6_PREFIX_1, X86_64_0F01_REG_5_MOD_3_RM_7_PREFIX_1, X86_64_0FC7_REG_6_MOD_3_PREFIX_1. (prefix_table): New instructions (see prefixes above). (rm_table): Likewise * i386-gen.c (cpu_flag_init): Add CPU_UINTR_FLAGS, CPU_ANY_UINTR_FLAGS. (cpu_flags): Add CpuUINTR. * i386-opc.h (enum): Add CpuUINTR. (i386_cpu_flags): Add cpuuintr. * i386-opc.tbl: Add UINTR insns. * i386-init.h: Regenerate. * i386-tbl.h: Likewise.
2020-10-14x86: Remove the prefix byte from non-VEX/EVEX base_opcodeH.J. Lu4-1077/+1136
Replace the prefix byte in non-VEX/EVEX base_opcode with PREFIX_0X66, PREFIX_0XF2 or PREFIX_0XF3. gas/ * config/tc-i386.c (load_insn_p): Check opcodeprefix == 0 for base_opcode == 0xfc7. (match_template): Likewise. (process_suffix): Check opcodeprefix == PREFIX_0XF2 for CRC32. (check_byte_reg): Likewise. (output_insn): Don't add the 0xf3 prefix twice for PadLock instructions. Don't add prefix from non-VEX/EVEX base_opcode. opcodes/ * i386-gen.c (process_i386_opcode_modifier): Return 1 for non-VEX/EVEX/prefix encoding. (output_i386_opcode): Fail if non-VEX/EVEX/prefix base_opcode has a prefix byte. * i386-opc.tbl: Replace the prefix byte in non-VEX/EVEX base_opcode with PREFIX_0X66, PREFIX_0XF2 or PREFIX_0XF3. * i386-tbl.h: Regenerated.
2020-10-13x86: Rename VexOpcode to OpcodePrefixH.J. Lu5-2149/+2180
Rename VexOpcode to OpcodePrefix so that OpcodePrefix can be used for regular encoding prefix. gas/ * config/tc-i386.c (build_vex_prefix): Replace vexopcode with opcodeprefix. (build_evex_prefix): Likewise. (is_any_vex_encoding): Don't check vexopcode. (output_insn): Handle opcodeprefix. opcodes/ * i386-gen.c (opcode_modifiers): Replace VexOpcode with OpcodePrefix. * i386-opc.h (VexOpcode): Renamed to ... (OpcodePrefix): This. (PREFIX_NONE): New. (PREFIX_0X66): Likewise. (PREFIX_0XF2): Likewise. (PREFIX_0XF3): Likewise. * i386-opc.tbl (Prefix_0X66): New. (Prefix_0XF2): Likewise. (Prefix_0XF3): Likewise. Replace VexOpcode= with OpcodePrefix=. Use Prefix_0X66 on xorpd. Use Prefix_0XF3 on cvtdq2pd. Use Prefix_0XF2 on cvtpd2dq. * i386-tbl.h: Regenerated.
2020-10-05Fix spelling mistakesSamanta Navarro4-5/+11
2020-10-05x86-64: Always display suffix for %LQ in 64bitH.J. Lu2-1/+6
In 64bit, assembler generates a warning for "sysret": $ echo sysret | as --64 -o x.o - {standard input}: Assembler messages: {standard input}:1: Warning: no instruction mnemonic suffix given and no register operands; using default for `sysret' Always display suffix for %LQ in 64bit to display "sysretl". gas/ PR binutils/26704 * testsuite/gas/i386/noreg64-data16.d: Expect sysretl instead of sysret. * testsuite/gas/i386/noreg64.d: Likewise. * testsuite/gas/i386/x86-64-intel64.d: Likewise. * testsuite/gas/i386/x86-64-opcode.d: Likewise. opcodes/ PR binutils/26704 * i386-dis.c (putop): Always display suffix for %LQ in 64bit.
2020-10-05x86: Clear modrm if not neededH.J. Lu2-4/+15
The MODRM byte can be checked to display the instruction name only if the MODRM byte needed. Clear modrm if the MODRM byte isn't needed so that modrm field checks in putop like, modrm.mod == N with N != 0, can be done without checking need_modrm. gas/ PR binutils/26705 * testsuite/gas/i386/x86-64-suffix.s: Add "mov %rsp,%rbp" before sysretq. * testsuite/gas/i386/x86-64-suffix-intel.d: Updated. * testsuite/gas/i386/x86-64-suffix.d: Likewise. opcodes/ PR binutils/26705 * i386-dis.c (print_insn): Clear modrm if not needed. (putop): Check need_modrm for modrm.mod != 3. Don't check need_modrm for modrm.mod == 3.
2020-09-28This patch introduces ETMv4 (Embedded Trace Macrocell) system registers for ↵Przemyslaw Wirkus2-3/+236
the AArch64 architecture. gas * testsuite/gas/aarch64/etm-ro-invalid.d: New test. * testsuite/gas/aarch64/etm-ro-invalid.l: New test. * testsuite/gas/aarch64/etm-ro-invalid.s: New test. * testsuite/gas/aarch64/etm-ro.s: New test. * testsuite/gas/aarch64/etm-wo-invalid.d: New test. * testsuite/gas/aarch64/etm-wo-invalid.l: New test. * testsuite/gas/aarch64/etm-wo-invalid.s: New test. * testsuite/gas/aarch64/etm-wo.s: New test. * testsuite/gas/aarch64/etm.s: New test. * testsuite/gas/aarch64/sysreg.d: system register s2_1_c0_c3_0 disassembled now to trcstatr. opcodes * aarch64-opc.c: Added ETMv4 system registers TRCACATRn, TRCACVRn, TRCAUTHSTATUS, TRCAUXCTLR, TRCBBCTLR, TRCCCCTLR, TRCCIDCCTLR0, TRCCIDCCTLR1, TRCCIDCVRn, TRCCIDR0, TRCCIDR1, TRCCIDR2, TRCCIDR3, TRCCLAIMCLR, TRCCLAIMSET, TRCCNTCTLRn, TRCCNTRLDVRn, TRCCNTVRn, TRCCONFIGR, TRCDEVAFF0, TRCDEVAFF1, TRCDEVARCH, TRCDEVID, TRCDEVTYPE, TRCDVCMRn, TRCDVCVRn, TRCEVENTCTL0R, TRCEVENTCTL1R, TRCEXTINSELR, TRCIDR0, TRCIDR1, TRCIDR2, TRCIDR3, TRCIDR4, TRCIDR5, TRCIDR6, TRCIDR7, TRCIDR8, TRCIDR9, TRCIDR10, TRCIDR11, TRCIDR12, TRCIDR13, TRCIMSPEC0, TRCIMSPECn, TRCITCTRL, TRCLAR WOTRCLSR, TRCOSLAR WOTRCOSLSR, TRCPDCR, TRCPDSR, TRCPIDR0, TRCPIDR1, TRCPIDR2, TRCPIDR3, TRCPIDR4, TRCPIDR[5,6,7], TRCPRGCTLR, TRCP,CSELR, TRCQCTLR, TRCRSCTLRn, TRCSEQEVRn, TRCSEQRSTEVR, TRCSEQSTR, TRCSSCCRn, TRCSSCSRn, TRCSSPCICRn, TRCSTALLCTLR, TRCSTATR, TRCSYNCPR, TRCTRACEIDR, TRCTSCTLR, TRCVDARCCTLR, TRCVDCTLR, TRCVDSACCTLR, TRCVICTLR, TRCVIIECTLR, TRCVIPCSSCTLR, TRCVISSCTLR, TRCVMIDCCTLR0, TRCVMIDCCTLR1 and TRCVMIDCVRn.
2020-09-28This patch introduces ETE (Embedded Trace Extension) system registers for ↵Przemyslaw Wirkus2-0/+10
the AArch64 architecture. gas * testsuite/gas/aarch64/ete.d: New test. * testsuite/gas/aarch64/ete.s: New test. opcodes * aarch64-opc.c: Add ETE system registers TRCEXTINSELR<0-3> and TRCRSR.
2020-09-28This patch introduces TRBE (Trace Buffer Extension) system registers for the ↵Przemyslaw Wirkus2-0/+13
AArch64 architecture. gas * testsuite/gas/aarch64/trbe-invalid.d: New test. * testsuite/gas/aarch64/trbe-invalid.l: New test. * testsuite/gas/aarch64/trbe-invalid.s: New test. * testsuite/gas/aarch64/trbe.d: New test. * testsuite/gas/aarch64/trbe.s: New test. opcodes * aarch64-opc.c: Add TRBE system registers TRBIDR_EL1 , TRBBASER_EL1 , TRBLIMITR_EL1 , TRBMAR_EL1 , TRBPTR_EL1, TRBSR_EL1 and TRBTRG_EL1.
2020-09-26ubsan: opcodes/csky-opc.h:929 shift exponent 536870912Alan Modra3-28/+34
opcodes/ * csky-opc.h: Formatting. (GENERAL_REG_BANK): Correct spelling. Update use throughout file. (get_register_name): Mask arch with CSKY_ARCH_MASK for shift, and shift 1u. (get_register_number): Likewise. * csky-dis.c (get_gr_name, get_cr_name): Don't mask mach_flag. gas/ * config/tc-csky.c (parse_type_ctrlreg): Don't mask mach_flag for csky_get_control_regno. (csky_get_reg_val): Likewise when calling csky_get_general_regno.
2020-09-25Put together MOD_VEX_0F38* in i386-dis.c,Cui,Lili2-62/+67
There are 11 MOD_VEX_0F38* inserted in MOD_0F38* group, which should be placed in MOD_VEX_0F38* group. opcode/ PR 26654 *i386-dis.c (enum): Put MOD_VEX_0F38* together.
2020-09-24csky/opcodes: enclose if body in curly bracesAndrew Burgess2-2/+9
This commit: commit afdcafe89118cee761f9bf67ea1b1efc29311300 Date: Thu Sep 17 14:30:28 2020 +0800 CSKY: Add objdump option -M abi-names. cases the build of GDB (configured with --enabled-targets=all) to fail with this error: libtool: compile: gcc -DHAVE_CONFIG_H -I. -I../../src/opcodes -I. -I../../src/opcodes -I../bfd -I../../src/opcodes/../include -I../../src/opcodes/../bfd -W -Wall -Wstrict-prototypes -Wmissing-prototypes -Wshadow -Wstack-usage=262144 -Werror -O0 -g3 -D_GLIBCXX_DEBUG=1 -MT csky-dis.lo -MD -MP -MF .deps/csky-dis.Tpo -c ../../src/opcodes/csky-dis.c -o csky-dis.o ../../src/opcodes/csky-dis.c: In function 'csky_output_operand': ../../src/opcodes/csky-dis.c:849:7: error: this 'if' clause does not guard... [-Werror=misleading-indentation] 849 | if (IS_CSKY_V1 (mach_flag)) | ^~ ../../src/opcodes/csky-dis.c:851:2: note: ...this statement, but the latter is misleadingly indented as if it were guarded by the 'if' 851 | strcat (str, buf); | ^~~~~~ this commit adds { ... } around the if body to resolve this issue. opcodes/ChangeLog: * csky-dis.c (csky_output_operand): Enclose body of if in curly braces.
2020-09-24Add support for Intel TDX instructions.Cui,Lili7-4266/+4422
gas/ * NEWS: Add TDX. * config/tc-i386.c (cpu_arch): Add .tdx. (cpu_noarch): Likewise. * doc/c-i386.texi: Document tdx. * testsuite/gas/i386/i386.exp: Run tdx tests. * testsuite/gas/i386/tdx.d: Likewise. * testsuite/gas/i386/tdx.s: Likewise. * testsuite/gas/i386/x86-64-tdx.d: Likewise. * testsuite/gas/i386/x86-64-tdx.s: Likewise. opcodes/ * i386-dis.c (enum): Add PREFIX_0F01_REG_1_RM_5, PREFIX_0F01_REG_1_RM_6, PREFIX_0F01_REG_1_RM_7, X86_64_0F01_REG_1_RM_5_P_2, X86_64_0F01_REG_1_RM_6_P_2, X86_64_0F01_REG_1_RM_7_P_2. (prefix_table): Likewise. (x86_64_table): Likewise. (rm_table): Likewise. * i386-gen.c (cpu_flag_init): Add CPU_TDX_FLAGS and CPU_ANY_TDX_FLAGS. (cpu_flags): Add CpuTDX. * i386-opc.h (enum): Add CpuTDX. (i386_cpu_flags): Add cputdx. * i386-opc.tbl: Add TDX insns. * i386-init.h: Regenerate. * i386-tbl.h: Likewise.
2020-09-23CSKY: Add objdump option -M abi-names.Cooper Qu3-180/+531
Add option parser for disassembler, and refine the codes of parse register operand and disassemble register operand. While strengthen the operands legality check of some instructions. Co-Authored-By: Lifang Xia <lifang_xia@c-sky.com> gas/ * config/tc-csky.c (parse_type_ctrlreg): Use function csky_get_control_regno to operand. (csky_get_reg_val): Likewise. (is_reg_sp_with_bracket): Use function csky_get_reg_val to parse operand. (is_reg_sp): Refine. (is_oimm_within_range): Fix, report error when operand is not constant. (parse_type_cpreg): Refine. (parse_type_cpcreg): Refine. (get_operand_value): Add handle of OPRND_TYPE_IMM5b_LS. (md_assemble): Fix no error reporting somtimes when operands number are not fit. (csky_addc64): Refine. (csky_subc64): Refine. (csky_or64): Refine. (v1_work_fpu_fo): Refine. (v1_work_fpu_read): Refine. (v1_work_fpu_writed): Refine. (v1_work_fpu_readd): Refine. (v2_work_addc): New function, strengthen the operands legality check of addc. * gas/testsuite/gas/csky/all.d : Use register number format when disassemble register name by default. * gas/testsuite/gas/csky/cskyv2_all.d : Likewise. * gas/testsuite/gas/csky/trust.d: Likewise. * gas/testsuite/gas/csky/cskyv2_ck860.d : Fix. * gas/testsuite/gas/csky/trust.s : Fix. opcodes/ * csky-dis.c (using_abi): New. (parse_csky_dis_options): New function. (get_gr_name): New function. (get_cr_name): New function. (csky_output_operand): Use get_gr_name and get_cr_name to disassemble and add handle of OPRND_TYPE_IMM5b_LS. (print_insn_csky): Parse disassembler options. * opcodes/csky-opc.h (OPRND_TYPE_IMM5b_LS): New enum. (GENARAL_REG_BANK): Define. (REG_SUPPORT_ALL): Define. (REG_SUPPORT_ALL): New. (ASH): Define. (REG_SUPPORT_A): Define. (REG_SUPPORT_B): Define. (REG_SUPPORT_C): Define. (REG_SUPPORT_D): Define. (REG_SUPPORT_E): Define. (csky_abiv1_general_regs): New. (csky_abiv1_control_regs): New. (csky_abiv2_general_regs): New. (csky_abiv2_control_regs): New. (get_register_name): New function. (get_register_number): New function. (csky_get_general_reg_name): New function. (csky_get_general_regno): New function. (csky_get_control_reg_name): New function. (csky_get_control_regno): New function. (csky_v2_opcodes): Prefer two oprerans format for bclri and bseti, strengthen the operands legality check of addc, zext and sext.
2020-09-23Enable support to Intel Keylocker instructionsTerry Guo7-4183/+4507
gas/ * NEWS: Add Key Locker. * config/tc-i386.c (cpu_arch): Add .kl and .wide_kl. (cpu_noarch): Likewise. * doc/c-i386.texi: Document kl and wide_kl. * testsuite/gas/i386/i386.exp: Run keylocker tests. * testsuite/gas/i386/keylocker-intel.d: New test. * testsuite/gas/i386/keylocker.d: Likewise. * testsuite/gas/i386/keylocker.s: Likewise. * testsuite/gas/i386/x86-64-keylocker-intel.d: Likewise. * testsuite/gas/i386/x86-64-keylocker.d: Likewise. * testsuite/gas/i386/x86-64-keylocker.s: Likewise. * testsuite/gas/i386/x86-64-property-10.d: Likewise. * testsuite/gas/i386/property-10.d: Likewise. * testsuite/gas/i386/property-10.s: Likewise. opcodes/ * i386-dis.c (enum): Add REG_0F38D8_PREFIX_1, MOD_0F38FA_PREFIX_1, MOD_0F38FB_PREFIX_1, MOD_0F38DC_PREFIX_1, MOD_0F38DD_PREFIX_1, MOD_0F38DE_PREFIX_1, MOD_0F38DF_PREFIX_1, PREFIX_0F38D8, PREFIX_0F38FA, PREFIX_0F38FB. (reg_table): New instructions (see prefixes above). (prefix_table): Likewise. (three_byte_table): Likewise. (mod_table): Likewise * i386-gen.c (cpu_flag_init): Add CPU_KL_FLAGS, CPU_WIDE_KL_FLAGS, CPU_ANY_KL_FLAGS and CPU_ANY_WIDE_KL_FLAGS. (cpu_flags): Likewise. (operand_type_init): Likewise. * i386-opc.h (enum): Add CpuKL and CpuWide_KL. (i386_cpu_flags): Add cpukl and cpuwide_kl. * i386-opc.tbl: Add KL and WIDE_KL insns. * i386-init.h: Regenerate. * i386-tbl.h: Likewise.
2020-09-21rx-dis.c:103:3: suspicious concatenation of string literalsAlan Modra2-8/+16
* rx-dis.c (flag_names): Add missing comma. (register_names, flag_names, double_register_names), (double_register_high_names, double_register_low_names), (double_control_register_names, double_condition_names): Remove trailing commas.
2020-09-18bpf: xBPF SDIV, SMOD instructionsDavid Faust5-6/+194
Add gas and opcodes support for two xBPF-exclusive ALU operations: SDIV (signed division) and SMOD (signed modulo), and add tests for them in gas. cpu/ * bpf.cpu (insn-op-code-alu): Add SDIV and SMOD. (define-alu-insn-bin, daib): Take ISAs as an argument. (define-alu-instructions): Update calls to daib pmacro with ISAs; add sdiv and smod. gas/ * testsuite/gas/bpf/alu-xbpf.d: New file. * testsuite/gas/bpf/alu-xbpf.s: Likewise. * testsuite/gas/bpf/alu32-xbpf.d: Likewise. * testsuite/gas/bpf/alu32-xbpf.d: Likewise. * testuiste/gas/bpf/bpf.exp: Run new tests. opcodes/ * bpf-desc.c: Regenerate. * bpf-desc.h: Likewise. * bpf-opc.c: Likewise. * bpf-opc.h: Likewise.
2020-09-17opcodes/csky: return the default disassembler when there is no bfdAndrew Burgess2-15/+22
The disassembler function should return a valid disassembler function even when there is no BFD present. This is implied (I believe) by the comment in dis-asm.h which says the BFD may be NULL. Further, it makes sense when considering that the disassembler is used in GDB, and GDB may connect to a target and perform debugging even without a BFD being supplied. This commit makes the csky_get_disassembler function return the default disassembler configuration when no bfd is supplied, this is the same default configuration as is used when a BFD is supplied, but the BFD has no attributes section. Before the change configuring GDB with --enable-targets=all and running the tests gdb.base/all-architectures-2.exp results in many errors, but after this change there are no failures. opcodes/ChangeLog: * csky-dis.c (csky_get_disassembler): Don't return NULL when there is no BFD.
2020-09-16Tidy elf_symbol_fromAlan Modra2-1/+5
bfd/ * elf-bfd.h (elf_symbol_from): Remove unused ABFD parameter. * elf.c (ignore_section_sym, _bfd_elf_copy_private_symbol_data), (swap_out_syms): Adjust elf_symbol_from invocation. binutils/ * nm.c (print_symbol): Adjust elf_symbol_from invocation. * objcopy.c (is_hidden_symbol): Likewise. gas/ * config/obj-elf.c (obj_elf_visibility, elf_frob_symbol): Adjust elf_symbol_from invocation. * config/tc-aarch64.c (s_variant_pcs): Likewise. * config/tc-m68hc11.c (s_m68hc11_mark_symbol): Likewise. * config/tc-ppc.c (ppc_elf_localentry, ppc_force_relocation), (ppc_fix_adjustable): Likewise. * config/tc-xgate.c (xgate_frob_symbol): Likewise. ld/ * plugin.c (asymbol_from_plugin_symbol): Adjust elf_symbol_from invocation. opcodes/ * ppc-dis.c (ppc_symbol_is_valid): Adjust elf_symbol_from invocation.
2020-09-10Stop symbols generated by the annobin gcc plugin from breaking the ↵Nick Clifton2-0/+31
disassembly of PowerPC binaries. * ppc-dis.c (ppc_symbol_is_valid): New function. Returns false for hidden, local, no-type symbols. (disassemble_init_powerpc): Point the symbol_is_valid field in the info structure at the new function.
2020-09-10CSKY: Add L2Cache instructions for CK860.Cooper Qu2-109/+124
opcodes/ * csky-opc.h (csky_v2_opcodes): Add L2Cache instructions. * testsuite/gas/csky/cskyv2_ck860.d : Adjust to icache.iva opcode fixing.
2020-09-10CSKY: Add new arches while refine the cpu option process.Cooper Qu1-0/+2
Add arches CK804, CK805 and CK800. CK800 is an special arch which support all instructions for CSKYV2. Refine the cpu tables to simplify adding a new cpu. Co-Authored-By: Lifang Xia <lifang_xia@c-sky.com> gas/ * config/tc-csky.c (struct csky_cpu_info): Add new members isa_flag, features and ver. (struct csky_cpu_feature): New. (struct csky_cpu_version): New. (CSKY_FEATURE_MAX): Define. (CSKY_CPU_REVERISON_MAX): Define. (FEATURE_DSP_EXT, FEATURE_DSP, FEATURE_MMU, FEATURE_VDSP, FEATURE_FLOAT, FEATURE_TRUST, FEATURE_JAVA, FEATURE_SHIELD): Define, each standard one collection of instructions. (CSKY_FEATURES_DEF_NULL, CSKY_FEATURES_DEF_e, CSKY_FEATURES_DEF_t, CSKY_FEATURES_DEF_f, CSKY_FEATURES_DEF_v, CSKY_FEATURES_DEF_ef, CSKY_FEATURES_DEF_jt, CSKY_FEATURES_DEF_efht, CSKY_FEATURES_DEF_efv, CSKY_FEATURES_DEF_eft, CSKY_FEATURES_DEF_d, CSKY_FEATURES_DEF_df, CSKY_FEATURES_DEF_ft, CSKY_FEATURES_DEF_tv, CSKY_FEATURES_DEF_fv, CSKY_FEATURES_DEF_dft, CSKY_FEATURES_DEF_dfv, CSKY_FEATURES_DEF_ftv, CSKY_FEATURES_DEF_eftv): Define, the features combination used by cpu. (CSKY_CPU_REVERISON_r0p0, CSKY_CPU_REVERISON_r1p0, CSKY_CPU_REVERISON_r2p0, CSKY_CPU_REVERISON_r3p0, CSKY_CPU_REVERISON_RESERVED, CSKY_CPU_REVERISON_R3): Define, version information used by cpu. (csky_cpus): Refine, and add CK804, CK805 and CK800. (parse_cpu): Refine. (parse_arch): Refine. (md_show_usage): Refine. (md_begin): Refine. include/ * opcode/csky.h (CSKY_ARCH_804): Define. (CSKY_ARCH_805): Define. (CSKY_ARCH_800): Define.
2020-09-10Fix compile time warnings when building for the CSKY target on a 32-bit host.Nick Clifton2-1/+6
incldue * opcode/csky.h (CSKY_ISA_FLOAT_7E60): Use a long long type for this value. opcodes * csky-dis.c (csky_output_operand): Coerce the immediate values to long before printing.
2020-09-10sprintf arg overlaps destinationAlan Modra2-4/+8
* csky-dis.c (csky_output_operand): Don't sprintf str to itself.
2020-09-09CSKY: Change mvtc and mulsw's ISA flag.Cooper Qu2-2/+7
gas/ * config/tc-csky.c (CSKYV2_ISA_DSP): CSKY_ISA_DSPE60. (CSKY_ISA_860): Likewise. include/ * opcode/csky.h (CSKY_ISA_DSPE60): Define. opcodes/ * csky-opc.h (csky_v2_opcodes): Change mvtc and mulsw's ISA flag.
2020-09-09CSKY: Add FPUV3 instructions, which supported by ck860f.Cooper Qu3-2/+2133
Co-Authored-By: Lifang Xia <lifang_xia@c-sky.com> gas/ * config/tc-csky.c (float_work_fpuv3_fmovi): New function, helper function to encode fpuv3 fmovi instructions. (float_work_fpuv3_fstore): New function. (struct literal): Add new member 'offset'. (csky_cpus): New cpu CK860f. (enter_literal): Return literal pool pointer instead of offset. (parse_rt): Adjust the change of enter_literal. (parse_rtf): Likewise. (v1_work_lrw): Likewise. (v1_work_jbsr): Likewise. (v2_work_lrw): Likewise. (v2_work_jbsr): Likewise. (v2_work_jsri): Likewise. (vdsp_work_vlrw): Likewise. (is_freglist_legal): Add handler for FPUV3. (parse_type_freg): Likewise. (is_imm_within_range): Set e.X_add_number if it is a signed and negtive number. (get_operand_value): Add handler for OPRND_TYPE_IMM9b, OPRND_TYPE_HFLOAT_FMOVI, OPRND_TYPE_SFLOAT_FMOVI and OPRND_TYPE_DFLOAT_FMOVI. (float_to_half): Convert float number to harf float. opcodes/ * csky-dis.c (csky_output_operand): Add handlers for OPRND_TYPE_HFLOAT_FMOVI, OPRND_TYPE_SFLOAT_FMOVI and OPRND_TYPE_DFLOAT_FMOVI. Refine OPRND_TYPE_FREGLIST_DASH to support FPUV3 instructions. * csky-opc.h (enum operand_type): New enum OPRND_TYPE_IMM9b, OPRND_TYPE_HFLOAT_FMOVI, OPRND_TYPE_SFLOAT_FMOVI and OPRND_TYPE_DFLOAT_FMOVI. (OPRND_MASK_4_5, OPRND_MASK_6, OPRND_MASK_6_7, OPRND_MASK_6_8, OPRND_MASK_7, OPRND_MASK_7_8, OPRND_MASK_17_24, OPRND_MASK_20, OPRND_MASK_20_21, OPRND_MASK_20_22, OPRND_MASK_20_23, OPRND_MASK_20_24, OPRND_MASK_20_25, OPRND_MASK_0_3or5_8, OPRND_MASK_0_3or6_7, OPRND_MASK_0_3or25, OPRND_MASK_0_4or21_24, OPRND_MASK_5or20_21, OPRND_MASK_5or20_22, OPRND_MASK_5or20_23, OPRND_MASK_5or20_24, OPRND_MASK_5or20_25, OPRND_MASK_8_9or21_25, OPRND_MASK_8_9or16_25, OPRND_MASK_4_6or20, OPRND_MASK_5_7or20, OPRND_MASK_4_5or20or25, OPRND_MASK_4_6or20or25, OPRND_MASK_4_7or20or25, OPRND_MASK_6_9or17_24, OPRND_MASK_6_7or20, OPRND_MASK_6or20, OPRND_MASK_7or20, OPRND_MASK_5or8_9or16_25, OPRND_MASK_5or8_9or20_25): Define. (csky_v2_opcodes): Add FPUV3 instructions. include/ * opcode/csky.h (CSKY_ISA_FLOAT_7E60): Define.
2020-09-08aarch64: Add support for Armv8-R system registersAlex Coplan3-10/+93
This patch adds support for the system registers introduced in Armv8-R AArch64. gas/ChangeLog: 2020-09-08 Alex Coplan <alex.coplan@arm.com> * config/tc-aarch64.c (parse_sys_reg): Also pass sysreg name to validation function. (parse_sys_ins_reg): Likewise. (print_operands): Pass CPU features to aarch64_print_operand(). * testsuite/gas/aarch64/v8-r-bad-sysregs.d: New test. * testsuite/gas/aarch64/v8-r-bad-sysregs.l: Error output. * testsuite/gas/aarch64/v8-r-bad-sysregs.s: Input. * testsuite/gas/aarch64/v8-r-sysregs-need-arch.d: New test. * testsuite/gas/aarch64/v8-r-sysregs-need-arch.l: Error output. * testsuite/gas/aarch64/v8-r-sysregs.d: New test. * testsuite/gas/aarch64/v8-r-sysregs.s: Input for previous two tests. include/ChangeLog: 2020-09-08 Alex Coplan <alex.coplan@arm.com> * opcode/aarch64.h (aarch64_sys_ins_reg_supported_p): Also take system register name in order to simplify validation for v8-R. (aarch64_print_operand): Also take CPU feature set, as disassembly for system registers now depends on arch variant. opcodes/ChangeLog: 2020-09-08 Alex Coplan <alex.coplan@arm.com> * aarch64-dis.c (print_operands): Pass CPU features to aarch64_print_operand(). * aarch64-opc.c (aarch64_print_operand): Use CPU features to determine preferred disassembly of system registers. (SR_RNG): Refactor to use new SR_FEAT2 macro. (SR_FEAT2): New. (SR_V8_1_A): New. (SR_V8_4_A): New. (SR_V8_A): New. (SR_V8_R): New. (SR_EXPAND_ELx): New. (SR_EXPAND_EL12): New. (aarch64_sys_regs): Specify which registers are only on A-profile, add R-profile system registers. (ENC_BARLAR): New. (PRBARn_ELx): New. (PRLARn_ELx): New. (aarch64_sys_ins_reg_supported_p): Reject EL3 registers for Armv8-R AArch64.
2020-09-08aarch64: Add support for Armv8-R DFB aliasAlex Coplan5-1367/+1385
This adds support for the DFB alias introduced in Armv8-R AArch64. gas/ChangeLog: 2020-09-08 Alex Coplan <alex.coplan@arm.com> * testsuite/gas/aarch64/dfb.d: New test. * testsuite/gas/aarch64/dfb.s: Input. opcodes/ChangeLog: 2020-09-08 Alex Coplan <alex.coplan@arm.com> * aarch64-tbl.h (aarch64_feature_v8_r): New. (ARMV8_R): New. (V8_R_INSN): New. (aarch64_opcode_table): Add dfb. * aarch64-opc-2.c: Regenerate. * aarch64-asm-2.c: Regenerate. * aarch64-dis-2.c: Regenerate.
2020-09-08aarch64: Add base support for Armv8-RAlex Coplan2-0/+41
This patch adds the basic infrastructure needed to support Armv8-R in AArch64 binutils: new command-line flags, new feature bits, a new BFD architecture, and support for differentiating between architecture variants in the disassembler. The new command-line options added by this patch are -march=armv8-r in GAS and -m aarch64:armv8-r in objdump. The disassembler support is necessary since Armv8-R AArch64 introduces a system register (VSCTLR_EL2) which shares an encoding with a different system register (TTBR0_EL2) in Armv8-A. This also allows us to use the correct preferred disassembly for the new DFB alias introduced in Armv8-R. bfd/ChangeLog: 2020-09-08 Alex Coplan <alex.coplan@arm.com> * archures.c (bfd_mach_aarch64_8R): New. * bfd-in2.h: Regenerate. * cpu-aarch64.c (bfd_aarch64_arch_v8_r): New. (bfd_aarch64_arch_ilp32): Update tail pointer. gas/ChangeLog: 2020-09-08 Alex Coplan <alex.coplan@arm.com> * config/tc-aarch64.c (aarch64_archs): Add armv8-r. * doc/c-aarch64.texi: Document -march=armv8-r. include/ChangeLog: 2020-09-08 Alex Coplan <alex.coplan@arm.com> * opcode/aarch64.h (AARCH64_FEATURE_V8_A): New. (AARCH64_FEATURE_V8_R): New. (AARCH64_ARCH_V8): Include new A-profile feature bit. (AARCH64_ARCH_V8_R): New. opcodes/ChangeLog: 2020-09-08 Alex Coplan <alex.coplan@arm.com> * aarch64-dis.c (arch_variant): New. (determine_disassembling_preference): Disassemble according to arch variant. (select_aarch64_variant): New. (print_insn_aarch64): Set feature set.
2020-09-02ubsan: v850-opc.c:412 left shift cannot be representedAlan Modra2-74/+81
include/ * opcode/v850.h (struct v850_operand <insert>): Make param op an unsigned long. opcodes/ * v850-opc.c (insert_i5div1, insert_i5div2, insert_i5div3), (insert_d5_4, insert_d8_6, insert_d8_7, insert_v8, insert_d9), (insert_u16_loop, insert_d16_15, insert_d16_16, insert_d17_16), (insert_d22, insert_d23, insert_d23_align1, insert_i9, insert_u9), (insert_spe, insert_r4, insert_POS, insert_WIDTH, insert_SELID), (insert_VECTOR8, insert_VECTOR5, insert_CACHEOP, insert_PREFOP), (nsert_IMM10U, insert_SRSEL1, insert_SRSEL2): Use unsigned long for value parameter and update code to suit. (extract_d9, extract_d16_15, extract_d16_16, extract_d17_16), (extract_d22, extract_d23, extract_i9): Use unsigned long variables.
2020-09-02ubsan: i386-dis.cAlan Modra2-13/+19
i386-dis.c:12207 left shift of 128 by 24 places cannot be represented in type 'long int' i386-dis.c:12220 left shift of 128 by 24 places cannot be represented in type 'long int' i386-dis.c:12222 left shift of 1 by 31 places cannot be represented in type 'long int' i386-dis.c:12222 signed integer overflow: 162254319 - -2147483648 cannot be represented in type 'long int' * i386-dis.c (OP_E_memory): Don't cast to signed type when negating. (get32, get32s): Use unsigned types in shift expressions.
2020-09-02ubsan: csky-dis.c:1038 left shift cannot be representedAlan Modra2-1/+5
* csky-dis.c (print_insn_csky): Use unsigned type for "given".
2020-09-02ubsan: crx-dis.c:571 left shift of negative valueAlan Modra2-74/+80
* crx-dis.c: Whitespace. (print_arg): Use unsigned type for longdisp and mask variables, and for left shift constant.
2020-09-02ubsan: *-ibld.cAlan Modra16-60/+78
bfin-dis.c:160 shift exponent 32 is too large for 32-bit type 'long unsigned int' bpf-ibld.c:196 left shift of 1 by 31 places cannot be represented in type 'long int' bpf-ibld.c:196 negation of -2147483648 cannot be represented in type 'long int'; cast to an unsigned type to negate this itself bpf-ibld.c:197 left shift of 1 by 31 places cannot be represented in type 'long int' bpf-ibld.c:197 signed integer overflow: -2147483648 - 1 cannot be represented in type 'long int' bpf-ibld.c:501 left shift of 1 by 31 places cannot be represented in type 'long int' * cgen-ibld.in (insert_normal, extract_normal): Use 1UL in left shift. * bpf-ibld.c: Regenerate. * epiphany-ibld.c: Regenerate. * fr30-ibld.c: Regenerate. * frv-ibld.c: Regenerate. * ip2k-ibld.c: Regenerate. * iq2000-ibld.c: Regenerate. * lm32-ibld.c: Regenerate. * m32c-ibld.c: Regenerate. * m32r-ibld.c: Regenerate. * mep-ibld.c: Regenerate. * mt-ibld.c: Regenerate. * or1k-ibld.c: Regenerate. * xc16x-ibld.c: Regenerate. * xstormy16-ibld.c: Regenerate.
2020-09-02ubsan: bfin-dis.c:160 shift exponent 32 is too largeAlan Modra2-1/+5
* bfin-dis.c (MASKBITS): Use SIGNBIT.
2020-09-02CSKY: Add CPU CK803r3.Cooper Qu2-2/+7
Move divul and divsl to CSKYV2_ISA_3E3R3 instruction set, which is enabled by ck803r3, and it's still a part of enhance DSP instruction set. gas/ * config/tc-csky.c (csky_cpus): Add ck803r3. (CSKY_ISA_803R3): Define. (CSKY_ISA_803R2): Refine, use CSKY_ISA_803R1. include/ * opcode/csky.h (CSKYV2_ISA_3E3R3): Define. opcodes/ * csky-opc.h (csky_v2_opcodes): Move divul and divsl to CSKYV2_ISA_3E3R3 instruction set.
2020-09-02CSKY: Fix Encode of mulsws.Cooper Qu2-1/+5
gas/ * testsuite/gas/csky/cskyv2_dsp.d : Fix Encode of mulsws. opcodes/ * csky-opc.h (csky_v2_opcodes): Fix Encode of mulsws.
2020-09-01mep: ubsan: mep-ibld.c:1635,1645,1652 left shift of negative valueAlan Modra2-5/+9
cpu/ * mep-core.cpu (f-8s8a2, f-12s4a2, f-17s16a2): Multiply signed value by two rather than shifting left. (f-24s5a2n): Similarly multiply signed f-24s5a2n-hi to extract. opcodes/ * mep-ibld.c: Regenerate.
2020-08-31CSKY: Refine operand format error reporting.Cooper Qu2-0/+6
Rename SET_ERROR_NUMBER to SET_ERROR_STRING, and add SET_ERROR_INTEGER to report error message which pass an integer argument. gas/ * config/tc-csky.c (csky_error_state): New member 'arg_int'. (SET_ERROR_NUMBER): Rename to SET_ERROR_STRING. (SET_ERROR_INTEGER): New. (err_formats): Add error format for ERROR_FREG_OVER_RANGE and ERROR_VREG_OVER_RANGE. (csky_show_error): Pass an integer argument for some error numbers. (parse_exp): Call SET_ERROR_STRING instead of SET_ERROR_NUMBER. (parse_rt): Likewise. (parse_type_ctrlreg): Likewise. (csky_get_reg_val): Likewise. (is_reglist_legal): Likewise. (is_freglist_legal): Likewise. (is_reglist_dash_comma_legal): Likewise. (is_reg_lshift_illegal): Likewise. (is_psr_bit): Likewise. (parse_type_cpreg): Likewise. (parse_type_cpcreg): Likewise. (parse_type_areg): Likewise. (parse_type_freg): Likewise. (parse_ldst_imm): Likewise and call SET_ERROR_INTEGER. (get_operand_value): Likewise. (parse_operands_op): Likewise and call is_imm_within_range, is_imm_within_range_ext and is_oimm_within_range. (md_assemble): Likewise. (is_imm_within_range): New. (is_imm_within_range_ext): Rename from is_imm_over_range. (is_oimm_within_range): Rename from is_oimm_over_range. (v2_work_add_sub): Call SET_ERROR_INTEGER. (csky_rolc): call is_imm_within_range instead of is_imm_over_range. opcodes/ * csky-dis.c (csky_output_operand): Assign dis_info.value for OPRND_TYPE_VREG.
2020-08-30cr16 disassembly error of disp20 fieldsAlan Modra2-63/+60
When looking at the UB errors, I noticed that cbitb_test.d disassembly wasn't reproducing the input assembly. That turned out to be an error in make_argument case arg_cr. This fixes that and makes some general tidies. opcodes/ * cr16-dis.c: Formatting. (parameter): Delete struct typedef. Use dwordU instead throughout file. (make_argument <arg_idxr>): Simplify detection of cbitb, sbitb and tbitb. (make_argument <arg_cr>): Extract 20-bit field not 16-bit. gas/ * testsuite/gas/cr16/cbitb_test.d: Update expected output. * testsuite/gas/cr16/cbitw_test.d: Likewise. * testsuite/gas/cr16/sbitb_test.d: Likewise. * testsuite/gas/cr16/sbitw_test.d: Likewise. * testsuite/gas/cr16/storb_test.d: Likewise. * testsuite/gas/cr16/storw_test.d: Likewise. * testsuite/gas/cr16/tbitb_test.d: Likewise. * testsuite/gas/cr16/tbitw_test.d: Likewise.
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