aboutsummaryrefslogtreecommitdiff
path: root/opcodes
AgeCommit message (Expand)AuthorFilesLines
2022-10-24x86: emit {evex} prefix when disassembling ambiguous AVX512VL insnsJan Beulich6-235/+271
2022-10-21Support Intel AMX-FP16Cui,Lili6-4088/+4139
2022-10-20x86: re-work AVX-VNNI supportJan Beulich4-7025/+7021
2022-10-18x86: Disable AVX-VNNI when disabling AVX2H.J. Lu2-3/+3
2022-10-18x86: correct CPU_AMX_{BF16,INT8}_FLAGSJan Beulich2-4/+4
2022-10-17Allow explicit size specifier for predicate operand of {sq, uq, }{incp, decp}CaiJingtao2-7/+17
2022-10-17aarch64: Tweak handling of F_STRICTRichard Sandiford1-17/+8
2022-10-17x86: properly decode EVEX.W for AVX512_4{FMAPS,VNNIW} insnsJan Beulich1-6/+6
2022-10-17x86: fold AVX512-VNNI disassembler entries with AVX-VNNI onesJan Beulich3-15/+22
2022-10-16PowerPC se_rfmci and VLE, SPE2 and LSP insns with -manyAlan Modra2-1/+9
2022-10-14PowerPC SPE disassembly and testsAlan Modra1-2/+2
2022-10-14e200 LSP supportAlan Modra2-337/+411
2022-10-14opcodes/riscv-dis.c: Remove last_map_stateTsukasa OI1-3/+0
2022-10-14opcodes/riscv-dis.c: Make XLEN variable staticTsukasa OI1-1/+1
2022-10-14opcodes/riscv-dis.c: Use bool type whenever possibleTsukasa OI1-5/+5
2022-10-14opcodes/riscv-dis.c: Tidying with spacingTsukasa OI1-1/+1
2022-10-14opcodes/riscv-dis.c: Tidying with comments/clarityTsukasa OI1-4/+21
2022-10-14RISC-V: Move standard hints before all instructionsTsukasa OI1-4/+8
2022-10-14RISC-V: Move certain arrays to riscv-opc.cTsukasa OI1-0/+13
2022-10-06RISC-V: Print XTheadMemPair literal as "immediate"Tsukasa OI1-1/+1
2022-10-06RISC-V: Fix T-Head immediate types on printingTsukasa OI1-4/+4
2022-10-06RISC-V: Print comma and tabs as the "text" styleTsukasa OI1-11/+20
2022-10-06RISC-V: Optimize riscv_disassemble_data printfTsukasa OI1-6/+4
2022-10-06RISC-V: Fix printf argument types corresponding %xTsukasa OI1-7/+7
2022-10-06RISC-V: Fix immediates to have "immediate" styleTsukasa OI1-5/+5
2022-10-05Arm64: support CLEARBHB aliasJan Beulich4-1576/+1579
2022-10-04RISC-V: Fix buffer overflow on print_insn_riscvTsukasa OI1-1/+1
2022-10-04RISC-V: Renamed INSN_CLASS for floating point in integer extensions.Nelson Chu1-222/+222
2022-10-04opcodes/riscv: style csr names as registersAndrew Burgess1-1/+2
2022-10-03RISC-V: Move supervisor instructions after all unprivileged onesTsukasa OI1-32/+32
2022-09-30RISC-V: Relax "fmv.[sdq]" requirementsTsukasa OI1-3/+3
2022-09-30RISC-V: fix build after "Add support for arbitrary immediate encoding formats"Jan Beulich1-2/+2
2022-09-30RISC-V: drop stray INSN_ALIAS flagsJan Beulich1-3/+3
2022-09-30RISC-V: re-arrange opcode table for consistent alias handlingJan Beulich1-38/+38
2022-09-30x86: correct build dependencies in opcodes/Jan Beulich2-12/+16
2022-09-30x86/Intel: restrict suffix derivationJan Beulich4-7481/+7463
2022-09-30PR29626, Segfault when disassembling ARM codeAlan Modra1-63/+61
2022-09-23RISC-V: Add Zawrs ISA extension supportChristoph Müllner1-0/+4
2022-09-22RISC-V: Add T-Head MemPair vendor extensionChristoph Müllner1-0/+24
2022-09-22RISC-V: Add support for literal instruction argumentsChristoph Müllner1-0/+9
2022-09-22RISC-V: Add T-Head MemIdx vendor extensionChristoph Müllner1-0/+60
2022-09-22RISC-V: Add T-Head FMemIdx vendor extensionChristoph Müllner1-0/+10
2022-09-22RISC-V: Add T-Head MAC vendor extensionChristoph Müllner1-0/+8
2022-09-22RISC-V: Add T-Head CondMov vendor extensionChristoph Müllner1-0/+4
2022-09-22RISC-V: Add T-Head Bitmanip vendor extensionChristoph Müllner1-0/+17
2022-09-22RISC-V: Add support for arbitrary immediate encoding formatsChristoph Müllner1-0/+34
2022-09-22RISC-V: Add T-Head SYNC vendor extensionChristoph Müllner1-0/+7
2022-09-22RISC-V: Add T-Head CMO vendor extensionChristoph Müllner1-0/+25
2022-09-22opcodes: SH fix bank register disassemble.Yoshinori Sato2-0/+7
2022-09-22RISC-V: Remove "b" operand type from disassemblerTsukasa OI1-1/+0
generated by cgit v1.1 at 2024-12-21 11:11:05 +0000