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AgeCommit message (Expand)AuthorFilesLines
2020-06-08x86: restrict use of register aliasesJan Beulich2-1/+5
2020-06-06Power10 tidiesAlan Modra2-0/+9
2020-06-05bpf stack smashing detectedAlan Modra2-5/+11
2020-06-04cpu,gas,opcodes: remove no longer needed workaround from the BPF portJose E. Marchesi5-27/+35
2020-06-04opcodes: discriminate endianness and insn-endianness in CGEN portsJose E. Marchesi32-98/+145
2020-06-04opcodes: support insn endianness in cgen_cpu_openJose E. Marchesi30-70/+236
2020-06-03Updated Serbian translation for the opcodes sub-directoryNick Clifton2-530/+1480
2020-06-03RISC-V: Fix the error when building RISC-V linux native gdbserver.Nelson Chu2-8/+13
2020-06-01Regen opcodes/bpf-desc.cAlan Modra2-12/+8
2020-05-28cpu,opcodes: add instruction semantics to bpf.cpu and minor fixesJose E. Marchesi5-204/+243
2020-05-28ubsan: nios2: undefined shiftAlan Modra2-11/+10
2020-05-28asan: ns32k: use of uninitialized valueAlan Modra2-7/+8
2020-05-28Fix a potential use of an uninitialised value in the ns32k disassembler.Nick Clifton2-1/+9
2020-05-26Fix extraction of signed constants in nios2 disassembler (again).Sandra Loosemore2-8/+25
2020-05-26ChangeLog entries for f687f5f563Stefan Schulze Frielinghaus1-0/+6
2020-05-26S/390: z13: Accept vector alignment hintsStefan Schulze Frielinghaus1-12/+7
2020-05-21Replace "if (x) free (x)" with "free (x)", opcodesAlan Modra20-194/+88
2020-05-20[PATCH v2 0/9] RISC-V: Support version controling for ISA standard extensions...Nelson Chu4-63/+331
2020-05-19Power10 dcbf, sync, and wait extensions.Peter Bergner2-26/+243
2020-05-19or1k: Regenerate opcodes after removing 32-bit supportStafford Horne9-1648/+1195
2020-05-11Power10 VSX scalar min-max-compare quad precision operationsAlan Modra2-0/+16
2020-05-11Power10 VSX load/store rightmost element operationsAlan Modra2-0/+21
2020-05-11Power10 test lsb by byte operationAlan Modra2-0/+5
2020-05-11Power10 string operationsAlan Modra2-0/+15
2020-05-11Power10 Set boolean extensionPeter Bergner2-0/+13
2020-05-11Power10 bit manipulation operationsAlan Modra2-1/+27
2020-05-11Power10 VSX PCV generate operationsAlan Modra2-0/+9
2020-05-11Power10 VSX Mask Manipulation OperationsAlan Modra2-1/+36
2020-05-11Power10 Reduced precision outer product operationsAlan Modra3-4/+231
2020-05-11Power10 SIMD permute class operationsAlan Modra2-3/+129
2020-05-11Power10 128-bit binary integer operationsAlan Modra2-0/+44
2020-05-11Power10 VSX 32-byte storage accessAlan Modra2-1/+44
2020-05-11Power10 vector integer multiply, divide, modulo insnsAlan Modra2-0/+23
2020-05-11Power10 byte reverse instructionsPeter Bergner2-0/+10
2020-05-11Power10 Copy/Paste ExtensionsPeter Bergner2-2/+37
2020-05-11Power10 Add new L operand to the slbiag instructionPeter Bergner2-1/+7
2020-05-11PowerPC Default disassembler to -Mpower10Alan Modra2-1/+5
2020-05-11PowerPC Rename powerxx to power10Alan Modra3-30/+41
2020-05-11Updated French translation for the ld sub-directory and an update Spanish tra...Nick Clifton2-349/+455
2020-04-30AArch64: add GAS support for UDF instructionAlex Coplan8-2477/+2541
2020-04-29Also use unsigned 8-bit immediate values for the LDRC and SETRC insns.Nick Clifton2-2/+8
2020-04-29Updated Serbian translation for the binutils sub-directory, and Swedish trans...Nick Clifton2-351/+457
2020-04-29Fix the disassmbly of SH instructions which have an unsigned 8-bit immediate ...Nick Clifton3-18/+31
2020-04-21Disallow PC relative for CMPI on MC68000/10Andreas Schwab2-6/+18
2020-04-20[AArch64, Binutils] Add missing TSB instructionSudakshina Das10-1376/+1422
2020-04-20[AArch64, Binutils] Make hint space instructions valid for Armv8-aSudakshina Das5-1370/+1369
2020-04-17[PATCH v2] binutils: arm: Fix disassembly of conditional VDUPs.Fredrik Strupe2-10/+53
2020-04-16cpu,gas,opcodes: support for eBPF JMP32 instruction classDavid Faust5-13/+515
2020-04-07Add support for intel TSXLDTRK instructions$Cui,Lili7-4154/+4234
2020-04-02Add support for intel SERIALIZE instructionLiliCui7-4151/+4205
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