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2017-03-29opcodes: sparc: support missing SPARC ASIs from UA2005, UA2007, OSA2011, & OS...Jose E. Marchesi2-0/+34
2017-03-29PowerPC -Mraw disassemblyAlan Modra2-10/+26
2017-03-27PR21303, objdump doesn't show e200z4 insnsAlan Modra2-2/+19
2017-03-27Implement ARC NPS-400 Ultra Ip and Miscellaneous instructions.Rinat Zelig3-350/+612
2017-03-21S/390: Remove vx2 facility flagAndreas Krebbel3-146/+147
2017-03-21arc/nps400: Add cp16/cp32 instructions to opcodes libraryRinat Zelig3-3/+279
2017-03-17E6500 spr mnemonicsAlan Modra2-8/+15
2017-03-15RISC-V: Fix assembler for c.li, c.andi and c.addiwKito Cheng2-3/+9
2017-03-15RISC-V: Fix assembler for c.addi, rd can be x0Kito Cheng2-1/+5
2017-03-14RISC-V: Fix [dis]assembly of srai/srliAndrew Waterman2-4/+11
2017-03-09X86: Add pseudo prefixes to control encodingH.J. Lu5-73/+183
2017-03-09Use CpuCET on rdsspqH.J. Lu3-2/+7
2017-03-08Update -maltivec and -mvsx options to only enable their oldest instructions.Peter Bergner2-2/+7
2017-03-08Add support for the new 'lnia' extended mnemonic.Peter Bergner2-0/+7
2017-03-06Add support for Intel CET instructionsH.J. Lu7-334/+681
2017-03-06Don't decode powerpc insns with invalid fieldsAlan Modra2-49/+168
2017-02-28GDB: Add support for the new set/show disassembler-options commands.Peter Bergner6-218/+394
2017-02-28x86: fix handling of 64-bit operand size VPCMPESTR{I,M}Jan Beulich4-26/+170
2017-02-24[AArch64] Additional SVE instructionsRichard Sandiford11-2089/+2815
2017-02-24[AArch64] Add a "compnum" featureRichard Sandiford2-6/+17
2017-02-24x86: also correctly support TEST opcode aliasesJan Beulich2-2/+6
2017-02-23S/390: Add support for new cpu architecture - arch12.Andreas Krebbel3-79/+311
2017-02-23opcodes,gas: associate SPARC ASIs with an architecture level.Sheldon Lobo2-195/+196
2017-02-23x86: drop stray VEX opcode 82 referencesJan Beulich2-4/+9
2017-02-22aarch64: actually copy first operand in convert_bfc_to_bfm()Jan Beulich2-2/+7
2017-02-15Add SFENCE.VMA instructionAndrew Waterman2-0/+8
2017-02-15[AArch64] Add SVE system registersRichard Sandiford2-0/+21
2017-02-15[ARC] Fix assembler relaxation.Claudiu Zissulescu2-34/+75
2017-02-15Distinguish some of the registers different on ARC700 and HS38 cpusVineet Gupta2-12/+41
2017-02-14PowerPC register expression checksAlan Modra2-5/+11
2017-02-11Fix use after free in cgen instruction lookupAlan Modra2-15/+20
2017-02-10POWER9 add scv/rfscv instruction supportNicholas Piggin2-1/+7
2017-02-06[ARC] Provide an interface to decode ARC instructions.Claudiu Zissulescu4-363/+609
2017-02-03Fix compile time warning messages when compiling binutils with gcc 7.0.1.Nick Clifton3-5/+16
2017-01-27Fix disassembling of TIC6X parallel instructions where the previous fetch pac...Alexis Deruell2-2/+18
2017-01-25Clarify that include/opcode/ files are part of GNU opcodesDimitar Dimitrov2-2/+5
2017-01-20Updated Irish translation for the opcodes library.Nick Clifton2-458/+813
2017-01-18[ARM] Fix the decoding of indexed element VCMLA instructionSzabolcs Nagy2-4/+8
2017-01-13Return -1 on memory error in print_insn_m68kYao Qi2-7/+19
2017-01-13Remove magic numbers in m68k-dis.c:print_insn_argYao Qi2-41/+72
2017-01-12Enable Intel AVX512_VPOPCNTDQ instructionsIgor Tsimbalist8-5344/+5432
2017-01-12Return -1 on memory error in print_insn_msp430Yao Qi2-14/+99
2017-01-05Prevent an abort in the FRV disassembler if the target bfd name is unknown.Nick Clifton2-3/+11
2017-01-04[AArch64] Add separate feature flag for weaker release consistent load insnsSzabolcs Nagy2-3/+13
2017-01-03Add support for the Q extension to the RISCV ISA.Kito Cheng2-0/+66
2017-01-03Add fall through comment.Dilyan Palauzov2-0/+5
2017-01-03Add new Serbian translation for the opcodes library.Nick Clifton4-2/+1515
2017-01-02Regen opcodes cgen filesAlan Modra27-0/+237
2017-01-02Update year range in copyright notice of all files.Alan Modra275-278/+282
2017-01-02ChangeLog rotationAlan Modra2-2167/+2181
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