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AgeCommit message (Expand)AuthorFilesLines
2018-03-14RISC-V: Add .insn support.Jim Wilson2-0/+78
2018-03-13Updated Russian and Brazilian Portuguese translations.Nick Clifton2-3/+7
2018-03-08x86-64: Also optimize "clr reg64"H.J. Lu3-2/+7
2018-03-08x86: Remove support for old (<= 2.8.1) versions of gccH.J. Lu5-5237/+5098
2018-03-08x86: fold several AVX512VL templatesJan Beulich4-2052/+357
2018-03-08x86: fold certain AVX512 rotate and shift templatesJan Beulich3-954/+142
2018-03-08x86: fold VEX-encoded GFNI templatesJan Beulich3-86/+21
2018-03-08x86: fold a few AVX512F templatesJan Beulich3-240/+31
2018-03-08x86: fold LWP templatesJan Beulich3-86/+20
2018-03-08x86: fold FMA and FMA4 templatesJan Beulich3-1656/+330
2018-03-08x86: drop {X,Y,Z}MMWORD_MNEM_SUFFIXJan Beulich3-2/+7
2018-03-08x86: drop bogus NoAVXJan Beulich3-14/+20
2018-03-08x86: avoid SSE check for LDMXCSR/STMXCSRJan Beulich3-4/+9
2018-03-08x86: drop FloatDJan Beulich5-19738/+19743
2018-03-08x86/Intel: correct disassembly of fsub*/fdiv*Jan Beulich2-8/+12
2018-03-08x86: bogus VMOVD with 64-bit operands should only allow for registersJan Beulich3-6/+11
2018-03-08x86: fold AVX vcvtpd2ps memory formsJan Beulich3-20/+8
2018-03-07XCOFF disassemblerAlan Modra4-20/+19
2018-03-03opcodes error messagesAlan Modra78-867/+1218
2018-03-01x86: Encode AVX256/AVX512 vpsub[bwdq] with VEX128/EVEX128H.J. Lu3-24/+30
2018-03-01Add missing translations to ALL_LINGUASAlan Modra3-2/+7
2018-02-27[ARM] Remove ARM_FEATURE_COPY macroThomas Preud'homme2-2/+7
2018-02-27x86: Add -O[2|s] assembler command-line optionsH.J. Lu5-5354/+5388
2018-02-26crx string overflow warningAlan Modra2-1/+6
2018-02-22RISC-V: Make disassebler work for --enable-targets=all config.Jim Wilson2-0/+5
2018-02-22x86: Add {rex} pseudo prefixH.J. Lu3-0/+20
2018-02-20MIPS16/opcodes: Free up `M' operand codeMaciej W. Rozycki2-2/+6
2018-02-19[ARM] Fix bxns maskThomas Preud'homme2-1/+5
2018-02-13Fix compile time warning messages from gcc version 8 about cast between incom...Nick Clifton2-3/+13
2018-02-13WebAssembly: Correct an `index' global shadowing error for pre-4.8 GCCMaciej W. Rozycki2-3/+8
2018-02-12MIPS: Fix encoding for MIPSr6 sigrie instruction.Henry Wong2-1/+5
2018-02-05Updated Brazillian portuguese and Russian translationNick Clifton2-2/+6
2018-01-23Enable Intel PCONFIG instruction.Igor Tsimbalist7-5483/+5529
2018-01-23Enable Intel WBNOINVD instruction.Igor Tsimbalist7-5483/+5535
2018-01-17RISC-V: Fix bug in prior addi/c.nop patch.Jim Wilson2-1/+5
2018-01-17Replace CET bit with IBT and SHSTK bits.Igor Tsimbalist6-5557/+5602
2018-01-16Update translations for various binutils components.Nick Clifton3-596/+2117
2018-01-15RISC-V: Add support for addi that compresses to c.nop.Jim Wilson2-0/+13
2018-01-15Update Ukranian translations for bfd, binutils, gas, gold, ld and opcodesNick Clifton2-407/+444
2018-01-13Update pot filesNick Clifton2-371/+407
2018-01-13Bump version number to 2.30.51Nick Clifton2-10/+14
2018-01-13Add note about 2.30 branch creation to changelogsNick Clifton1-0/+4
2018-01-11Remove VL variants for 4FMAPS and 4VNNIW insns.Igor Tsimbalist3-172/+5
2018-01-10x86: fix Disp8 handling for scalar AVX512_4FMAPS insnsJan Beulich3-4/+9
2018-01-10x86: fix Disp8 handling for AVX512VL VPCMP*{B,W} variantsJan Beulich3-96/+106
2018-01-09RISC-V: Disassemble x0 based addresses as 0.Jim Wilson2-1/+6
2018-01-09[Arm] Add CSDB instructionJames Greenhalgh2-0/+11
2018-01-09Add support for the AArch64's CSDB instruction.James Greenhalgh5-1012/+1022
2018-01-08x86: Properly encode vmovd with 64-bit memeoryH.J. Lu3-42/+13
2018-01-05RISC-V: Print symbol address for jalr w/ zero offset.Jim Wilson2-0/+7
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