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2018-01-16Update translations for various binutils components.Nick Clifton3-596/+2117
2018-01-15RISC-V: Add support for addi that compresses to c.nop.Jim Wilson2-0/+13
2018-01-15Update Ukranian translations for bfd, binutils, gas, gold, ld and opcodesNick Clifton2-407/+444
2018-01-13Update pot filesNick Clifton2-371/+407
2018-01-13Bump version number to 2.30.51Nick Clifton2-10/+14
2018-01-13Add note about 2.30 branch creation to changelogsNick Clifton1-0/+4
2018-01-11Remove VL variants for 4FMAPS and 4VNNIW insns.Igor Tsimbalist3-172/+5
2018-01-10x86: fix Disp8 handling for scalar AVX512_4FMAPS insnsJan Beulich3-4/+9
2018-01-10x86: fix Disp8 handling for AVX512VL VPCMP*{B,W} variantsJan Beulich3-96/+106
2018-01-09RISC-V: Disassemble x0 based addresses as 0.Jim Wilson2-1/+6
2018-01-09[Arm] Add CSDB instructionJames Greenhalgh2-0/+11
2018-01-09Add support for the AArch64's CSDB instruction.James Greenhalgh5-1012/+1022
2018-01-08x86: Properly encode vmovd with 64-bit memeoryH.J. Lu3-42/+13
2018-01-05RISC-V: Print symbol address for jalr w/ zero offset.Jim Wilson2-0/+7
2018-01-03Update year range in copyright notice of binutils filesAlan Modra277-280/+284
2018-01-03ChangeLog rotationAlan Modra2-1965/+1979
2018-01-02x86: partial revert of 10c17abdd0Jan Beulich2-0/+9
2017-12-20RISC-V: Add compressed instruction hints, and a few misc cleanups.Jim Wilson2-13/+46
2017-12-19Correct disassembly of dot product instructions.Tamar Christina5-4/+15
2017-12-19Add support for V_4B so we can properly reject it.Tamar Christina2-0/+6
2017-12-18x86: fold certain AVX and AVX2 templatesJan Beulich5-4106/+789
2017-12-18x86: fold RegXMM/RegYMM/RegZMM into RegSIMDJan Beulich7-46306/+46315
2017-12-18x86: drop FloatReg and FloatAccJan Beulich6-32581/+32585
2017-12-18x86: replace Reg8, Reg16, Reg32, and Reg64Jan Beulich7-32766/+33250
2017-12-15Fix disassembly for PowerPCDimitar Dimitrov2-3/+8
2017-12-15x86: drop stray CheckRegSize usesJan Beulich3-155/+164
2017-12-13Add missing RISC-V fsrmi and fsflagsi instructions.Jim Wilson2-0/+9
2017-12-13This patch enables disassembler_needs_relocs for PRU. It is needed to print c...Dimitar Dimitrov2-0/+9
2017-12-11[Binutils][Objdump]Check symbol section information while search a mapping sy...Renlin Li2-3/+11
2017-12-03Fix "FAIL: VLE relocations 3"Alan Modra2-7/+7
2017-12-01Use consistent types for holding instructions, instruction masks, etc.Peter Bergner3-517/+556
2017-11-30x86: derive DispN from BaseIndexJan Beulich4-4142/+4196
2017-11-30x86: drop Vec_Disp8Jan Beulich6-16227/+16225
2017-11-29Support --localedir, --datarootdir and --datadirStefan Stroe2-4/+10
2017-11-27Update the simplified Chinese translation of the messages in the opcodes libr...Nick Clifton2-437/+945
2017-11-24x86: don't omit disambiguating suffixes from "fi*"Jan Beulich2-12/+17
2017-11-23Add Disp8MemShift for AVX512 VAES instructions.Igor Tsimbalist3-24/+29
2017-11-23x86: fix AVX-512 16-bit addressingJan Beulich2-0/+7
2017-11-23x86: correct UDnJan Beulich4-14/+47
2017-11-22Remove Vec_Disp8 field for vgf2p8mulb for AVX flavor.Igor Tsimbalist3-4/+9
2017-11-22Update ChangeLogIgor Tsimbalist1-0/+5
2017-11-22Remove Vec_Disp8 from vpcompressb and vpexpandb.Igor Tsimbalist2-13/+12
2017-11-22[ARC] Fix handling of ARCv2 H-register class.claziss2-0/+6
2017-11-21[ARC] Improve printing of pc-relative instructions.claziss3-17/+52
2017-11-16Add new AArch64 FP16 FM{A|S} instructions.Tamar Christina2-2/+7
2017-11-16Correct AArch64 crypto dependencies.Tamar Christina1-4/+6
2017-11-16Add assembler and disassembler support for the new Armv8.4-a instructions for...Tamar Christina3-2925/+3534
2017-11-16x86: ignore high register select bit(s) in 32- and 16-bit modesJan Beulich2-28/+47
2017-11-15x86: use correct register namesJan Beulich2-3/+8
2017-11-15x86: drop VEXI4_Fixup()Jan Beulich2-50/+45
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