aboutsummaryrefslogtreecommitdiff
path: root/opcodes
AgeCommit message (Collapse)AuthorFilesLines
2002-12-01 * m68hc11-dis.c (PC_REGNUM): Define.Stephane Carrez2-5/+52
(print_indexed_operand): Need an adjustment for some PC-relative operand modes; print the final address of PC-relative modes. (print_insn): Take into account movw/movb to adjust the PC-relative operand addresses.
2002-11-30s/boolean/bfd_boolean/ s/true/TRUE/ s/false/FALSE/. SimplifyAlan Modra9-158/+183
comparisons of bfd_boolean vars with TRUE/FALSE. Formatting.
2002-11-25* xstormy16-opc.c: Regenerate.DJ Delorie2-2/+6
2002-11-25Patch from Kenneth Chen to fix brl disassembly.Jim Wilson2-2/+6
* ia64-dis.c (print_insn_ia64): Correct handling of IA64_OPND_TGT64.
2002-11-20* xstormy16-desc.c: Regenerate.DJ Delorie4-3/+42
* xstormy16-opc.c: Regenerate. * xstormy16-opc.h: Regenerate.
2002-11-182002-11-12 Klee Dienes <kdienes@apple.com>Klee Dienes2-11/+34
* avr-dis.c: Include libiberty.h (for xmalloc). (struct avr_opcodes_s): Remove 'bin_mask' field (it's automatically computed in the init routine). (AVR_INSN): No longer provide bin_mask field in initializer. (avr_opcodes_s): Declare as const. (print_insn_avr): Store the bin_mask field in a separate table (allocated with xmalloc); iterate through it at the same time as we iterate through the opcodes.
2002-11-182002-11-11 Klee Dienes <kdienes@apple.com>Klee Dienes2-9/+43
* h8300.h (h8_opcode): Remove 'length' field. (h8_opcodes): Mark as 'const' (both the declaration and definition). Modify initializer and initializer macros to no longer initialize the length field. 2002-11-11 Klee Dienes <kdienes@apple.com> * h8300-dis.c: Include libiberty.h (for xmalloc). (struct h8_instruction): New type, used to wrap h8_opcodes with a length field (computed at run-time). (h8_instructions): New variable. (bfd_h8_disassemble_init): Allocate the storage for h8_instructions. Fill h8_instructions with pointers to the appropriate opcode and the correct value for the length field. (bfd_h8_disassemble): Iterate through h8_instructions instead of h8_opcodes.
2002-11-182002-11-18 Klee Dienes <kdienes@apple.com>Klee Dienes9-9/+27
* arc.h (arc_ext_opcodes): Declare as extern. (arc_ext_operands): Declare as extern. * i860.h (i860_opcodes): Declare as const. 2002-11-18 Klee Dienes <kdienes@apple.com> * arc-opc.c (arc_ext_opcodes): Define. (arc_ext_operands): Define. * i386-dis.c (Suffix3DNow): Declare as const. * arm-opc.h (arm_opcodes): Declare as const. (thumb_opcodes): Declare as const. * h8500-opc.h (h8500_table): Declare as const. (h8500_table): Use a NULL for the opcode in the terminator, so that code testing (opcode->name) behaves correctly. * mcore-opc.h (mcore_table): Declare as const. * sh-opc.h (sh_table): Declare as const. * w65-opc.h (optable): Declare as const. * z8k-opc.h (z8k_table): Declare as const.
2002-11-18 * gas/config/tc-tic4x.c: Fixed proper commandlineSvein Seldal2-31/+136
parameters. Added support for new opcode-list format. General error message fixups. (c4x_inst_add): Reject insn not for our CPU (md_begin): Added matrix for setting the proper opcode-level & device-flags according to cpu type and revision. Rewrite the opcode hasher. (c4x_operand_parse): Fix opcode bug (c4x_operands_match): New function argument. Added dry-run mechanism, that is optional error generation. Added constraint 'i' and 'j'. (c4x_insn_check): Added new function for post-verification of the generated insn. (md_assemble): Check all opcodes before croaking because of an argument mismatch. Need this to be able to fully support ortogonally arguments. (md_parse_options): Revised commandprompt swicthes and added new ones. (md_show_usage): Complete rewrite of printout. * gas/testsuite/gas/tic4x/addressing.s: Fix bug in one insn * gas/testsuite/gas/tic4x/addressing_c3x.d: Update thereafter * gas/testsuite/gas/tic4x/addressing_c4x.d: Update thereafter * gas/testsuite/gas/tic4x/allopcodes.S: Add support for new opclass.h changes * gas/testsuite/gas/tic4x/opclasses.h: Added testsuites for the new enhanced opcodes. * gas/testsuite/gas/tic4x/opcodes.s: Regenerate * gas/testsuite/gas/tic4x/opcodes_c3x.d: Update from above * gas/testsuite/gas/tic4x/opcodes_c4x.d: Update from above * gas/testsuite/gas/tic4x/opcodes_new.d: Added new testsuite for the enhanced and special insns. * gas/testsuite/gas/tic4x/tic4x.exp: Added the opcodes_new testsuite * include/opcode/tic4x.h: File reordering. Added enhanced opcodes. * opcodes/tic4x-dis.c: Added support for enhanced and special insn. (c4x_print_op): Added insn class 'i' and 'j' (c4x_hash_opcode_special): Add to support special insn (c4x_hash_opcode): Update to support the new opcode-list format. Add support for the new special insns. (c4x_disassemble): New opcode-list support.
2002-11-162002-11-16 Klee Dienes <kdienes@apple.com>Klee Dienes2-34/+537
* m88k-dis.c: Include libiberty.h (for xmalloc). (HASHTAB): New type, used to build instruction hash tables. Contains a pointer to an INSTAB and a pointer to the next hash chain entry. (instructions): Move definition from m88k.h; remove initialization of 'next' field. (hashtable): Now an aray of pointer-to-HASHTAB, not INSTAB. (printop): Mark pointer to OPSPEC as const. (install): Remove; fold into init_disasm. (m88kdis): Update to ihashtab_initialized to 1 after calling init_disasm. entry_ptr now iterates through HASHTABs, not INSTABs. (init_disasm): Iterate through the instructions and add to hashtable[].
2002-11-16 * gas/config/tc-tic4x.c: Remove c4x_pseudo_ignore function.Svein Seldal2-1/+10
(c4x_operands_match): Added check for 8-bits LDF insn. Give warning when using constant direct bigger than 2^16. Add the new arguments. * include/opcode/tic4x.h: Major rewrite of entire file. Define instruction classes, and put each instruction into a class. * opcodes/tic4x-dis.c: (c4x_print_op): Add support for the new argument format. Fix bug in 'N' register printer.
2002-11-12 * ppc-dis.c (print_insn_powerpc): Correct condition register display.Alan Modra2-13/+12
2002-11-082002-11-07 Aldy Hernandez <aldyh@redhat.com>Aldy Hernandez2-1/+2
* ppc-opc.c (EVUIMM_4): Change bit size to 32. (EVUIMM_2): Same. (EVUIMM_8): Same.
2002-11-072002-11-07 Aldy Hernandez <aldyh@redhat.com>Aldy Hernandez2-2/+7
* ppc-opc.c (EVUIMM_4): Change bit size to 32. (EVUIMM_2): Same.
2002-11-07Convert ia64-gen to use getopt(). Add standard GNU options plus --srcdir.Nick Clifton12-2203/+2292
Convert Makefile.am to pass --srcdir to ia64-gen. Fix compile time warnings.
2002-11-072002-11-06 Aldy Hernandez <aldyh@redhat.com>Aldy Hernandez2-4/+8
* opcodes/ppc-opc.c: Change RD to RS for evmerge*.
2002-10-23Add conditional/unconditional branch classification.Nick Clifton2-19/+26
2002-10-13 * m68hc11-dis.c (print_insn): Treat bitmask and branch operandsStephane Carrez2-49/+55
at the end.
2002-09-30[include/opcode/]Richard Sandiford3-21/+176
* mips.h: Update comment for new opcodes. (OP_MASK_VECBYTE, OP_SH_VECBYTE): New. (OP_MASK_VECALIGN, OP_SH_VECALIGN): New. (INSN_4111, INSN_4120, INSN_5400, INSN_5500): New. (CPU_VR4120, CPU_VR5400, CPU_VR5500): New. (OPCODE_IS_MEMBER): Handle the new CPU_* values and INSN_* flags. Don't match CPU_R4111 with INSN_4100. [opcodes/] * mips-dis.c (print_insn_arg): Handle '[', ']', 'e' and '%'. (mips_isa_type): Handle bfd_mach_mips4120, bfd_mach_mips5400 and bfd_mach_mips5500. * mips-opc.c (V1): Include INSN_4111 and INSN_4120. (N411, N412, N5, N54, N55): New convenience defines. (mips_builtin_opcodes): Add vr4120, vr5400 and vr5500 opcodes. Change dmadd16 and madd16 from V1 to N411.
2002-09-26 /gas/ChangeLogThiemo Seufer2-1/+8
* config/tc-mips.c (CPU_HAS_MIPS16): Add mips-lsi-elf as MIPS16 capable configuration. (macro_build): Check for MIPS16 capability, not for actual MIPS16 code generation. (mips_ip): Likewise. /gas/testsuite/ChangeLog * gas/mips/mips-jalx.d: New file, check jalx assembly. * gas/mips/mips-jalx.s: Likewise. * gas/mips/mips-no-jalx.l: Likewise. * gas/mips/mips-no-jalx.s: Likewise. * gas/mips/mips16-jalx.d: Likewise. * gas/mips/mips16-jalx.s: Likewise. * gas/mips/mips.exp: Add new tests. /opcodes/ChangeLog: * mips-dis.c (print_insn_mips): Always allow disassembly of 32-bit jalx opcode.
2002-09-24Updated German translation.Nick Clifton2-45/+100
2002-09-21 * Makefile.am: Run "make dep-am".Alan Modra4-141/+148
* Makefile.in: Regenerate. * po/POTFILES.in: Regenerate.
2002-09-20Allow CRFS and CRFD operands to accept CR register namesNick Clifton2-2/+7
2002-09-17 * tic4x-dis.c: Add function declarations and ATTRIBUTE_UNUSED.Alan Modra2-32/+86
Convert functions to K&R format.
2002-09-13Fix Book-E opcodesNick Clifton2-272/+396
2002-09-12 * ppc-dis.c (powerpc_dialect): Add missing PPC_OPCODE_CLASSIC.Alan Modra2-1/+6
2002-09-11Update translationsNick Clifton2-47/+100
2002-09-04Do not insert non-BookE32 instructions into the hash table if the target cpuNick Clifton2-2/+6
is the BookE32. (case 107575)
2002-09-04Have objdump's --help switch document PPC -M options.Nick Clifton3-0/+24
2002-09-04The BookE implementations of the TLBWE and TLBRE instructions do not take anyNick Clifton2-3/+8
arguments.
2002-09-02Remove redundant references to V850EA architecture.Nick Clifton2-17/+4
2002-09-02 * arc-opc.c: Include bfd.h.Alan Modra2-1/+7
(arc_get_opcode_mach): Subtract off base bfd_mach value.
2002-08-30 * v850-dis.c (disassemble): Remove bfd_mach_v850ea case.Alan Modra3-5/+7
* mips-dis.c (_print_insn_mips): Don't use hard-coded mach constants.
2002-08-28Add TMS320C4x supportNick Clifton7-1/+707
2002-08-22opcodes: Fix definition of "in rd,imm16" opcode.Nick Clifton4-5/+12
gas: Adjust ptr variable also in "case 0" case.
2002-08-192002-08-19 Elena Zannoni <ezannoni@redhat.com>Elena Zannoni3-7/+623
From matthew green <mrg@redhat.com> * ppc-dis.c (powerpc_dialect): Support `-m500', `-m500x2' and `-mefs'. Turn off AltiVec for E500 and efs. (print_insn_powerpc): Don't print an AltiVec instruction if the dialect is not efs. * ppc-opc.c (insert_pmrn, extract_pmrn, insert_ev2, extract_ev2, insert_ev4, extract_ev4, insert_ev8, extract_ev8): New functions for extracting pmrn/evld/evstd/etc operands. (CRB, CRFD, CRFS, DC, RD): New instruction fields. (CT): Make this equal to RD + 1. (PMRN): New operand. (RA): Update. (EVUIMM, EVUIMM_2, EVUIMM_4, EVUIMM_8): New operands. (WS): Update. (EVSEL, EVSEL_MASK): New instruction form and mask for EVSEL. (ISEL, ISEL_MASK): New instruction form and mask for ISEL. (XISEL, XISEL_MASK): New instruction form and mask for ISEL. (CTX, CTX_MASK): New instruction form and mask for context cache instructions. (UCTX, UCTX_MASK): New instruction form and mask for user context cache instructions. (XC, XC_MASK, XUC, XUC_MASK): New instruction forms. (CLASSIC): New define. (PPCESPE): New define. (PPCISEL, , PPCBRLK, PPCPMR, PPCCHLK, PPCRFMI): New defines for integer select, cache control, branch locking, power management, cache locking and machine check APU instructions, respectively. (efsabs, efsnabs, efsneg, efsadd, efssub, efsmul, efsdiv, efscmpgt, efscmplt, efscmpeq, efststgt, efststlt, efststeq, efscfui, efsctuiz, efscfsi, efscfuf, efscfsf, efsctui, efsctsi, efsctsiz, efsctuf, efsctsf, evaddw, evaddiw, evsubfw, evsubifw, evabs, evneg, evextsb, evextsh, evrndw, evcntlzw, evcntlsw, brinc, evand, evandc, evor, evorc, evxor, eveqv, evnand, evnor, evrlw, evrlwi, evslw, evslwi, evsrws, evsrwu, evsrwis, evsrwiu, evsplati, evsplatfi, evmergehi, evmergelo, evmergehilo, evmergelohi, evcmpgts, evcmpgtu, evcmplts, evcmpltu, evcmpeq, evsel, evldd, evlddx, evldw, evldwx, evldh, evldhx, evlwhe, evlwhex, evlwhou, evlwhoux, evlwhos, evlwhosx, evlwwsplat, evlwwsplatx, evlwhsplat, evlwhsplatx, evlhhesplat, evlhhesplatx, evlhousplat, evlhousplatx, evlhossplat, evlhossplatx, evstdd, evstddx, evstdw, evstdwx, evstdh, evstdhx, evstwwe, evstwwex, evstwwo, evstwwox, evstwhe, evstwhex, evstwho, evstwhox, evfsabs, evfsnabs, evfsneg, evfsadd, evfssub, evfsmul, evfsdiv, evfscmpgt, evfscmplt, evfscmpeq, evfststgt, evfststlt, evfststeq, evfscfui, evfsctuiz, evfscfsi, evfscfuf, evfscfsf, evfsctui, evfsctsi, evfsctsiz, evfsctuf, evfsctsf, evsabs, evsnabs, evsneg, evsadd, evssub, evsmul, evsdiv, evscmpgt, evsgmplt, evsgmpeq, evststgt, evststlt, evststeq, evscfui, evscfsi, evscfuf, evscfsf, evsctui, evsctuiz, evsctsi, evsctsiz, evsctuf, evsctsf, evmhossf, evmhossfa, evmhosmf, evmhosmfa, evmhosmi, evmhosmia, evmhoumi, evmhoumia, evmhessf, evmhessfa, evmhesmf, evmhesmfa, evmhesmi, evmhesmia, evmheumi, evmheumia, evmhossfaaw, evmhossiaaw, evmhosmfaaw, evmhosmiaaw, evmhousiaaw, evmhoumiaaw, evmhessfaaw, evmhessiaaw, evmhesmfaaw, evmhesmiaaw, evmheusiaaw, evmheumiaaw, evmhossfanw, evmhossianw, evmhosmfanw, evmhosmianw, evmhousianw, evmhoumianw, evmhessfanw, evmhessianw, evmhesmfanw, evmhesmianw, evmheusianw, evmheumianw, evmhogsmfaa, evmhogsmiaa, evmhogumiaa, evmhegsmfaa, evmhegsmiaa, evmhegumiaa, evmhogsmfan, evmhogsmian, evmhogumian, evmhegsmfan, evmhegsmian, evmhegumian, evmwhssf, evmwhssfa, evmwhssfaa, evmwhssmaa, evmwhsmfaa, evmwhsmiaa, evmwhusiaa, evmwhumiaa, evmwhssfan, evmwhssian, evmwhsmfan, evmwhsmian, evmwhusian, evmwhumian, evmwhgssfaa, evmwhgsmfaa, evmwhgsmiaa, evmwhgumiaa, evmwhgssfan, evmwhgsmfan, evmwhgsmian, evmwhgumian, evmwhsmf, evmwhsmfa, evmshsmi, evmshsmia, evmshumi, evmshumia, evmmlssf, evmmlssfa, evmwlsmf, evmwlsmfa, evmwlumi, evmwlumia, evmwlssfaaw, evmwlssiaaw, evmwlsmfaaw, evmwlsmiaaw, evmwlusiaaw, evmwlumiaaw, evmwissfanw, evmwissianw, evmwlsmfanw, evmwlsmianw, evmwlusianw, evmwlumianw, evmwssf, evmwssfa, evmwsmf, evmwsmfa, evmwsmi, evmwsmia, evmwumi, evmwumia, evmwssfaa, evmwsmfaa, evmwsmiaa, evmwumiaa, evmwssfan, evmwsmfan, evmwsmian, evmwumian, evaddssiaaw, evaddsmiaaw, evaddusiaaw, evaddumiaaw, evsubfssiaaw, evsubfsmiaaw, evsubfusiaaw, evsubfumiaaw, evmra, evdivws, evdivws): New e500x2 Core Complex instructions. (rfmci): New machine check APU instruction. (isel): New integer select APU instructino. (icbtls, icbtlse, icblc, icblce, dcbtls, dcbtlse, dcbtstls, dcbtstlse, dcblc, dcblce): New cache control APU instructions. (mtspefscr, mfspefscr): New instructions. (mfpmr, mtpmr): New performance monitor APU instructions. (savecontext): New context cache APU instructions. (bblels, bbelr): New branch locking APU instructions. (bblels, bbelr): New instructions. (mftbl, mftbu, mftb): Set as CLASSIC instructions. Add BOOKE alias.
2002-08-13 * m68hc11-opc.c: Update call operand to accept the page definition.Stephane Carrez2-16/+30
Identify instructions that are branches and calls to generate a RL_JUMP relocation.
2002-08-13 * m68hc11-dis.c (print_insn): Take into account 68HC12 memoryStephane Carrez2-7/+86
banks and fix disassembling of call instruction. (print_indexed_operand): New param to tell whether it was an indirect addressing operand (for disassembling call).
2002-08-09Updated Swedish translationNick Clifton2-47/+67
2002-08-09* config/tc-mips.c (macro): Handle a register plus a 16-bitMaciej W. Rozycki2-2/+5
immediate offset in "dla" and "la" expansions. * gas/mips/empic.d: Treat "addiu" and "daddiu" as equivalent when $0 is source. * mips-opc.c (mips_builtin_opcodes): Remove "dla" and "la" as aliases to "daddiu" and "addiu".
2002-07-30Updated TranslationsNick Clifton2-63/+51
2002-07-25New translationsNick Clifton6-221/+363
2002-07-24Update Spanish and Swedish translationsNick Clifton4-151/+176
2002-07-23 * Makefile.am: Run "make dep-am".Alan Modra4-65/+76
* Makefile.in: Regenerate. * po/POTFILES.in: Regenerate.
2002-07-23oops - omitted from previous deltaNick Clifton1-0/+423
2002-07-23update translations.Nick Clifton5-76/+140
2002-07-19Add IP2k GAS and OPCODES support.Nick Clifton13-54/+5352
2002-07-172002-07-17 David Mosberger <davidm@hpl.hp.com>H.J. Lu3-570/+587
* ia64-opc-b.c (bWhc): New macro. (mWhc): Ditto. (OpPaWhcD): Ditto. (ia64_opcodes_b): Correct patterns for indirect call instructions to use 3-bit "wh" field. * ia64-asmtab.c: Regnerate.
2002-07-09 * config/tc-mips.c (macro_build): Handle MIPS16 insns.Thiemo Seufer3-6/+13
(mips_ip): Likewise. * mips.h (INSN_MIPS16): New define. * mips-dis.c (mips_isa_type): Add MIPS16 insn handling. * mips-opc.c (I16): New define. (mips_builtin_opcodes): Make jalx an I16 insn.
2002-06-182002-06-18 Dave Brolley <brolley@redhat.com>Dave Brolley14-2/+17242
* po/POTFILES.in: Add frv-*.[ch]. * disassemble.c (ARCH_frv): New macro. (disassembler): Handle bfd_arch_frv. * configure.in: Support frv_bfd_arch. * Makefile.am (HFILES): Add frv-*.h. (CFILES): Add frv-*.c (ALL_MACHINES): Add frv-*.lo. (CLEANFILES): Add stamp-frv. (FRV_DEPS): New variable. (stamp-frv): New target. (frv-asm.lo): New target. (frv-desc.lo): New target. (frv-dis.lo): New target. (frv-ibld.lo): New target. (frv-opc.lo): New target. (frv-*.[ch]): New files.
generated by cgit v1.1 at 2024-12-22 03:47:47 +0000