Age | Commit message (Collapse) | Author | Files | Lines |
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* d10v-opc.c (d10v_opcodes): Minor fixes to addi and bl.l.
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* d10v-opc.c (d10v_opcodes): Correct 'mv' unit entry to EITHER.
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* makefile.vms: Update for alpha-opc changes.
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(ONE, OP_ONE): #ifdef out; not used.
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* d10v-opc.c (d10v_operands): Added 2 accumulator sub instructions.
Changed subi operand type to treat 0 as 16.
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<rose@netcom.com>.
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* arm-opc.h: (arm_opcodes): Added halfword and sign-extension
memory transfer instructions. Add new format string entries %h and %s.
* arm-dis.c: (print_insn_arm): Provide decoding of the new
formats %h and %s.
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* d10v-opc.c (d10v_operands): Added UNUM4S; a 4-bit accumulator shift.
(d10v_opcodes): Modified accumulator shift instructions to use UNUM4S.
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(print_insn_alpha_vms): Remove.
(print_insn_alpha): Make globally visible. Chose the register
names based on info->flavour.
* disassemble.c: Always return print_insn_alpha for the alpha.
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* d10v-dis.c (dis_long): Handle unknown opcodes.
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* d10v-opc.c: Changes to support signed and unsigned numbers.
All instructions with the same name that have long and short forms
now end in ".l" or ".s". Divs added.
* d10v-dis.c: Changes to support signed and unsigned numbers.
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Tue Jul 23 11:02:53 1996 Martin M. Hunt <hunt@pizza.cygnus.com>
* d10v-dis.c: Change all functions to use info->print_address_func.
end-sanitize-d10v
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<schwab@issan.informatik.uni-dortmund.de>
* m68k-opc.c (m68k_opcodes): Make opcode masks for the ColdFire
move ccr/sr insns more strict so that the disassembler only
selects them when the addressing mode is data register.
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Mon Jul 22 11:25:24 1996 Martin M. Hunt <hunt@pizza.cygnus.com>
* d10v-opc.c (pre_defined_registers): Declare.
* d10v-dis.c (print_operand): Now uses pre_defined_registers
to pick a better name for the registers.
end-sanitize-d10v
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operands for fexpand and fpmerge. From Christian Kuehnke
<Christian.Kuehnke@arbi.informatik.uni-oldenburg.de>.
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* alpha-dis.c (print_insn_alpha): No longer the user-visible
print routine. Take new regnames and cpumask arguments.
Kill the environment variable nonsense.
(print_insn_alpha_osf): New function. Do OSF/1 style regnames.
(print_insn_alpha_vms): New function. Do VMS style regnames.
* disassemble.c (disassembler): Test bfd flavour to pick
between OSF and VMS routines. Default to OSF.
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* configure: Rebuild.
* Makefile.in (install): Use @INSTALL_SHLIB@.
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Wed Jul 17 14:39:05 1996 Martin M. Hunt <hunt@pizza.cygnus.com>
* configure: (bfd_d10v_arch) Add new case.
* configure.in: (bfd_d10v_arch) Add new case.
* d10v-dis.c: New file.
* d10v-opc.c: New file.
* disassemble.c (disassembler) Add entry for d10v.
end-sanitize-d10v
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* m68k-opc.c (m68k_opcodes): Fix bugs in coldfire insns relating
to bcc, trapfl, subxl, and wddata discovered by Andreas Schwab.
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the 8086 instruction set.
* i386-dis.c: General cleanups. Make most things static. Add
prototypes. Get rid of static variables aflags and dflags. Pass
them as args (to almost everything).
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the 8086 instruction set.
* i386-dis.c: General cleanups. Make most things static. Add
prototypes. Get rid of static variables aflags and dflags. Pass
them as args (to almost everything).
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More HMSE.
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More disassembler fixes. HMSE.
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if the next arg is marked with SRC_IN_DST. Gross.
Gross hack so that shift-by-two insns are disassembled correctly.
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we're looking for and find EXR.
So we disassemble andc/orc/xorc with exr correctly.
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if we're looking for KBIT and we don't find it.
So we don't disassemble "inc" instructions as "adds" instructions.
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for L_3 and L_2.
So we only get values in the right range for L_3 (0..7) and L_2 (0..3).
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3bit immediate operands.
So we disassemble bXXX #IMM,@ADDRESS insns correctly.
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<kkaempf@progis.ac-net.de>.
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sparclite instructions.
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#ASI_NUCLEUS_LITTLE. Rename #ASI_AS_IF_USER_{PRIMARY,SECONDARY}_L
to #ASI_AS_IF_USER_{PRIMARY,SECONDARY}_LITTLE.
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Use autoconf-set values.
(docdir, oldincludedir): Removed.
* configure.in (AC_PREREQ): autoconf 2.5 or higher.
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* alpha-opc.c: New file.
* alpha-opc.h: Remove.
* alpha-dis.c: Complete rewrite to use new opcode table.
* configure.in: For bfd_alpha_arch, use alpha-opc.o.
* configure: Rebuild with autoconf 2.10.
* Makefile.in (ALL_MACHINES): Add alpha-opc.o.
(alpha-dis.o): Depend upon $(INCDIR)/opcode/alpha.h, not
alpha-opc.h.
(alpha-opc.o): New target.
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Set imm_added_to_rs1 even if the source and destination register
are not the same.
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to just "mode".
start-sanitize-h8s
* disassemble.c (disassembler): Handle H8/S.
* h8300-dis.c (print_insn_h8300s): New function for H8/S.
end-sanitize-h8s
Even more H8/S goo.
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<sergei@msil.sps.mot.com>.
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* makefile.vms: New file.
* alpha-dis.c (print_insn_alpha): Print lda ra,lit(rz) as mov.
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Set F_FLOAT on other floating point instructions.
PR 355.
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directories.
* configure: Rebuild.
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