| Age | Commit message (Expand) | Author | Files | Lines |
|---|
| 2025-01-17 | aarch64: Fix sve2p1 gating and add missing instructions | Andrew Carlotti | 2 | -333/+457 |
| 2025-01-17 | x86: Add CpuGMISM2 and CpuGMICCS | MayShao-oc | 5 | -2310/+2326 |
| 2025-01-17 | x86/APX: convert runtime special case to build-time one | Jan Beulich | 2 | -4/+18 |
| 2025-01-17 | RISC-V: Use t2 for tail if Zicfilp enabled | Kito Cheng | 1 | -0/+1 |
| 2025-01-17 | RISC-V: Support CFI Zicfiss and Zicfilp instructions and CSR. | Monk Chiang | 1 | -0/+45 |
| 2025-01-17 | RISC-V: Support ssctr/smctr extensions with version 1.0. | Nelson Chu | 1 | -2/+3 |
| 2025-01-17 | x86: Ignore rounding for vcvt[,u]si2sd under r32 and vcvt[,u]dq2pd instead of... | Haochen Jiang | 2 | -4/+3 |
| 2025-01-16 | x86: Support x86 Zhaoxin PadLock PHE2 instructions | MayShao-oc | 7 | -4496/+4546 |
| 2025-01-16 | disassemble_free_powerpc | Alan Modra | 3 | -0/+12 |
| 2025-01-14 | x86: Remove "NE" in mnemonics for convert insns related to AI data types | Haochen Jiang | 4 | -2133/+2133 |
| 2025-01-14 | x86: Rename VCOMSBF16 to VCOMISBF16 | Haochen Jiang | 4 | -2102/+2102 |
| 2025-01-14 | x86: Remove "P" and "NE" in mnemonics for BF16 arithmetic insns | Haochen Jiang | 4 | -2238/+2238 |
| 2025-01-14 | Support Intel AMX-AVX512 | Haochen Jiang | 12 | -1787/+2078 |
| 2025-01-14 | Support Intel AMX-MOVRS | Hu, Lin1 | 11 | -2622/+2830 |
| 2025-01-14 | Support Intel MOVRS | Hu, Lin1 | 10 | -2649/+2792 |
| 2025-01-14 | x86: Remove mod_table pass for MVexSIBMEM | Haochen Jiang | 1 | -28/+18 |
| 2025-01-10 | aarch64: Add support for FEAT_SME_B16B16 feature. | Srinath Parvathaneni | 2 | -311/+535 |
| 2025-01-10 | aarch64: Add support for FEAT_SVE_B16B16 min and max instructions. | Srinath Parvathaneni | 2 | -218/+283 |
| 2025-01-10 | aarch64: Add support for FEAT_SVE_B16B16 feature. | Srinath Parvathaneni | 1 | -14/+14 |
| 2025-01-10 | aarch64: Make VGx4 symbol mandatory for fvdotb and fvdott | Andrew Carlotti | 1 | -2/+2 |
| 2025-01-10 | aarch64: Rename AARCH64_OPND_SME_ZT0_INDEX2_12 | Andrew Carlotti | 3 | -5/+5 |
| 2025-01-10 | aarch64: Remove redundant sme-lutv2 qualifiers and operands | Andrew Carlotti | 6 | -96/+70 |
| 2025-01-10 | aarch64: Fix incorrect gating of sme-lutv2 instructions | Andrew Carlotti | 1 | -4/+10 |
| 2025-01-10 | aarch64: Add support for FEAT_SME_F16F16 fcvt and fcvtl instructions. | Srinath Parvathaneni | 2 | -218/+246 |
| 2025-01-10 | aarch64: Add support for FEAT_SME_F16F16 fmla and fmls instructions. | Srinath Parvathaneni | 2 | -286/+430 |
| 2025-01-10 | aarch64: Add support for FEAT_SME_F16F16 fmops and fmopa instructions. | Srinath Parvathaneni | 2 | -185/+221 |
| 2025-01-10 | x86: Support x86 Zhaoxin PadLockRNG2 instruction | MayShao-oc | 7 | -4432/+4483 |
| 2025-01-09 | RISC-V: Fix display of partial instructions | Charlie Jenkins | 1 | -4/+49 |
| 2025-01-08 | Support Intel AMX-FP8 | Liwei Xu | 7 | -1058/+1179 |
| 2025-01-06 | x86/APX: simplify ENQCMD[,S} opcode table entries | Jan Beulich | 2 | -8/+8 |
| 2025-01-02 | Support Intel AMX-TF32 | Haochen Jiang | 7 | -1090/+1172 |
| 2025-01-02 | Support Intel AMX-TRANSPOSE | Haochen Jiang | 8 | -11454/+11755 |
| 2025-01-01 | Update year range in copyright notice of binutils files | Alan Modra | 272 | -276/+276 |
| 2024-12-24 | arc: add_to_decodelist | Alan Modra | 1 | -147/+124 |
| 2024-12-23 | Support Intel AVX10.2 minmax, vector copy and compare instructions | Haochen Jiang | 8 | -2255/+2562 |
| 2024-12-18 | Support Intel SM4 AVX10.2 extension | Haochen Jiang | 6 | -9281/+9309 |
| 2024-12-16 | Update translations for the opcodes directory for the French and Serbian lang... | Nick Clifton | 2 | -976/+861 |
| 2024-12-09 | PowerPC: Disallow r0 as a base register for the hashst and hashchk insns | Peter Bergner | 1 | -7/+7 |
| 2024-12-09 | LoongArch: Assign DWARF register numbers to register aliases | Lulu Cai | 1 | -0/+32 |
| 2024-12-05 | Support Intel AVX10.2 satcvt instructions | Hu, Lin1 | 7 | -658/+1176 |
| 2024-12-05 | x86: Eliminate unnecessary {evex} prefixes | H.J. Lu | 4 | -11/+29 |
| 2024-12-03 | PowerPC: Add support for RFC02680 - PQC Acceleration Instructions | Surya Kumari Jangala | 1 | -0/+10 |
| 2024-12-03 | Support Intel AVX10.2 BF16 instructions | Kong Lingling | 6 | -2042/+2642 |
| 2024-12-02 | x86: default to not accepting MPX insns | Jan Beulich | 2 | -2/+2 |
| 2024-11-29 | s390: Treat addressing operand sequence as one in disassembler | Jens Remus | 1 | -18/+66 |
| 2024-11-29 | s390: Fix disassembly of optional addressing operands | Jens Remus | 1 | -12/+22 |
| 2024-11-29 | x86: SETcc doesn't permit W suffix | Jan Beulich | 2 | -31/+31 |
| 2024-11-27 | Re: nios2: Remove binutils support for Nios II target | Alan Modra | 1 | -2/+0 |
| 2024-11-26 | nios2: Remove binutils support for Nios II target. | Sandra Loosemore | 8 | -1846/+0 |
| 2024-11-24 | opcodes: fix Werror=format build breaker in opcodes/riscv-dis.c | Tom de Vries | 1 | -1/+1 |
