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path: root/opcodes/v850-opc.c
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1997-09-16Further rearrangements of the opcodes.Nick Clifton1-30/+51
1997-09-16Entries in v850_opcodes reordered to put same named entries adjacent to each ↵Nick Clifton1-5/+13
other.
1997-09-16Add initialisation of the processors field of the v850_opcode structure.Nick Clifton1-169/+162
1997-09-15Fix v850 sanitization.Andrew Cagney1-5/+7
1997-09-03Removed v850 sanitization.Nick Clifton1-0/+4
1997-09-02Removed use of V850_OPERNAD_ADJUST_SHORT_MEMORY.Nick Clifton1-38/+42
Fixed several operand patterns.
1997-08-26Made immediate parameter of MOVHI be unsignedNick Clifton1-1/+1
1997-08-22Updated from specs in HDD-tool-0611 document.Nick Clifton1-28/+37
1997-08-21Moved divh opcodes next to each other.Nick Clifton1-278/+582
1996-12-31Set V850_OPERAND_ADJUST_SHORT_MEMORY flag on sst.{h,w}/sld.{h,w} instructionsMichael Meissner1-2/+3
1996-10-29 * v850-opc.c (D9_RELAX): Renamed from D9, all referencesJeff Law1-13/+20
changed. (v850_operands): Make sure D22 immediately follows D9_RELAX.
1996-10-24 * v850-opc.c (v850_opcodes): Add "jCC" instructions (aliases forJeff Law1-1/+26
"bCC"instructions). Because quantum's code uses jnz, jcc, etc etc etc.
1996-10-03Add missing copyright.Jeff Law1-5/+23
1996-08-31 * v850-dis.c (disassemble): Handle insertion of ',', '[' andJeff Law1-80/+80
']' characters into the output stream. * v850-opc.c (v850_opcodes: Remove size field from all opcodes. Add "memop" field to all opcodes (for the disassembler). Reorder opcodes so that "nop" comes before "mov" and "jr" comes before "jarl". Should give us a functional disassembler.
1996-08-31 * v850-dis.c (v850_reg_names): Define.Jeff Law1-3/+3
(v850_sreg_names, v850_cc_names): Likewise. (disassemble): Very rough cut at printing operands (unformatted). One step at a time. * v850-opc.c (BOP_MASK): Fix. (v850_opcodes): Fix mask for jarl and jr. Bugs exposed by disassembler testing.
1996-08-31 * v850-opc.c (insert_d8_7, extract_d8_7): New functions.Jeff Law1-19/+79
(insert_d8_6, extract_d8_6): New functions. (v850_operands): Rename D7S to D7; operand for D7 is unsigned. Rename D8 to D8_7, use {insert,extract}_d8_7 routines. Add D8_6. (IF4A, IF4B): Use "D7" instead of "D7S". (IF4C, IF4D): Use "D8_7" instead of "D8". (IF4E, IF4F): New. Use "D8_6". (v850_opcodes): Use IF4A/IF4B for sld.b/sst.b. Use IF4C/IF4D for sld.h/sst.h. Use IF4E/IF4F for sld.w/sst.w. So we can assemble sst/sld instructions correctly.
1996-08-31 * v850-opc.c (insert_d16_15, extract_d16_15): New functions.Jeff Law1-11/+45
(v850_operands): Change D16 to D16_15, use special insert/extract routines. New new D16 that uses the generic insert/extract code. (IF7A, IF7B): Use D16_15. (IF7C, IF7D): New. Use D16. (v850_opcodes): Use IF7C and IF7D for ld.b and st.b.
1996-08-31 * v850-opc.c (insert_d9, insert_d22): Slightly improve errorJeff Law1-1/+7
message. Issue an error if the branch offset is odd.
1996-08-31 * v850-opc.c: Add notes about needing special insert/extractJeff Law1-0/+6
for all the load/store insns, except "ld.b" and "st.b". So we don't forget!
1996-08-31 * v850-opc.c (insert_d22, extract_d22): New functions.Jeff Law1-2/+26
(v850_operands): Use insert_d22 and extract_d22 for D22 operands. (insert_d9): Fix range check.
1996-08-31* v850-opc.c (v850_operands): Add V850_OPERAND_SIGNED flagJ.T. Conklin1-2/+2
and set bits field to D9 and D22 operands.
1996-08-30 * v850-opc.c (v850_operands): Define SR2 operand.Jeff Law1-1/+6
(v850_opcodes): "ldsr" uses R1,SR2. ldsr is kinda weird.
1996-08-29 * v850-opc.c (v850_opcodes): Fix opcode specs forJeff Law1-5/+5
sld.w, sst.b, sst.h, sst.w, and nop.
1996-08-28 * v850-opc.c (v850_opcodes): Add null opcode to mark theJeff Law1-5/+13
end of the opcode table. For the simulator
1996-08-23 * v850-opc.c (v850_operands): Define EP operand.Jeff Law1-5/+9
(IF4A, IF4B, IF4C, IF4D): Use EP.
1996-08-23 * v850-opc.c (v850_opcodes): Fix opcode numbers for "mov"Jeff Law1-7/+4
with immediate operand, "movhi". Tweak "ldsr". More fixes.
1996-08-23 * v850-opc.c (v850_opcodes): Get ld.[bhw] and st.[bhw]Jeff Law1-9/+9
correct. Get sld.[bhw] and sst.[bhw] closer.
1996-08-23 * v850-opc.c (v850_operands): "not" is a two byte insn.Jeff Law1-1/+1
1996-08-23 * v850-opc.c (v850_opcodes): Correct bit pattern for setf.Jeff Law1-1/+1
1996-08-23 * v850-opc.c (v850_operands): D16 inserts at offset 16!Jeff Law1-1/+1
1996-08-23 * v850-opc.c (two): Get order of words correct.Jeff Law1-1/+1
1996-08-23 * v850-opc.c (v850_operands): I16 inserts at offset 16!Jeff Law1-1/+1
Should get immediate 16bit operands into the right place
1996-08-23 * v850-opc.c (v850_operands): Add "SR1" and "SR2" for systemJeff Law1-2/+8
register source and destination operands. (v850_opcodes): Use SR1 and SR2 for "ldsr" and "stsr". More parsing fixes.
1996-08-23 * v850-opc.c (v850_opcodes): Fix thinko in "jmp" opcode. FixJeff Law1-1/+1
same thinko in "trap" opcode.
1996-08-23 * v850-opc.c (v850_opcodes): Fix thinko in "jmp" opcode.Jeff Law1-1/+1
1996-08-23 * v850-opc.c (v850_opcodes): Add initializer for size fieldJeff Law1-84/+84
on all opcodes.
1996-08-23 * v850-opc.c (v850_operands): D6 -> DS7. References changed.Jeff Law1-14/+21
Add D8 for 8-bit unsigned field in short load/store insns. (IF4A, IF4D): These both need two registers. (IF4C, IF4D): Define. Use 8-bit unsigned field. (v850_opcodes): For "sld.h", "sld.w", "sst.h", "sst.w", use IF4C & IF4D. For "trap" use I5U, not I5. Add IF1 operand for "ldsr" and "stsr". * v850-opc.c (v850_operands): 3-bit immediate for bit insns is unsigned. Fixing up the parser again.
1996-08-23 * v850-opc.c (v850_operansd): 3-bit immediate for bit insnsJeff Law1-1/+1
is unsigned.
1996-08-23Add V850_OPERAND_SIGNED flag as appropriate, create new unsigned IMM5 operandJ.T. Conklin1-8/+11
1996-08-23 * v850-opc.c (v850_opcodes): Correct short store half (sst.h) andJeff Law1-1/+1
short store word (sst.w).
1996-08-23start writing functions for extracting and inserting unusual operandsJ.T. Conklin1-6/+37
1996-08-23* v850-opc.c (v850_operands): Added insert and extract fields,J.T. Conklin1-13/+15
pointers to functions that handle unusual operand encodings.
1996-08-22 * v850-opc.c (v850_opcodes): Enable "trap".Jeff Law1-2/+0
1996-08-22 * v850-opc.c (v850_opcodes): Fix order of displacementJeff Law1-4/+4
and register for "set1", "clr1", "not1", and "tst1".
1996-08-22minimal setf supportJ.T. Conklin1-1/+3
1996-08-22Stub in load and store insns. Fix order of jarl operandsJ.T. Conklin1-5/+19
1996-08-22Arggh. B3. shift counts are from the start of each half-word apparently.Jeff Law1-1/+1
1996-08-22Fix thinko in B3.Jeff Law1-1/+1
1996-08-22 * v850-opc.c (v850_operands): Add "B3" support.Jeff Law1-7/+9
(v850_opcodes): Fix and enable "set1", "clr1", "not1" and "tst1".
1996-08-22 * v850-ope.c ("jmp"): R1 is only operand.Jeff Law1-1/+1
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