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2024-01-04Update year range in copyright notice of binutils filesAlan Modra1-1/+1
Adds two new external authors to etc/update-copyright.py to cover bfd/ax_tls.m4, and adds gprofng to dirs handled automatically, then updates copyright messages as follows: 1) Update cgen/utils.scm emitted copyrights. 2) Run "etc/update-copyright.py --this-year" with an extra external author I haven't committed, 'Kalray SA.', to cover gas testsuite files (which should have their copyright message removed). 3) Build with --enable-maintainer-mode --enable-cgen-maint=yes. 4) Check out */po/*.pot which we don't update frequently.
2023-01-01Update year range in copyright notice of binutils filesAlan Modra1-1/+1
The newer update-copyright.py fixes file encoding too, removing cr/lf on binutils/bfdtest2.c and ld/testsuite/ld-cygwin/exe-export.exp, and embedded cr in binutils/testsuite/binutils-all/ar.exp string match.
2022-05-10opcodes: remove use of PTRAlan Modra1-1/+1
The non-cgen parts of opcodes. * cr16-dis.c (print_arg): Replace PTR with void *. * crx-dis.c (print_arg): Likewise. * rl78-dis.c (print_insn_rl78_common): Don't use PTR cast. * rx-dis.c (print_insn_rx): Likewise. * visium-dis.c (print_insn_visium): Likewise. * z8k-dis.c (print_insn_z8k): Likewise.
2022-01-02Update year range in copyright notice of binutils filesAlan Modra1-1/+1
The result of running etc/update-copyright.py --this-year, fixing all the files whose mode is changed by the script, plus a build with --enable-maintainer-mode --enable-cgen-maint=yes, then checking out */po/*.pot which we don't update frequently. The copy of cgen was with commit d1dd5fcc38ead reverted as that commit breaks building of bfp opcodes files.
2021-01-01Update year range in copyright notice of binutils filesAlan Modra1-1/+1
2020-09-21rx-dis.c:103:3: suspicious concatenation of string literalsAlan Modra1-8/+8
* rx-dis.c (flag_names): Add missing comma. (register_names, flag_names, double_register_names), (double_register_high_names, double_register_low_names), (double_control_register_names, double_condition_names): Remove trailing commas.
2020-01-01Update year range in copyright notice of binutils filesAlan Modra1-1/+1
2019-10-25Fix potential undefined behaviour in the RX disassembler.Nick Clifton1-1/+1
* rx-dis.c (print_insn_rx): Use parenthesis to ensure correct access to opcodes.op array element.
2019-10-23Fix typo in RX disassembler error messages.Nick Clifton1-10/+10
* rx-dis.c (get_register_name): Fix spelling typo in error message. (get_condition_name, get_flag_name, get_double_register_name) (get_double_register_high_name, get_double_register_low_name) (get_double_control_register_name, get_double_condition_name) (get_opsize_name, get_size_name): Likewise.
2019-10-22Prevent more potential illegal memory accesses in the RX disassembler.Nick Clifton1-16/+34
* rx-dis.c (get_size_name): New function. Provides safe access to name array. (get_opsize_name): Likewise. (print_insn_rx): Use the accessor functions.
2019-10-16Fix potential illegal memory access when disassembling corrupt RX binaries.Nick Clifton1-15/+82
opcodes * rx-dis.c (get_register_name): New function. Provides safe access to name array. (get_condition_name, get_flag_name, get_double_register_name) (get_double_register_high_name, get_double_register_low_name) (get_double_control_register_name, get_double_condition_name): Likewise. (print_insn_rx): Use the accessor functions.
2019-01-13Add RXv3 instructions.Yoshinori Sato1-2/+62
* rx-decode.opc (DSIZE): New. double size. (_ld): New. dmov size attribute. (PSCALE): Add double size. (DCR, DDR, DDRH, DDRL, DCND): New. Double FPU registers. (SCR, SDR, SDRH, SDRL): Likewise. (S2DR, S2CR): Likewise. (SDD): New. double displacement. (DL): New. Set dmov size attribute. (rx_decode_opcode): Add RXv3 instructions. * rx-decode.c: Regenerate. * rx-dis.c (size_names): Add double entry. (opsize_names): Likewise. (double_register_names): New. Double FPU registers. (double_register_high_names): Likewise. (double_register_low_names): Likewise. (double_register_control_names): Likewise. (double_condition_names): dcmp condition. (print_insn_rx): Add bfmov / bfmovz output. Add double FPU output.
2019-01-01Update year range in copyright notice of binutils filesAlan Modra1-1/+1
2018-01-03Update year range in copyright notice of binutils filesAlan Modra1-1/+1
2017-01-02Update year range in copyright notice of all files.Alan Modra1-1/+1
2016-12-12Handle memory error in print_insn_rxYao Qi1-4/+28
Nowadays, memory error in rx disassembly is not handled, so if I start a fresh GDB, and disassemble, (gdb) set architecture rx The target architecture is assumed to be rx (gdb) disassemble 0x0,+4 Dump of assembler code from 0x0 to 0x4: 0x00000000: brk 0x00000001: brk 0x00000002: brk 0x00000003: brk the output is wrong. This patch adds code to call dis->memory_error_func on memory error, and longjmp to print_insn_rx. With this patch applied, (gdb) set architecture rx The target architecture is assumed to be rx (gdb) disassemble 0,+4 Dump of assembler code from 0x0 to 0x4: 0x00000000: Cannot access memory at address 0x0 opcodes: 2016-12-12 Yao Qi <yao.qi@linaro.org> * rx-dis.c: Include <setjmp.h> (struct private): New. (rx_get_byte): Check return value of read_memory_func, and call memory_error_func and OPCODES_SIGLONGJMP on error. (print_insn_rx): Call OPCODES_SIGSETJMP.
2016-01-01Copyright update for binutilsAlan Modra1-1/+1
2015-12-15Add support for RX V2 Instruction SetYoshinori Sato1-2/+2
binutils * readelf.c(get_machine_flags): Add v2 flag. gas * config/rx-defs.h(rx_cpu_type): Add RXV2 type. * config/tc-rx.c(cpu_type_list): New type lookup table. (md_parse_option): Use lookup table for choose cpu. (md_show_usage): Add rxv2 for mcpu option. * doc/c-rx.texi: Likewise. * config/rx-parse.y: Add v2 instructions and ACC register. (rx_check_v2): check v2 type. include/elf * rx.h(E_FLAG_RX_V2): New RXv2 type. include/opcode * rx.h: Add new instructions. opcoes * rx-deocde.opc(rx_decode_opcode): Add new instructions pattern. * rx-dis.c(register_name): Add new register. gas/testsuite * gas/rx/emaca.d: New. * gas/rx/emaca.sm: New. * gas/rx/emsba.d: New. * gas/rx/emsba.sm: New. * gas/rx/emula.d: New. * gas/rx/emula.sm: New. * gas/rx/fadd.d: Add new pattern. * gas/rx/fadd.sm: Add new pattern. * gas/rx/fmul.d: Add new pattern. * gas/rx/fmul.sm: Add new pattern. * gas/rx/fsqrt.d: New. * gas/rx/fsqrt.sm: New. * gas/rx/fsub.d: Add new pattern. * gas/rx/fsub.sm: Add new pattern. * gas/rx/ftou.d: New. * gas/rx/ftou.sm: New. * gas/rx/maclh.d: New. * gas/rx/maclh.sm: New. * gas/rx/maclo.d: Add new pattern. * gas/rx/maclo.sm: Add new pattern. * gas/rx/macros.inc: Add new register. * gas/rx/movco.d: New. * gas/rx/movco.sm: New. * gas/rx/movli.d: New. * gas/rx/movli.sm: New. * gas/rx/msbhi.d: New. * gas/rx/msbhi.sm: New. * gas/rx/msblh.d: New. * gas/rx/msblh.sm: New. * gas/rx/msblo.d: New. * gas/rx/msblo.sm: New. * gas/rx/mullh.d: New. * gas/rx/mullh.sm: New. * gas/rx/mvfacgu.d: New. * gas/rx/mvfacgu.sm: New. * gas/rx/mvfachi.d: Add new pattern. * gas/rx/mvfachi.sm: Add new pattern. * gas/rx/mvfaclo.d: Add new pattern. * gas/rx/mvfaclo.sm: Add new pattern. * gas/rx/mvfacmi.d: Add new pattern. * gas/rx/mvfacmi.sm: Add new pattern. * gas/rx/mvfc.d: Add new pattern. * gas/rx/mvtacgu.d: New. * gas/rx/mvtacgu.sm: New. * gas/rx/mvtc.d: Add new pattern. * gas/rx/popc.d: Add new pattern. * gas/rx/pushc.d: Add new pattern. * gas/rx/racl.d: New. * gas/rx/racl.sm: New. * gas/rx/racw.d: Add new pattern. * gas/rx/racw.sm: Add new pattern. * gas/rx/rdacl.d: New. * gas/rx/rdacl.sm: New. * gas/rx/rdacw.d: New. * gas/rx/rdacw.sm: New. * gas/rx/rx.exp: Add option. * gas/rx/stnz.d: Add new pattern. * gas/rx/stnz.sm: Add new pattern. * gas/rx/stz.d: Add new pattern. * gas/rx/stz.sm: Add new pattern. * gas/rx/utof.d: New. * gas/rx/utof.sm: New.
2015-11-17Fix the disassembly of conditional instructions will illegal condition ↵Nick Clifton1-1/+1
selections. * rx-dis.c (condition_names): Replace always and never with invalid, since the always/never conditions can never be legal.
2015-11-02Fix disassembly of RX zero-offset register indirect instructions.Nick Clifton1-5/+5
opcode * rx.h (enum RX_Operand_Type): Add RX_Operand_Zero_Indirect. opcodes * rx-decode.opc (rx_disp): If the displacement is zero, set the type to RX_Operand_Zero_Indirect. * rx-decode.c: Regenerate. * rx-dis (print_insn): Handle RX_Operand_Zero_Indirect. gas * config/rx-parse.y: Allow zero value for 5-bit displacements. tests * gas/rx/mov.sm: Add tests for zero offset indirect moves. * gas/rx/mov.d: Update expected output.
2015-09-22Enhance the RX disassembler to detect and report bad instructions.Nick Clifton1-8/+25
opcode * rx.h (enum RX_Size): Add RX_Bad_Size entry. opcodes * rx-decode.opc (bwl): Use RX_Bad_Size. (sbwl): Likewise. (ubwl): Likewise. Rename to ubw. (uBWL): Rename to uBW. Replace all references to uBWL with uBW. * rx-decode.c: Regenerate. * rx-dis.c (size_names): Add entry for RX_Bad_Size. (opsize_names): Likewise. (print_insn_rx): Detect and report RX_Bad_Size.
2015-01-02ChangeLog rotatation and copyright year updateAlan Modra1-1/+1
2014-03-05Update copyright yearsAlan Modra1-1/+1
2012-05-18 * arc-dis.c: Include sysdep.h first, remove some redundant includes.Alan Modra1-1/+2
* bfin-dis.c: Likewise. * i860-dis.c: Likewise. * ia64-dis.c: Likewise. * ia64-gen.c: Likewise. * m68hc11-dis.c: Likewise. * mmix-dis.c: Likewise. * msp430-dis.c: Likewise. * or32-dis.c: Likewise. * rl78-dis.c: Likewise. * rx-dis.c: Likewise. * tic4x-dis.c: Likewise. * tilegx-opc.c: Likewise. * tilepro-opc.c: Likewise. * rx-decode.c: Regenerate.
2011-01-12* rx-dis.c (print_insn_rx): Support RX_Operand_TwoReg.DJ Delorie1-0/+1
2009-11-05[opcodes]DJ Delorie1-1/+1
* rx-decode.opc (rx_decode_opcode) (mvtipl): Add. (mvtcp, mvfcp, opecp): Remove. * rx-decode.c: Regenerate. * rx-dis.c (cpen): Remove. [gas] * config/rx-parse.y (MVTIPL): Update bit pattern. (cpen): Remove. [include/opcode] * rx.h (rx_decode_opcode) (mvtipl): Add. (mvtcp, mvfcp, opecp): Remove.
2009-09-29bfdNick Clifton1-0/+199
* Makefile.am (ALL_MACHINES): Add cpu-rx.lo. (ALL_MACHINES_CFILES): Add cpu-rx.c. (BFD32_BACKENDS): Add elf32-rx.lo. (BFD32_BACKENDS_CFILES): Add elf32-rx.c. * archures.c (bfd_architecture): Add bfd_arch_rx and bfd_mach_rx. Export bfd_rx_arch. (bfd_archures_list): Add bfd_rx_arch. * config.bfd: Add entry for rx-*-elf. * configure.in: Add entries for bfd_elf32_rx_le_vec and bfd_elf32_rx_be_vec. * reloc.c: Add RX relocations. * targets.c: Add RX target vectors. * Makefile.in: Regenerate. * bfd-in2.h: Regenerate. * configure: Regenerate. * libbfd.h: Regenerate. * cpu-rx.c: New file. * elf32-rx.c: New file. binutils * readelf.c: Add support for RX target. * MAINTAINERS: Add DJ and NickC as maintainers for RX. gas * Makefile.am: Add RX target. * configure.in: Likewise. * configure.tgt: Likewise. * read.c (do_repeat_with_expander): New function. * read.h: Provide a prototype for do_repeat_with_expander. * doc/Makefile.am: Add RX target documentation. * doc/all.texi: Likewise. * doc/as.texinfo: Likewise. * Makefile.in: Regenerate. * NEWS: Mention support for RX architecture. * configure: Regenerate. * doc/Makefile.in: Regenerate. * config/rx-defs.h: New file. * config/rx-parse.y: New file. * config/tc-rx.h: New file. * config/tc-rx.c: New file. * doc/c-rx.texi: New file. gas/testsuite * gas/rx: New directory. * gas/rx/*: New set of test cases. * gas/elf/section2.e-rx: New expected output file. * gas/all/gas.exp: Add support for RX target. * gas/elf/elf.exp: Likewise. * gas/lns/lns.exp: Likewise. * gas/macros/macros.exp: Likewise. include * dis-asm.h: Add prototype for print_insn_rx. include/elf * rx.h: New file. include/opcode * rx.h: New file. ld * Makefile.am: Add rules to build RX emulation. * configure.tgt: Likewise. * NEWS: Mention support for RX architecture. * Makefile.in: Regenerate. * emulparams/elf32rx.sh: New file. * emultempl/rxelf.em: New file. opcodes * Makefile.am: Add RX files. * configure.in: Add support for RX target. * disassemble.c: Likewise. * Makefile.in: Regenerate. * configure: Regenerate. * opc2c.c: New file. * rx-decode.c: New file. * rx-decode.opc: New file. * rx-dis.c: New file.
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