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2020-01-01Update year range in copyright notice of binutils filesAlan Modra1-1/+1
2019-01-01Update year range in copyright notice of binutils filesAlan Modra1-1/+1
2018-01-03Update year range in copyright notice of binutils filesAlan Modra1-1/+1
2017-05-24Move print_insn_XXX to an opcodes internal headerYao Qi1-1/+1
With the changes done in previous patches, print_insn_XXX functions don't have to be external visible out of opcodes, because both gdb and objdump select disassemblers through a single interface. This patch moves these print_insn_XXX declarations from include/dis-asm.h to opcodes/disassemble.h, which is a new header added by this patch. include: 2017-05-24 Yao Qi <yao.qi@linaro.org> * dis-asm.h: Move some function declarations to opcodes/disassemble.h. opcodes: 2017-05-24 Yao Qi <yao.qi@linaro.org> * alpha-dis.c: Include disassemble.h, don't include dis-asm.h. * avr-dis.c, bfin-dis.c, cr16-dis.c: Likewise. * crx-dis.c, d10v-dis.c, d30v-dis.c: Likewise. * disassemble.c, dlx-dis.c, epiphany-dis.c: Likewise. * fr30-dis.c, ft32-dis.c, h8300-dis.c, h8500-dis.c: Likewise. * hppa-dis.c, i370-dis.c, i386-dis.c: Likewise. * i860-dis.c, i960-dis.c, ip2k-dis.c: Likewise. * iq2000-dis.c, lm32-dis.c, m10200-dis.c: Likewise. * m10300-dis.c, m32r-dis.c, m68hc11-dis.c: Likewise. * m68k-dis.c, m88k-dis.c, mcore-dis.c: Likewise. * metag-dis.c, microblaze-dis.c, mmix-dis.c: Likewise. * moxie-dis.c, msp430-dis.c, mt-dis.c: * nds32-dis.c, nios2-dis.c, ns32k-dis.c: Likewise. * or1k-dis.c, pdp11-dis.c, pj-dis.c: Likewise. * ppc-dis.c, pru-dis.c, riscv-dis.c: Likewise. * rl78-dis.c, s390-dis.c, score-dis.c: Likewise. * sh-dis.c, sh64-dis.c, tic30-dis.c: Likewise. * tic4x-dis.c, tic54x-dis.c, tic6x-dis.c: Likewise. * tic80-dis.c, tilegx-dis.c, tilepro-dis.c: Likewise. * v850-dis.c, vax-dis.c, visium-dis.c: Likewise. * w65-dis.c, wasm32-dis.c, xc16x-dis.c: Likewise. * xgate-dis.c, xstormy16-dis.c, xtensa-dis.c: Likewise. * z80-dis.c, z8k-dis.c: Likewise. * disassemble.h: New file.
2017-05-24Use disassemble.c:disassembler select rl78 disassemblerYao Qi1-1/+5
This patch changes rl78 to let disassble.c:disassembler select disassembler. rl78_get_disassembler doesn't handle the case that abfd is NULL, so this patch also fix it. gdb: 2017-05-24 Yao Qi <yao.qi@linaro.org> * rl78-tdep.c (rl78_gdbarch_init): Don't call set_gdbarch_print_insn. opcodes: 2017-05-24 Yao Qi <yao.qi@linaro.org> * rl78-dis.c (rl78_get_disassembler): If parameter abfd is NULL, set cpu to E_FLAG_RL78_ANY_CPU.
2017-01-02Update year range in copyright notice of all files.Alan Modra1-1/+1
2016-12-12Handle memory error in print_insn_rl78_commonYao Qi1-4/+28
Nowadays, memory error in rl78 disassembly is not handled, so if I start a fresh GDB, and disassemble, (gdb) set architecture rl78 The target architecture is assumed to be rl78 (gdb) disassemble 0x0,+4 Dump of assembler code from 0x0 to 0x4: 0x00000000: nop 0x00000001: nop 0x00000002: nop 0x00000003: nop the output is wrong. This patch adds code to call dis->memory_error_func on memory error, and longjmp to print_insn_rl78_common. With this patch applied, (gdb) set architecture rl78 The target architecture is assumed to be rl78 (gdb) disassemble 0,+4 Dump of assembler code from 0x0 to 0x4: 0x00000000: Cannot access memory at address 0x0 opcodes: 2016-12-12 Yao Qi <yao.qi@linaro.org> * rl78-dis.c: Include <setjmp.h>. (struct private): New. (rl78_get_byte): Check return value of read_memory_func, and call memory_error_func and OPCODES_SIGLONGJMP on error. (print_insn_rl78_common): Call OPCODES_SIGJMP.
2016-03-01Fix typo in print_insn_rl78_common function.Nick Clifton1-1/+2
PR target/19747 * rl78-dis.c (print_insn_rl78_common): Fix typo.
2016-01-14Fix display of RL78 MOVW instructions that use the stack pointer.Nick Clifton1-1/+13
* rl78-decode.opc (rl78_decode_opcode): Add 's' operand to movw instructions that can support stack pointer operations. * rl78-decode.c: Regenerate. * rl78-dis.c: Fix display of stack pointer in MOVW based instructions. * testsuite/gas/rl78/sp-relative-movw.s: New test. * testsuite/gas/rl78/sp-relative-movw.d: Expected disassembly. * testsuite/gas/rl78/rl78.exp: Run the new test.
2016-01-01Copyright update for binutilsAlan Modra1-1/+1
2015-10-27Display system registers by their names when disassembling RL78 instructions.Vinay Kumar1-0/+12
PR binutils/19158 opcodes * rl78-decode.opc: Add 's' print operator to instructions that access system registers. * rl78-decode.c: Regenerate. * rl78-dis.c (print_insn_rl78_common): Decode all system registers. tests * gas/rl78/pr19158.s: New test source file. * gas/rl78/pr19158.d: New test case. * gas/rl78/rl78.exp: Run the new test.
2015-08-12Remove trailing spaces in opcodesH.J. Lu1-2/+2
2015-04-30Make RL78 disassembler and simulator respect ISA for mul/divDJ Delorie1-3/+46
[gas] * config/rl78-defs.h (rl78_isa_g10): New. (rl78_isa_g13): New. (rl78_isa_g14): New. * config/rl78-parse.y (ISA_G10): New. (ISA_G13): New. (ISA_G14): New. (MULHU, MULH, MULU, DIVHU, DIVWU, MACHU, MACH): Use them. * config/tc-rl78.c (rl78_isa_g10): New. (rl78_isa_g13): New. (rl78_isa_g14): New. [gdb] * rl78-tdep.c (rl78_analyze_prologue): Pass RL78_ISA_DEFAULT to rl78_decode_opcode [include] * dis-asm.h (print_insn_rl78_g10): New. (print_insn_rl78_g13): New. (print_insn_rl78_g14): New. (rl78_get_disassembler): New. * opcode/rl78.h (RL78_Dis_Isa): New. (rl78_decode_opcode): Add ISA parameter. [opcodes] * disassemble.c (disassembler): Choose suitable disassembler based on E_ABI. * rl78-decode.opc (rl78_decode_opcode): Take ISA parameter. Use it to decode mul/div insns. * rl78-decode.c: Regenerate. * rl78-dis.c (print_insn_rl78): Rename to... (print_insn_rl78_common): ...this, take ISA parameter. (print_insn_rl78): New. (print_insn_rl78_g10): New. (print_insn_rl78_g13): New. (print_insn_rl78_g14): New. (rl78_get_disassembler): New. [sim] * rl78/cpu.c (g14_multiply): New. * rl78/cpu.h (g14_multiply): New. * rl78/load.c (rl78_load): Decode ISA completely. * rl78/main.c (main): Expand -M to include other ISAs. * rl78/rl78.c (decode_opcode): Decode based on ISA. * rl78/trace.c (rl78_disasm_fn): New. (sim_disasm_init): Reset it. (sim_disasm_one): Get correct disassembler for ISA.
2015-02-11Fixes a problem with the RL78 disassembler which would incorrectly ↵Nick Clifton1-1/+1
disassemble [HL+0] as [HL]. * rl78-decode.opc: Add 'a' attribute to instructions that support [HL+0] addressing. * rl78-decode.c: Regenerate. * rl78-dis.c (print_insn_rl78): Display the offset in [HL+0] addresses.
2015-01-02ChangeLog rotatation and copyright year updateAlan Modra1-1/+1
2014-03-05Update copyright yearsAlan Modra1-1/+1
2013-04-10opcodes/Jan Kratochvil1-1/+1
* rl78-dis.c (print_insn_rl78): Use alternative form as a GCC false warning workaround.
2012-08-15* rl78-decode.opc (rl78_decode_opcode): Merge %e and %[01]DJ Delorie1-109/+110
operands, so that data addresses can be corrected when not ES-overridden. * rl78-decode.c: Regenerate. * rl78-dis.c (print_insn_rl78): Make order of modifiers irrelevent. When the 'e' specifier is used on an operand and no ES prefix is provided, adjust address to make it absolute.
2012-05-18 * arc-dis.c: Include sysdep.h first, remove some redundant includes.Alan Modra1-1/+2
* bfin-dis.c: Likewise. * i860-dis.c: Likewise. * ia64-dis.c: Likewise. * ia64-gen.c: Likewise. * m68hc11-dis.c: Likewise. * mmix-dis.c: Likewise. * msp430-dis.c: Likewise. * or32-dis.c: Likewise. * rl78-dis.c: Likewise. * rx-dis.c: Likewise. * tic4x-dis.c: Likewise. * tilegx-opc.c: Likewise. * tilepro-opc.c: Likewise. * rx-decode.c: Regenerate.
2011-11-02[.]DJ Delorie1-0/+327
* configure.ac (rl78-*-*) New case. * configure: Regenerate. [bfd] * Makefile.am (ALL_MACHINES): Add cpu-rl78.lo. (ALL_MACHINES_CFILES): Add cpu-rl78.c. (BFD32_BACKENDS): Add elf32-rl78.lo. (BFD32_BACKENDS_CFILES): Add elf32-rl78.c. (Makefile.in): Regenerate. * archures.c (bfd_architecture): Define bfd_arch_rl78. (bfd_archures_list): Add bfd_rl78_arch. * config.bfd: Add rl78-*-elf. * configure.in: Add bfd_elf32_rl78_vec. * reloc.c (bfd_reloc_code_type): Add BFD_RELOC_RL78_* relocations. * targets.c (bfd_target_vector): Add bfd_elf32_rl78_vec. * Makefile.in: Regenerate. * bfd-in2.h: Regenerate. * configure: Regenerate. * libbfd.h: Regenerate. * cpu-rl78.c: New file. * elf32-rl78.c: New file. [binutils] * readelf.c: Include elf/rl78.h (guess_is_rela): Handle EM_RL78. (dump_relocations): Likewise. (get_machine_name): Likewise. (is_32bit_abs_reloc): Likewise. * NEWS: Mention addition of RL78 support. * MAINTAINERS: Add myself as RL78 port maintainer. [gas] * Makefile.am (TARGET_CPU_CFILES): Add tc-rl78.c. (TARGET_CPU_HFILES): Add rc-rl78.h. (EXTRA_DIST): Add rl78-parse.c and rl78-parse.y. (rl78-parse.c, rl78-parse.h, rl78-parse.o, rl78-defs.h): New rules. * Makefile.in: Regenerate. * configure.in: Add rl78 case. * configure: Regenerate. * configure.tgt: Add rl78 case. * config/rl78-defs.h: New file. * config/rl78-parse.y: New file. * config/tc-rl78.c: New file. * config/tc-rl78.h: New file. * NEWS: Add Renesas RL78. * doc/Makefile.am (c-rl78.texi): New. * doc/Makefile.in: Likewise. * doc/all.texi: Enable it. * doc/as.texi: Add it. [include] * dis-asm.h (print_insn_rl78): Declare. [include/elf] * common.h (EM_RL78, EM_78K0R): New. * rl78.h: New. [include/opcode] * rl78.h: New file. [ld] * Makefile.am (ALL_EMULATION_SOURCES): Add eelf32rl78.c. (+eelf32rl78.c): New rule. * Makefile.in: Regenerate. * configure.tgt: Add rl78-*-* case. * emulparams/elf32rl78.sh: New file. * NEWS: Mention addition of Renesas RL78 support. [opcodes] * Makefile.am (TARGET_LIBOPCODES_CFILES): Add rl78-decode.c and rl78-dis.c. (MAINTAINERCLEANFILES): Add rl78-decode.c. (rl78-decode.c): New rule, built from rl78-decode.opc and opc2c. * Makefile.in: Regenerate. * configure.in: Add bfd_rl78_arch case. * configure: Regenerate. * disassemble.c: Define ARCH_rl78. (disassembler): Add ARCH_rl78 case. * rl78-decode.c: New file. * rl78-decode.opc: New file. * rl78-dis.c: New file.
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