| Age | Commit message (Expand) | Author | Files | Lines |
|---|---|---|---|---|
| 2017-03-15 | RISC-V: Fix assembler for c.li, c.andi and c.addiw | Kito Cheng | 1 | -3/+3 |
| 2017-03-15 | RISC-V: Fix assembler for c.addi, rd can be x0 | Kito Cheng | 1 | -1/+1 |
| 2017-03-14 | RISC-V: Fix [dis]assembly of srai/srli | Andrew Waterman | 1 | -4/+4 |
| 2017-02-15 | Add SFENCE.VMA instruction | Andrew Waterman | 1 | -0/+3 |
| 2017-01-03 | Add support for the Q extension to the RISCV ISA. | Kito Cheng | 1 | -0/+60 |
| 2017-01-02 | Update year range in copyright notice of all files. | Alan Modra | 1 | -1/+1 |
| 2016-12-22 | Avoid creating symbol table entries for registers | Andrew Waterman | 1 | -2/+2 |
| 2016-12-20 | Correct assembler mnemonic for RISC-V aqrl AMOs | Andrew Waterman | 1 | -22/+22 |
| 2016-12-20 | Fix disassembly of RISC-V CSR instructions under -Mno-aliases | Andrew Waterman | 1 | -22/+22 |
| 2016-12-20 | Add canonical JALR for RISC-V | Andrew Waterman | 1 | -0/+3 |
| 2016-12-20 | Formatting changes for RISC-V | Andrew Waterman | 1 | -8/+6 |
| 2016-11-01 | Add support for RISC-V architecture. | Nick Clifton | 1 | -0/+624 |
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index : riscv-gnu-toolchain/gdb.git | |
| Unnamed repository; edit this file 'description' to name the repository. | root |
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