riscv-gnu-toolchain/gdb.git - Unnamed repository; edit this file 'description' to name the repository.

Age	Commit message (Expand)	Author	Files	Lines
2022-10-14	RISC-V: Move standard hints before all instructions	Tsukasa OI	1	-4/+8
2022-10-14	RISC-V: Move certain arrays to riscv-opc.c	Tsukasa OI	1	-0/+13
2022-10-04	RISC-V: Renamed INSN_CLASS for floating point in integer extensions.	Nelson Chu	1	-222/+222
2022-10-03	RISC-V: Move supervisor instructions after all unprivileged ones	Tsukasa OI	1	-32/+32
2022-09-30	RISC-V: Relax "fmv.[sdq]" requirements	Tsukasa OI	1	-3/+3
2022-09-30	RISC-V: drop stray INSN_ALIAS flags	Jan Beulich	1	-3/+3
2022-09-30	RISC-V: re-arrange opcode table for consistent alias handling	Jan Beulich	1	-38/+38
2022-09-23	RISC-V: Add Zawrs ISA extension support	Christoph Müllner	1	-0/+4
2022-09-22	RISC-V: Add T-Head MemPair vendor extension	Christoph Müllner	1	-0/+24
2022-09-22	RISC-V: Add T-Head MemIdx vendor extension	Christoph Müllner	1	-0/+60
2022-09-22	RISC-V: Add T-Head FMemIdx vendor extension	Christoph Müllner	1	-0/+10
2022-09-22	RISC-V: Add T-Head MAC vendor extension	Christoph Müllner	1	-0/+8
2022-09-22	RISC-V: Add T-Head CondMov vendor extension	Christoph Müllner	1	-0/+4
2022-09-22	RISC-V: Add T-Head Bitmanip vendor extension	Christoph Müllner	1	-0/+17
2022-09-22	RISC-V: Add T-Head SYNC vendor extension	Christoph Müllner	1	-0/+7
2022-09-22	RISC-V: Add T-Head CMO vendor extension	Christoph Müllner	1	-0/+25
2022-08-30	RISC-V: Add 'Zmmul' extension in assembler.	Tsukasa OI	1	-13/+13
2022-07-07	RISC-V: Added Zfhmin and Zhinxmin.	Tsukasa OI	1	-63/+63
2022-06-22	RISC-V: Use single h extension to control hypervisor CSRs and instructions.	Nelson Chu	1	-19/+19
2022-05-30	RISC-V: Add zhinx extension supports.	jiawei	1	-56/+56
2022-05-20	RISC-V: Update zfinx implement with zicsr.	Jia-Wei Chen	1	-14/+14
2022-05-20	RISC-V: Remove RV128-only fmv instructions	Tsukasa OI	1	-2/+0
2022-05-17	RISC-V: Added half-precision floating-point v1.0 instructions.	Nelson Chu	1	-0/+65
2022-03-29	RISC-V: correct FCVT.Q.L[U]	Jan Beulich	1	-2/+2
2022-03-18	RISC-V: Cache management instructions	Tsukasa OI	1	-0/+6
2022-03-18	RISC-V: Prefetch hint instructions and operand set	Tsukasa OI	1	-0/+3
2022-02-25	RISC-V: Fix mask for some fcvt instructions	Tsukasa OI	1	-4/+4
2022-01-02	Update year range in copyright notice of binutils files	Alan Modra	1	-1/+1
2021-12-24	RISC-V: Hypervisor ext: support Privileged Spec 1.12	Vineet Gupta	1	-0/+21
2021-12-16	RISC-V: Support svinval extension with frozen version 1.0.	Nelson Chu	1	-0/+7
2021-11-30	RISC-V: Dump vset[i]vli immediate as numbers once vsew or vlmul is reserved.	Nelson Chu	1	-2/+2
2021-11-18	RISC-V: Add instructions and operand set for z[fdq]inx	jiawei	1	-148/+148
2021-11-17	RISC-V: Support rvv extension with released version 1.0.	Nelson Chu	1	-0/+826
2021-11-16	RISC-V: Scalar crypto instructions and operand set.	jiawei	1	-20/+72
2021-10-07	RISC-V: Support aliases for Zbs instructions	Philipp Tomsich	1	-0/+4
2021-10-07	RISC-V: Add support for Zbs instructions	Philipp Tomsich	1	-0/+9
2021-10-07	RISC-V: Split Zb[abc] into commented sections	Philipp Tomsich	1	-0/+6
2021-04-16	RISC-V: compress "addi d,CV,z" to "c.mv d,CV"	Lifang Xia	1	-0/+1
2021-03-16	RISC-V : Support bitmanip-0.93 ZBA/ZBB/ZBC instructions	Kuan-Lin Chen	1	-4/+49
2021-02-19	RISC-V: PR27158, fixed UJ/SB types and added CSS/CL/CS types for .insn.	Nelson Chu	1	-12/+22
2021-02-18	RISC-V: Add bfd/cpu-riscv.h to support all spec versions controlling.	Nelson Chu	1	-87/+0
2021-02-04	RISC-V: Removed the v0.93 bitmanip ZBA/ZBB/ZBC instructions.	Nelson Chu	1	-53/+4
2021-01-15	RISC-V: Indent and GNU coding standards tidy, also aligned the code.	Nelson Chu	1	-710/+707
2021-01-15	RISC-V: Comments tidy and improvement.	Nelson Chu	1	-17/+16
2021-01-07	RISC-V: Add pause hint instruction.	Philipp Tomsich	1	-0/+3
2021-01-07	RISC-V: Support riscv bitmanip frozen ZBA/ZBB/ZBC instructions (v0.93).	Claire Xenia Wolf	1	-4/+53
2021-01-01	Update year range in copyright notice of binutils files	Alan Modra	1	-1/+1
2020-12-10	RISC-V: Add sext.[bh] and zext.[bhw] pseudo instructions.	Nelson Chu	1	-0/+5
2020-12-10	RISC-V: Control fence.i and csr instructions by zifencei and zicsr.	Nelson Chu	1	-20/+20
2020-12-01	RISC-V: Remove the unimplemented extensions.	Nelson Chu	1	-11/+0