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path: root/opcodes/riscv-opc.c
AgeCommit message (Expand)AuthorFilesLines
2018-06-20RISC-V: Accept constant operands in la and llaSebastian Huber1-2/+2
2018-05-08RISC-V: Add missing hint instructions from RV128I.Jim Wilson1-9/+45
2018-03-14RISC-V: Add .insn support.Jim Wilson1-0/+74
2018-01-17RISC-V: Fix bug in prior addi/c.nop patch.Jim Wilson1-1/+1
2018-01-15RISC-V: Add support for addi that compresses to c.nop.Jim Wilson1-0/+8
2018-01-03Update year range in copyright notice of binutils filesAlan Modra1-1/+1
2017-12-20RISC-V: Add compressed instruction hints, and a few misc cleanups.Jim Wilson1-13/+35
2017-12-13Add missing RISC-V fsrmi and fsflagsi instructions.Jim Wilson1-0/+4
2017-10-24RISC-V: Fix disassembly of c.addi4spn, c.addi16sp, c.lui when imm=0Andrew Waterman1-7/+23
2017-09-27Add support for the new names of the RISC-V fmv.x.s and fmv.s.x instructions,...Nick Clifton1-0/+5
2017-08-22RISC-V: Mark "c.nop" as an aliasPalmer Dabbelt1-1/+1
2017-06-23RISC-V: Fix SLTI disassemblyAndrew Waterman1-2/+2
2017-05-02RISC-V: Change CALL macro to use ra as the temporary address registerMichael Clark1-1/+1
2017-03-15RISC-V: Fix assembler for c.li, c.andi and c.addiwKito Cheng1-3/+3
2017-03-15RISC-V: Fix assembler for c.addi, rd can be x0Kito Cheng1-1/+1
2017-03-14RISC-V: Fix [dis]assembly of srai/srliAndrew Waterman1-4/+4
2017-02-15Add SFENCE.VMA instructionAndrew Waterman1-0/+3
2017-01-03Add support for the Q extension to the RISCV ISA.Kito Cheng1-0/+60
2017-01-02Update year range in copyright notice of all files.Alan Modra1-1/+1
2016-12-22Avoid creating symbol table entries for registersAndrew Waterman1-2/+2
2016-12-20Correct assembler mnemonic for RISC-V aqrl AMOsAndrew Waterman1-22/+22
2016-12-20Fix disassembly of RISC-V CSR instructions under -Mno-aliasesAndrew Waterman1-22/+22
2016-12-20Add canonical JALR for RISC-VAndrew Waterman1-0/+3
2016-12-20Formatting changes for RISC-VAndrew Waterman1-8/+6
2016-11-01Add support for RISC-V architecture.Nick Clifton1-0/+624