riscv-gnu-toolchain/gdb.git - Unnamed repository; edit this file 'description' to name the repository.

Age	Commit message (Expand)	Author	Files	Lines
2020-02-19	RISC-V: Convert the ADD/ADDI to the compressed MV/LI if RS1 is zero.	Jim Wilson	1	-0/+2
2020-01-01	Update year range in copyright notice of binutils files	Alan Modra	1	-1/+1
2019-11-12	RISC-V: Support the INSN_CLASS.F. classes for .insn directive.	Jim Wilson	1	-60/+60
2019-09-17	RISC-V: Gate opcode tables by enum rather than string.	Jim Wilson	1	-658/+658
2019-07-30	RISC-V: Fix minor issues with FP csr instructions.	Jim Wilson	1	-16/+16
2019-07-05	Kito's 5-part patch set to improve .insn support.	Jim Wilson	1	-4/+26
2019-02-08	RISC-V: Compress 3-operand beq/bne against x0.	Jim Wilson	1	-0/+2
2019-01-01	Update year range in copyright notice of binutils files	Alan Modra	1	-1/+1
2018-12-07	RISC-V: Fix 4-arg add parsing.	Jim Wilson	1	-1/+1
2018-11-29	RISC-V: Add missing c.unimp instruction.	Jim Wilson	1	-1/+2
2018-11-27	RISC-V: Add .insn CA support.	Jim Wilson	1	-2/+7
2018-10-02	RISC-V: Add fence.tso instruction	Palmer Dabbelt	1	-0/+1
2018-09-17	RISC-V: bge[u] should get higher priority than ble[u].	Jim Wilson	1	-2/+2
2018-08-31	RISC-V: Correct the requirement of compressed floating point instructions	Jim Wilson	1	-16/+16
2018-08-30	RISC-V: Allow instruction require more than one extension	Jim Wilson	1	-629/+629
2018-07-30	RISC-V: Set insn info fields correctly when disassembling.	Jim Wilson	1	-178/+178
2018-06-20	RISC-V: Accept constant operands in la and lla	Sebastian Huber	1	-2/+2
2018-05-08	RISC-V: Add missing hint instructions from RV128I.	Jim Wilson	1	-9/+45
2018-03-14	RISC-V: Add .insn support.	Jim Wilson	1	-0/+74
2018-01-17	RISC-V: Fix bug in prior addi/c.nop patch.	Jim Wilson	1	-1/+1
2018-01-15	RISC-V: Add support for addi that compresses to c.nop.	Jim Wilson	1	-0/+8
2018-01-03	Update year range in copyright notice of binutils files	Alan Modra	1	-1/+1
2017-12-20	RISC-V: Add compressed instruction hints, and a few misc cleanups.	Jim Wilson	1	-13/+35
2017-12-13	Add missing RISC-V fsrmi and fsflagsi instructions.	Jim Wilson	1	-0/+4
2017-10-24	RISC-V: Fix disassembly of c.addi4spn, c.addi16sp, c.lui when imm=0	Andrew Waterman	1	-7/+23
2017-09-27	Add support for the new names of the RISC-V fmv.x.s and fmv.s.x instructions,...	Nick Clifton	1	-0/+5
2017-08-22	RISC-V: Mark "c.nop" as an alias	Palmer Dabbelt	1	-1/+1
2017-06-23	RISC-V: Fix SLTI disassembly	Andrew Waterman	1	-2/+2
2017-05-02	RISC-V: Change CALL macro to use ra as the temporary address register	Michael Clark	1	-1/+1
2017-03-15	RISC-V: Fix assembler for c.li, c.andi and c.addiw	Kito Cheng	1	-3/+3
2017-03-15	RISC-V: Fix assembler for c.addi, rd can be x0	Kito Cheng	1	-1/+1
2017-03-14	RISC-V: Fix [dis]assembly of srai/srli	Andrew Waterman	1	-4/+4
2017-02-15	Add SFENCE.VMA instruction	Andrew Waterman	1	-0/+3
2017-01-03	Add support for the Q extension to the RISCV ISA.	Kito Cheng	1	-0/+60
2017-01-02	Update year range in copyright notice of all files.	Alan Modra	1	-1/+1
2016-12-22	Avoid creating symbol table entries for registers	Andrew Waterman	1	-2/+2
2016-12-20	Correct assembler mnemonic for RISC-V aqrl AMOs	Andrew Waterman	1	-22/+22
2016-12-20	Fix disassembly of RISC-V CSR instructions under -Mno-aliases	Andrew Waterman	1	-22/+22
2016-12-20	Add canonical JALR for RISC-V	Andrew Waterman	1	-0/+3
2016-12-20	Formatting changes for RISC-V	Andrew Waterman	1	-8/+6
2016-11-01	Add support for RISC-V architecture.	Nick Clifton	1	-0/+624