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2023-01-01Update year range in copyright notice of binutils filesAlan Modra1-1/+1
The newer update-copyright.py fixes file encoding too, removing cr/lf on binutils/bfdtest2.c and ld/testsuite/ld-cygwin/exe-export.exp, and embedded cr in binutils/testsuite/binutils-all/ar.exp string match.
2022-12-07PowerPC: Add support for RFC02655 - Saturating Subtract InstructionPeter Bergner1-0/+9
opcodes/ * ppc-opc.c (XOL): New define. (XOL_MASK): Likewise. (powerpc_opcodes): Add subfus, subfus., subwus, subwus., subdus, subdus. gas/ * testsuite/gas/ppc/rfc02655.s: New test. * testsuite/gas/ppc/rfc02655.d: Likewise * testsuite/gas/ppc/future-raw.s: Likewise. * testsuite/gas/ppc/future-raw.d: Likewise. * testsuite/gas/ppc/ppc.exp: Run them.
2022-12-07PowerPC: Add support for RFC02656 - Enhanced Load Store with Length InstructionsPeter Bergner1-0/+13
opcodes/ * ppc-opc.c (PPCVSXF): New define. (powerpc_opcodes): Add lxvrl, lxvrll, lxvprl, lxvprll, stxvrl, stxvrll, stxvprl, stxvprl. gas/ * testsuite/gas/ppc/rfc02656.s: New test. * testsuite/gas/ppc/rfc02656.d: Likewise. * testsuite/gas/ppc/ppc.exp: Run it.
2022-11-12PowerPC64 paddi -MrawAlan Modra1-10/+10
On a testcase like pla 8,foo@pcrel disassembled with -Mpower10 results in 0: 00 00 10 06 pla r8,0 # 0 4: 00 00 00 39 0: R_PPC64_PCREL34 foo but with -Mpower10 -Mraw 0: 00 00 10 06 .long 0x6100000 0: R_PPC64_PCREL34 foo 4: 00 00 00 39 addi r8,0,0 The instruction is unrecognised due to the hack we have in extract_pcrel0 in order to disassemble paddi with RA0=0 and R=1 as pla. I could have just added "&& !(dialect & PPC_OPCODE_RAW)" to the condition in extract_pcrel0 under which *invalid is set, but went for this larger patch that reorders the extended insn pla to the more usual place before its underlying machine insn. (la is after addi because we never disassemble to la.) gas/ * testsuite/gas/ppc/raw.d, * testsuite/gas/ppc/raw.s: Add pla. opcodes/ * ppc-opc.c (extract_pcrel1): Rename from extract_pcrel0 and invert *invalid logic. (PCREL1): Rename from PCREL0. (prefix_opcodes): Sort pla before paddi, adjusting R operand for pla, paddi and psubi.
2022-11-08PowerPC: Add XSP operand definePeter Bergner1-5/+6
opcodes/ * ppc-opc.c (XSP): New define. (powerpc_opcodes) <stxvp, stxvpx, pstxvp>: Use it.
2022-10-27PowerPC: Add support for RFC02658 - MMA+ Outer-Product InstructionsPeter Bergner1-1/+38
gas/ * config/tc-ppc.c (md_assemble): Only check for prefix opcodes. * testsuite/gas/ppc/rfc02658.s: New test. * testsuite/gas/ppc/rfc02658.d: Likewise. * testsuite/gas/ppc/ppc.exp: Run it. opcodes/ * ppc-opc.c (XMSK8, P_GERX4_MASK, P_GERX2_MASK, XX3GERX_MASK): New. (powerpc_opcodes): Add dmxvi8gerx4pp, dmxvi8gerx4, dmxvf16gerx2pp, dmxvf16gerx2, dmxvbf16gerx2pp, dmxvf16gerx2np, dmxvbf16gerx2, dmxvi8gerx4spp, dmxvbf16gerx2np, dmxvf16gerx2pn, dmxvbf16gerx2pn, dmxvf16gerx2nn, dmxvbf16gerx2nn, pmdmxvi8gerx4pp, pmdmxvi8gerx4, pmdmxvf16gerx2pp, pmdmxvf16gerx2, pmdmxvbf16gerx2pp, pmdmxvf16gerx2np, pmdmxvbf16gerx2, pmdmxvi8gerx4spp, pmdmxvbf16gerx2np, pmdmxvf16gerx2pn, pmdmxvbf16gerx2pn, pmdmxvf16gerx2nn, pmdmxvbf16gerx2nn.
2022-10-27PowerPC: Add support for RFC02653 - Dense Math FacilityPeter Bergner1-26/+188
gas/ * config/tc-ppc.c (pre_defined_registers): Add dense math registers. (md_assemble): Check dmr specified in correct operand. * testsuite/gas/ppc/outerprod.s <dmsetaccz, dmxvbf16ger2, dmxvbf16ger2nn, dmxvbf16ger2np, dmxvbf16ger2pn, dmxvbf16ger2pp, dmxvf16ger2, dmxvf16ger2nn, dmxvf16ger2np, dmxvf16ger2pn, dmxvf16ger2pp, dmxvf32ger, dmxvf32gernn, dmxvf32gernp, dmxvf32gerpn, dmxvf32gerpp, dmxvf64ger, dmxvf64gernn, dmxvf64gernp, dmxvf64gerpn, dmxvf64gerpp, dmxvi16ger2, dmxvi16ger2pp, dmxvi16ger2s, dmxvi16ger2spp, dmxvi4ger8, dmxvi4ger8pp, dmxvi8ger4, dmxvi8ger4pp, dmxvi8ger4spp, dmxxmfacc, dmxxmtacc, pmdmxvbf16ger2, pmdmxvbf16ger2nn, pmdmxvbf16ger2np, pmdmxvbf16ger2pn, pmdmxvbf16ger2pp, pmdmxvf16ger2, pmdmxvf16ger2nn, pmdmxvf16ger2np, pmdmxvf16ger2pn, pmdmxvf16ger2pp, pmdmxvf32ger, pmdmxvf32gernn, pmdmxvf32gernp, pmdmxvf32gerpn, pmdmxvf32gerpp, pmdmxvf64ger, pmdmxvf64gernn, pmdmxvf64gernp, pmdmxvf64gerpn, pmdmxvf64gerpp, pmdmxvi16ger2, pmdmxvi16ger2pp, pmdmxvi16ger2s, pmdmxvi16ger2spp, pmdmxvi4ger8, pmdmxvi4ger8pp, pmdmxvi8ger4, pmdmxvi8ger4pp, pmdmxvi8ger4spp>: Add new tests. * testsuite/gas/ppc/outerprod.d: Likewise. * testsuite/gas/ppc/rfc02653.s: New test. * testsuite/gas/ppc/rfc02653.d: Likewise. * testsuite/gas/ppc/ppc.exp: Run it. include/ * opcode/ppc.h (PPC_OPERAND_DMR): Define. Renumber following PPC_OPERAND defines. opcodes/ * ppc-dis.c (print_insn_powerpc): Prepend 'dm' when printing DMR regs. * ppc-opc.c (insert_p2, (extract_p2, (insert_xa5, (extract_xa5, insert_xb5, (extract_xb5): New functions. (insert_xa6a, extract_xa6a, insert_xb6a, extract_xb6a): Disallow operand overlap only on Power10. (DMR, DMRAB, P1, P2, XA5p, XB5p, XDMR_MASK, XDMRDMR_MASK, XX2ACC_MASK, XX2DMR_MASK, XX3DMR_MASK): New defines. (powerpc_opcodes): Add dmmr, dmsetaccz, dmsetdmrz, dmxor, dmxvbf16ger2, dmxvbf16ger2nn, dmxvbf16ger2np, dmxvbf16ger2pn, dmxvbf16ger2pp, dmxvf16ger2, dmxvf16ger2nn, dmxvf16ger2np, dmxvf16ger2pn, dmxvf16ger2pp, dmxvf32ger, dmxvf32gernn, dmxvf32gernp, dmxvf32gerpn, dmxvf32gerpp, dmxvf64ger, dmxvf64gernn, dmxvf64gernp, dmxvf64gerpn, dmxvf64gerpp, dmxvi16ger2, dmxvi16ger2pp, dmxvi16ger2s, dmxvi16ger2spp, dmxvi4ger8, dmxvi4ger8pp, dmxvi8ger4, dmxvi8ger4pp, dmxvi8ger4spp, dmxxextfdmr256, dmxxextfdmr512, dmxxinstdmr256, dmxxinstdmr512, dmxxmfacc, dmxxmtacc, pmdmxvbf16ger2, pmdmxvbf16ger2nn, pmdmxvbf16ger2np, pmdmxvbf16ger2pn, pmdmxvbf16ger2pp, pmdmxvf16ger2, pmdmxvf16ger2nn, pmdmxvf16ger2np, pmdmxvf16ger2pn, pmdmxvf16ger2pp, pmdmxvf32ger, pmdmxvf32gernn, pmdmxvf32gernp, pmdmxvf32gerpn, pmdmxvf32gerpp, pmdmxvf64ger, pmdmxvf64gernn, pmdmxvf64gernp, pmdmxvf64gerpn, pmdmxvf64gerpp, pmdmxvi16ger2, pmdmxvi16ger2pp, pmdmxvi16ger2s, pmdmxvi16ger2spp, pmdmxvi4ger8, pmdmxvi4ger8pp, pmdmxvi8ger4, pmdmxvi8ger4pp, pmdmxvi8ger4spp.
2022-10-16PowerPC se_rfmci and VLE, SPE2 and LSP insns with -manyAlan Modra1-1/+5
I noticed recently that se_rfmci, a VLE mode instruction, was being accepted by non-VLE cpus, and also that se_rfmci by itself in a section did not cause SHF_PPC_VLE to be set. ie. both testcases added by this patch fail without the changes to tc-ppc.c here. Also, VLE, SPE2 and LSP insns were not accepted by the assembler with -many nor were SPE2 and LSP being disassembled with -Many. gas/ * config/tc-ppc.c (ppc_setup_opcodes): Wrap long lines. Add vle_opcodes when PPC_OPCODE_VLE or PPC_OPCODE_ANY. Simplify disassembler index segment checks. Add LSP and SPE2 opcodes when PPC_OPCODE_ANY too. (md_assemble): Correct logic adding PPC_APUINFO_VLE and SHF_PPC_VLE. * testsuite/gas/ppc/se_rfmci.s * testsuite/gas/ppc/se_rfmci.d, * testsuite/gas/ppc/se_rfmci_bad.d: New tests. * testsuite/gas/ppc/ppc.exp: Run them. opcodes/ * ppc-dis.c (print_insn_powerpc): Disassemble SPE2 and LSP insn when -Many. * ppc-opc.c (vle_opcodes <se_rfmci>): Comment.
2022-10-14PowerPC SPE disassembly and testsAlan Modra1-2/+2
Where sub and subf forms of an instruction exist we generally disassemble to the extended insn sub form rather than the underlying machine subf instruction. Do so for SPE evsubw and evsubiw too. spe_ambiguous.d always was a bit too optimistic. There is no sensible way to disassemble identical bytes back to different and original source. Instead change the test to check -Mraw results. gas/ * testsuite/gas/ppc/ppc.exp: Run spe_ambiguous test. * testsuite/gas/ppc/spe.d: Expect evsubw and evsubiw rather than evsubfw and evsubifw. * testsuite/gas/ppc/spe_ambiguous.s: Test evnor form equivalent to evnot. * testsuite/gas/ppc/spe_ambiguous.d: Test Mraw. opcodes/ * ppc-opc.c (powerpc_opcodes): Move evsubw before evsubfw and evsubiw before evsubifw and mark EXT.
2022-10-14e200 LSP supportAlan Modra1-332/+332
It has bothered me for a long time that we have disabled LSP (and SPE) tests. Also the LSP test comment indicating there is something wrong with get_powerpc_dialect. I don't think there is. Decoding of a VLE instruction depends on whether the processor is in VLE mode (some processors support both VLE and standard PPC) which we flag per section with SHF_PPC_VLE for decoding when disassembling. Background: Some versions of powerpc e200 have "Lightweight Signal Processing" support, examples being e200z215 and e200z425. As far as I can tell, LSP and SPE are mutually exclusive. This seems to be borne out by insn encoding, for example LSP "zvaddih" and SPE "evaddw" have the same encoding. So none of the processor descriptions in ppc_opts ought to have both PPC_OPCODE_LSP and PPC_OPCODE_SPE/2, if we want disassembly to work. I also could not find anything to suggest that the LSP insns are enabled only in VLE mode, which means the LSP insns should not be in vle_opcodes. Fix all this by moving the LSP insns to their own table, and add a new e200z2 cpu entry with LSP support, removing LSP from -me200z4 and from -mvle. (Yes, I know, as I said above some of the e200z4 processors have LSP. Others have SPE. It's hard to choose good options. Think of z2 as meaning earlier, z4 as later.) Also add -mlsp to allow adding the LSP insn set. include/ * opcode/ppc.h (lsp_opcodes, lsp_num_opcodes): Declare. (LSP_OP_TO_SEG): Define. binutils/ * doc/binutils.texi: Update ppc docs. gas/ * config/tc-ppc.c (ppc_setup_opcodes): Add lsp opcodes to ppc_hash. * doc/c-ppc.texi: Document e200 and lsp. * testsuite/gas/ppc/lsp-checks.d: Assemble with -me200z2. * testsuite/gas/ppc/lsp.d: Likewise, disassembly too. * testsuite/gas/ppc/ppc.exp: Don't xfail lsp test. opcodes/ * ppc-dis.c (ppc_opts): Add e200z2 and lsp. Don't set PPC_OPCODE_LSP for e200z4 or vle. (ppc_parse_cpu): Mutually exclude LSP and SPE. (LSP_OPCD_SEGS): Define. (lsp_opcd_indices): New array. (disassemble_init_powerpc): Init lsp_opcd_indices. (lookup_lsp): New function. (print_insn_powerpc): Call it. * ppc-opc.c: Include libiberty.h for ARRAY_SIZE and use throughout. (vle_opcodes): Move LSP opcodes to.. (lsp_opcodes): ..here, and sort. (lsp_num_opcodes): New.
2022-09-12ppc: Document the -mfuture and -Mfuture options and make them usablePeter Bergner1-0/+1
The -mfuture and -Mfuture options which are used for adding potential new ISA instructions were not documented. They also lacked a bitmask so new instructions could not be enabled by those options. Fixed. binutils/ * doc/binutils.texi: Document -Mfuture. gas/ * config/tc-ppc.c: Document -mfuture * doc/c-ppc.texi: Likewise. include/ * opcode/ppc.h (PPC_OPCODE_FUTURE): Define. opcodes/ * ppc-dis.c (ppc_opts) <future>: Use it. * ppc-opc.c (FUTURE): Define.
2022-08-11ppc/svp64: support svindex instructionDmitry Selyutin1-0/+15
https://libre-soc.org/openpower/sv/ https://libre-soc.org/openpower/sv/remap/#svindex https://libre-soc.org/openpower/isa/simplev/
2022-08-11ppc/svp64: support svremap instructionDmitry Selyutin1-0/+20
https://libre-soc.org/openpower/sv/ https://libre-soc.org/openpower/sv/remap/#svremap https://libre-soc.org/openpower/isa/simplev/
2022-08-11ppc/svp64: support svshape instructionDmitry Selyutin1-0/+23
https://libre-soc.org/openpower/sv/ https://libre-soc.org/openpower/sv/remap/#svshape https://libre-soc.org/openpower/isa/simplev/
2022-08-11ppc/svp64: support svstep instructionsDmitry Selyutin1-0/+3
https://libre-soc.org/openpower/sv/ https://libre-soc.org/openpower/sv/svstep/ https://libre-soc.org/openpower/isa/simplev/
2022-08-11ppc/svp64: support setvl instructionsDmitry Selyutin1-0/+22
https://libre-soc.org/openpower/sv/ https://libre-soc.org/openpower/sv/setvl/ https://libre-soc.org/openpower/isa/simplev/
2022-08-11ppc/svp64: support LibreSOC architectureDmitry Selyutin1-8/+9
This patch adds support for LibreSOC machine and SVP64 extension flag for PowerPC architecture. SV (Simple-V) is a strict RISC-paradigm Scalable Vector Extension for the Power ISA. SVP64 is the 64-bit Prefixed instruction format implementing SV. Funded by NLnet through EU Grants No: 825310 and 825322, SV is in DRAFT form and is to be publicly submitted via the OpenPOWER Foundation ISA Working Group via the newly-created External RFC Process. For more details, visit https://libre-soc.org.
2022-07-21PowerPC: Create new MMA instruction masks and use themPeter Bergner1-33/+39
The MMA instructions use XX3_MASK|3<<21 as an instruction mask, but that misses the RC bit/bit 31, so if we disassemble a .long that represents an MMA instruction except that it also has bit 31 set, we will erroneously disassemble it to that MMA instruction. We create new masks defines that contain bit 31 so that doesn't happen anymore. opcodes/ * ppc-opc.c (XACC_MASK, XX3ACC_MASK): New defines. (P_GER_MASK, xxmfacc, xxmtacc, xxsetaccz, xvi8ger4pp, xvi8ger4, xvf16ger2pp, xvf16ger2, xvf32gerpp, xvf32ger, xvi4ger8pp, xvi4ger8, xvi16ger2spp, xvi16ger2s, xvbf16ger2pp, xvbf16ger2, xvf64gerpp, xvf64ger, xvi16ger2, xvf16ger2np, xvf32gernp, xvi8ger4spp, xvi16ger2pp, xvbf16ger2np, xvf64gernp, xvf16ger2pn, xvf32gerpn, xvbf16ger2pn, xvf64gerpn, xvf16ger2nn, xvf32gernn, xvbf16ger2nn, xvf64gernn: Use them.
2022-05-25opcodes: introduce BC field; fix iselDmitry Selyutin1-2/+5
Per Power ISA Version 3.1B 3.3.12, isel uses BC field rather than CRB field present in binutils sources. Also, per 1.6.2, BC has the same semantics as BA and BB fields, so this should keep the same flags and mask, only with the different offset. opcodes/ * ppc-opc.c (BC): Define new field, with the same definition as CRB field, but with the PPC_OPERAND_CR_BIT flag present. gas/ * testsuite/gas/ppc/476.d: Update. * testsuite/gas/ppc/a2.d: Update. * testsuite/gas/ppc/e500.d: Update. * testsuite/gas/ppc/power7.d: Update.
2022-03-16Delete PowerPC macro insn supportAlan Modra1-18/+0
Let's hope this stays dead, but it's here as a patch separate from those that removed use of powerpc_macros just in case it needs to be resurrected. include/ * opcode/ppc.h (struct powerpc_macro): Delete declaration. (powerpc_macros, powerpc_num_macros): Likewise.. opcodes/ * ppc-opc.c (powerpc_macros, powerpc_num_macros): Delete. gas/ * config/tc-ppc.c (ppc_macro): Delete function. (ppc_macro_hash): Delete. (ppc_setup_opcodes, md_assemble): Delete macro support.
2022-03-16PowerPC SPE/SPE2 aliases in powerpc_macrosAlan Modra1-30/+27
* ppc-opc.c (powerpc_macros): Move "evsadd", "evssub", "evsabs", "evsnabs", "evsneg", "evsmul", "evsdiv", "evscmpgt", "evsgmplt", "evsgmpeq", "evscfui", "evscfsi", "evscfuf", "evscfsf", "evsctui", "evsctsi", "evsctuf", "evsctsf", "evsctuiz", "evsctsiz", "evststgt", "evststlt", "evststeq".. (powerpc_opcodes): ..to here. (powerpc_macros): Move "evdotphsssi", "evdotphsssia", "evdotpwsssi", and "evdotpwsssia".. (spe2_opcodes): ..to here.
2022-03-16PowerPC VLE extended instructions in powerpc_macrosAlan Modra1-13/+10
This moves VLE insn out of the macro table. "e_slwi" and "e_srwi" already exist in vle_opcodes as distinct instructions rather than encodings of e_rlwinm. opcodes/ * ppc-opc.c (vle_opcodes): Typo fix e_rlwinm operand. Add "e_inslwi", "e_insrwi", "e_rotlwi", "e_rotrwi", "e_clrlwi", "e_clrrwi", "e_extlwi", "e_extrwi", and "e_clrlslwi". (powerpc_macros): Delete same. Delete "e_slwi" and "e_srwi" too. gas/ * testsuite/gas/ppc/vle-simple-5.d: Update.
2022-03-16PowerPC32 extended instructions in powerpc_macrosAlan Modra1-25/+296
As for PowerPC64, move instructions to the main opcode table. opcodes/ * ppc-opc.c (insert_crwn, extract_crwn, insert_elwn, extract_elwn), (insert_erwn, extract_erwn, insert_erwb, extract_erwb), (insert_cslwn, extract_cslwb, insert_ilwb, extract_ilwn), (insert_irwb, extract_irwn, insert_rrwn, extract_rrwn), (insert_slwn, extract_slwn, insert_srwn, extract_srwn): New functions. (CRWn, ELWn, ERWn, ERWb, CSLWb, CSLWn, ILWn, ILWb, IRWn, IRWb), (RRWn, SLWn, SRWn): Define and add powerpc_operands entries. (MMB_MASK, MME_MASK, MSHMB_MASK): Define. (powerpc_opcodes): Add "inslwi", "insrwi", "rotrwi", "clrrwi", "slwi", "srwi", "extlwi", "extrwi", "sli", "sri" and corresponding record (ie. dot suffix) forms. (powerpc_macros): Delete same. gas/ * testsuite/gas/ppc/476.d: Update. * testsuite/gas/ppc/simpshft.d: Update.
2022-03-16PowerPC64 extended instructions in powerpc_macrosAlan Modra1-19/+245
The extended instructions implemented in powerpc_macros aren't used by the disassembler. That means instructions like "sldi r3,r3,2" appear in disassembly as "rldicr r3,r3,2,61", which is annoying since many other extended instructions are shown. Note that some of the instructions moved out of the macro table to the opcode table won't appear in disassembly, because they are aliases rather than a subset of the underlying raw instruction. If enabled, rotrdi, extrdi, extldi, clrlsldi, and insrdi would replace all occurrences of rotldi, rldicl, rldicr, rldic and rldimi. (Or many occurrences in the case of clrlsldi if n <= b was added to the extract functions.) The patch also fixes a small bug in opcode sanity checking. include/ * opcode/ppc.h (PPC_OPSHIFT_SH6): Define. opcodes/ * ppc-opc.c (insert_erdn, extract_erdn, insert_eldn, extract_eldn), (insert_crdn, extract_crdn, insert_rrdn, extract_rrdn), (insert_sldn, extract_sldn, insert_srdn, extract_srdn), (insert_erdb, extract_erdb, insert_csldn, extract_csldb), (insert_irdb, extract_irdn): New functions. (ELDn, ERDn, ERDn, RRDn, SRDn, ERDb, CSLDn, CSLDb, IRDn, IRDb): Define and add associated powerpc_operands entries. (powerpc_opcodes): Add "rotrdi", "srdi", "extrdi", "clrrdi", "sldi", "extldi", "clrlsldi", "insrdi" and corresponding record (ie. dot suffix) forms. (powerpc_macros): Delete same from here. gas/ * config/tc-ppc.c (insn_validate): Don't modify value passed to operand->insert for PPC_OPERAND_PLUS1 when calculating mask. Handle PPC_OPSHIFT_SH6. * testsuite/gas/ppc/prefix-reloc.d: Update. * testsuite/gas/ppc/simpshft.d: Update. ld/ * testsuite/ld-powerpc/elfv2so.d: Update. * testsuite/ld-powerpc/notoc.d: Update. * testsuite/ld-powerpc/notoc3.d: Update. * testsuite/ld-powerpc/tlsdesc2.d: Update. * testsuite/ld-powerpc/tlsget.d: Update. * testsuite/ld-powerpc/tlsget2.d: Update. * testsuite/ld-powerpc/tlsopt5.d: Update. * testsuite/ld-powerpc/tlsopt6.d: Update.
2022-01-02Update year range in copyright notice of binutils filesAlan Modra1-1/+1
The result of running etc/update-copyright.py --this-year, fixing all the files whose mode is changed by the script, plus a build with --enable-maintainer-mode --enable-cgen-maint=yes, then checking out */po/*.pot which we don't update frequently. The copy of cgen was with commit d1dd5fcc38ead reverted as that commit breaks building of bfp opcodes files.
2021-09-25PowerPC: Enable mfppr mfppr32, mtppr and mtppr32 extended mnemonics on POWER5Peter Bergner1-4/+4
SPR 896 and the mfppr mfppr32, mtppr and mtppr32 extended mnemonics were added in ISA 2.03, so enable them on POWER5 and later. opcodes/ * ppc-opc.c (powerpc_opcodes) <mfppr, mfppr32, mtppr, mtppr32>: Enable on POWER5 and later. gas/ * testsuite/gas/ppc/power5.s: New test. * testsuite/gas/ppc/power5.d: Likewise. * testsuite/gas/ppc/ppc.exp: Run it. * testsuite/gas/ppc/power7.s: Remove tests for mfppr, mfppr32, mtppr and mtppr32. * testsuite/gas/ppc/power7.d: Likewise.
2021-06-17powerpc: move cell "or rx,rx,rx" hintsAlan Modra1-5/+5
* ppc-opc.c (powerpc_opcodes): Move cell db*cyc to proper location in table.
2021-05-29PowerPC table driven -Mraw disassemblyAlan Modra1-1605/+1601
opcodes/ * ppc-dis.c (lookup_powerpc): Test deprecated field when -Many. Don't special case PPC_OPCODE_RAW. (lookup_prefix): Likewise. (lookup_vle, lookup_spe2): Similarly. Add dialect parameter and.. (print_insn_powerpc): ..update caller. * ppc-opc.c (EXT): Define. (powerpc_opcodes): Mark extended mnemonics with EXT. (prefix_opcodes, vle_opcodes): Likewise. (XISEL, XISEL_MASK): Add cr field and simplify. (powerpc_opcodes): Use XISEL with extended isel mnemonics and sort all isel variants to where the base mnemonic belongs. Sort dstt, dststt and dssall. gas/ * testsuite/gas/ppc/raw.s, * testsuite/gas/ppc/raw.d: New test. * testsuite/gas/ppc/ppc.exp: Run it.
2021-05-27PowerPC: Add new xxmr and xxlnot extended mnemonicsPeter Bergner1-0/+2
opcodes/ * ppc-opc.c (powerpc_opcodes) <xxmr, xxlnot>: New extended mnemonics. gas/ * testsuite/gas/ppc/vsx.d <xxmr, xxlnot>: Add tests. * testsuite/gas/ppc/vsx.s: Likewise.
2021-04-08PR27684, PowerPC missing mfsprg0 and othersAlan Modra1-4/+5
PR 27684 * ppc-opc.c (powerpc_opcodes): Correct usprg typos, add mfpir.
2021-04-08PR27676, PowerPC missing extended dcbt, dcbtst mnemonicsAlan Modra1-7/+82
Note that this doesn't implement the ISA to the letter regarding dcbtds (and dcbtstds), which says that the TH field may be zero. That doesn't make sense because allowing TH=0 would mean you no long have a dcbtds but rather a dcbtct instruction. I'm interpreting the ISA wording about allowing TH=0 to mean that the TH field of dcbtds is optional (in which case the TH value is 0b1000). opcodes/ PR 27676 * ppc-opc.c (DCBT_EO): Move earlier. (insert_thct, extract_thct, insert_thds, extract_thds): New functions. (powerpc_operands): Add THCT and THDS entries. (powerpc_opcodes): Add dcbtstct, dcbtstds, dcbna, dcbtct, dcbtds. gas/ * testsuite/gas/ppc/pr27676.d, * testsuite/gas/ppc/pr27676.s: New test. * testsuite/gas/ppc/ppc.exp: Run it. * testsuite/gas/ppc/dcbt.d: Update. * testsuite/gas/ppc/power4_32.d: Update.
2021-04-01PR27675, PowerPC missing extended mnemonic mfummcr2Alan Modra1-0/+2
PR 27675 * ppc-opc.c (powerpc_opcodes): Add mfummcr2 and mfmmcr2.
2021-03-25PR27647 PowerPC extended conditional branch mnemonicsAlan Modra1-476/+477
opcodes/ PR 27647 * ppc-opc.c (XLOCB_MASK): Delete. (XLBOBB_MASK, XLBOBIBB_MASK, XLBOCBBB_MASK): Define using XLBH_MASK. (powerpc_opcodes): Accept a BH field on all extended forms of bclr, bclrl, bcctr, bcctrl, bctar, bctarl. gas/ PR 27647 * testsuite/gas/ppc/a2.d: Update expected output. * testsuite/gas/ppc/power8.d: Likewise.
2021-01-09POWER10: Add Return-Oriented Programming instructionsPeter Bergner1-1/+45
POWER10 adds some return-oriented programming (ROP) instructions and this patch adds support for them. You will notice that they are enabled for POWER8 and later, not just POWER10 and later. This is on purpose. This allows the instructions to be added to POWER8 binaries that can be run on POWER8, POWER9 and POWER10 cpus. On POWER8 and POWER9, these instructions just act as nop's. opcodes/ * ppc-opc.c (insert_dw, (extract_dw): New functions. (DW, (XRC_MASK): Define. (powerpc_opcodes) <hashchk, hashchkp, hashst, haststp>: New mnemonics. gas/ * testsuite/gas/ppc/rop-checks.d, * testsuite/gas/ppc/rop-checks.l, * testsuite/gas/ppc/rop-checks.s, * testsuite/gas/ppc/rop.d, * testsuite/gas/ppc/rop.s: New tests. * testsuite/gas/ppc/ppc.exp: Run them.
2021-01-01Update year range in copyright notice of binutils filesAlan Modra1-1/+1
2020-08-19Correct vcmpsq, vcmpuq and xvtlsbb BF fieldAlan Modra1-3/+3
These shouldn't be optional. The record form of vector instructions set CR6, giving an expectation that omitting BF should be the same as specifying CR6. opcodes/ * ppc-opc.c (powerpc_opcodes): Replace OBF with BF for vcmpsq, vcmpuq and xvtlsbb. gas/ * testsuite/gas/ppc/int128.s: Correct vcmpuq. * testsuite/gas/ppc/int128.d: Update. * testsuite/gas/ppc/xvtlsbb.d: Update.
2020-08-18PowerPC: Rename xvcvbf16sp to xvcvbf16spnPeter Bergner1-1/+1
The xvcvbf16sp mnemonic has been renamed to xvcvbf16spn, to be consistent with the other non-signaling conversion instructions which all end with "n". opcodes/ * ppc-opc.c (powerpc_opcodes) <xvcvbf16sp>: Rename from this... <xvcvbf16spn>: ...to this. gas/ * testsuite/gas/ppc/vsx4.s: Update test to use new mnemonic. * testsuite/gas/ppc/vsx4.d: Likewise.
2020-08-11PowerPC CELL cctp*Alan Modra1-4/+7
* ppc-opc.c (powerpc_opcodes): Move cctpl, cctpm and cctph.
2020-08-10Implement missing powerpc mtspr and mfspr extended insnsAlan Modra1-6/+156
* ppc-opc.c (powerpc_opcodes): Add many mtspr and mfspr extended instructions.
2020-08-10Implement missing powerpc extended mnemonicsAlan Modra1-7/+11
gas/ * testsuite/gas/ppc/power8.d, * testsuite/gas/ppc/power8.s: Add miso. * testsuite/gas/ppc/power9.d, * testsuite/gas/ppc/power8.s: Add exser, msgsndu, msgclru. opcodes/ * ppc-opc.c (powerpc_opcodes): Add exser, msgsndu, msgclru. Enable icbt for power5, miso for power8.
2020-08-10Prioritise mtfprd and mtvrd over mtvsrd in PowerPC disassemblyAlan Modra1-2/+2
gas/ * testsuite/gas/ppc/power8.d: Update. * testsuite/gas/ppc/vsx2.d: Update. opcodes/ * ppc-opc.c (powerpc_opcodes): Prioritise mtfprd and mtvrd over mtvsrd, and similarly for mfvsrd.
2020-05-19Power10 dcbf, sync, and wait extensions.Peter Bergner1-26/+226
opcodes/ * ppc-opc.c (insert_ls, extract_ls): Handle 3-bit L fields and new WC values on POWER10 sync, dcbf and wait instructions. (insert_pl, extract_pl): New functions. (L2OPT, LS, WC): Use insert_ls and extract_ls. (LS3): New , 3-bit L for sync. (LS3, L3OPT): New, 3-bit L for sync and dcbf. (SC2, PL): New, 2-bit SC and PL for sync and wait. (XWCPL_MASK, XL3RT_MASK, XSYNCLS_MASK): New instruction masks. (XOPL3, XWCPL, XSYNCLS): New opcode macros. (powerpc_opcodes) <dcbflp, dcbfps, dcbstps pause_short, phwsync, plwsync, stcisync, stncisync, stsync, waitrsv>: New extended mnemonics. <wait>: Enable PL operand on POWER10. <dcbf>: Enable L3OPT operand on POWER10. <sync>: Enable SC2 operand on POWER10. gas/ * testsuite/gas/ppc/power9.s <dcbf, dcbfl, dcbflp>: Add tests. * testsuite/gas/ppc/power9.d: Likewise. * testsuite/gas/ppc/power10.s <dcbf, dcbfps, dcbstps, hwsync, lwsync, pause_short, phwsync, plwsync, ptesync, stcisync, stncisync, stsync, sync, wait, waitrsv>: Add tests. * testsuite/gas/ppc/power10.d: Likewise.
2020-05-11Power10 VSX scalar min-max-compare quad precision operationsAlan Modra1-0/+11
opcodes/ * ppc-opc (powerpc_opcodes): Add xscmpeqqp, xscmpgeqp, xscmpgtqp, xsmaxcqp, xsmincqp. gas/ * testsuite/gas/ppc/scalarquad.d, * testsuite/gas/ppc/scalarquad.s: New test. * testsuite/gas/ppc/ppc.exp: Run it.
2020-05-11Power10 VSX load/store rightmost element operationsAlan Modra1-0/+16
opcodes/ * ppc-opc.c (powerpc_opcodes): Add lxvrbx, lxvrhx, lxvrwx, lxvrdx, stxvrbx, stxvrhx, stxvrwx, stxvrdx. gas/ * testsuite/gas/ppc/rightmost.d, * testsuite/gas/ppc/rightmost.s: New test. * testsuite/gas/ppc/ppc.exp: Run it.
2020-05-11Power10 test lsb by byte operationAlan Modra1-0/+1
opcodes/ * ppc-opc.c (powerpc_opcodes): Add xvtlsbb. gas/ * testsuite/gas/ppc/xvtlsbb.d, * testsuite/gas/ppc/xvtlsbb.s: New test. * testsuite/gas/ppc/ppc.exp: Run it.
2020-05-11Power10 string operationsAlan Modra1-0/+10
opcodes/ * ppc-opc.c (powerpc_opcodes): Add vstribl, vstribr, vstrihl, vstrihr, vclrlb, vclrrb, vstribl., vstribr., vstrihl., vstrihr.. gas/ * testsuite/gas/ppc/stringop.d, * testsuite/gas/ppc/stringop.s: New test. * testsuite/gas/ppc/ppc.exp: Run it.
2020-05-11Power10 Set boolean extensionPeter Bergner1-0/+8
opcodes/ * ppc-opc.c (powerpc_opcodes) <setbc, setbcr, setnbc, setnbcr>: New mnemonics. gas/ * testsuite/gas/ppc/set_bool.d, * testsuite/gas/ppc/set_bool.s: New test. * testsuite/gas/ppc/ppc.exp: Run it.
2020-05-11Power10 bit manipulation operationsAlan Modra1-1/+20
opcodes/ * ppc-opc.c (UIM8, P_U8XX4_MASK): Define. (powerpc_opcodes): Add vgnb, vcfuged, vpextd, vpdepd, vclzdm, vctzdm, cntlzdm, pdepd, pextd, cfuged, cnttzdm. (prefix_opcodes): Add xxeval. gas/ * testsuite/gas/ppc/bitmanip.d, * testsuite/gas/ppc/bitmanip.s: New test. * testsuite/gas/ppc/ppc.exp: Run it.
2020-05-11Power10 VSX PCV generate operationsAlan Modra1-0/+4
opcodes/ * ppc-opc.c (powerpc_opcodes): Add xxgenpcvbm, xxgenpcvhm, xxgenpcvwm, xxgenpcvdm. gas/ * testsuite/gas/ppc/genpcv.d, * testsuite/gas/ppc/genpcv.s: New test. * testsuite/gas/ppc/ppc.exp: Run it.
2020-05-11Power10 VSX Mask Manipulation OperationsAlan Modra1-1/+27
opcodes/ * ppc-opc.c (MP, VXVAM_MASK): Define. (VXVAPS_MASK): Use VXVA_MASK. (powerpc_opcodes): Add mtvsrbmi, vexpandbm, vexpandhm, vexpandwm, vexpanddm, vexpandqm, vextractbm, vextracthm, vextractwm, vextractdm, vextractqm, mtvsrbm, mtvsrhm, mtvsrwm, mtvsrdm, mtvsrqm, vcntmbb, vcntmbh, vcntmbw, vcntmbd. gas/ * testsuite/gas/ppc/maskmanip.d, * testsuite/gas/ppc/maskmanip.s: New test. * testsuite/gas/ppc/ppc.exp: Run it.
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