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* doc/binutils.texi (objdump): Document -Mppcps.
gas/
* config/tc-ppc.c (parse_cpu): Handle "750cl".
(pre_defined_registers): Add "gqr0" to "gqr7", "gqr.0" to "gqr.7".
(md_show_usage): Document -m750cl.
(md_assemble): Handle two delimiters in succession (eg. `),').
* doc/c-ppc.texi (PowerPC-Opts): Document -m750cl.
* testsuite/gas/ppc/ppc.exp: Run ppc70ps dump tests.
* testsuite/gas/ppc/ppc750ps.s: New file.
* testsuite/gas/ppc/ppc750ps.d: Likewise.
include/opcode/
* ppc.h (PPC_OPCODE_PPCPS): New.
opcodes/
* ppc-opc.c (PSW, PSWM, PSQ, PSQM, PSD, MTMSRD_L): New.
(XOPS, XOPS_MASK, XW, XW_MASK): Likewise.
(PPCPS): Likewise.
(powerpc_opcodes): Add all pair singles instructions.
* ppc-dis.c (powerpc_dialect): Handle "ppcps".
(print_ppc_disassembler_options): Document -Mppcps.
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after setting skip_optional.
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(print_insn_powerpc): Use the new operand_value_powerpc and
skip_optional_operands functions to omit or print all optional
operands as a group.
* ppc-opc.c (BFF, W, XFL_L, XWRA_MASK): New.
(XFL_MASK): Delete L and W bits from the mask.
(mtfsfi, mtfsfi.): Replace use of BF with BFF. Relpace use of XRA_MASK
with XWRA_MASK. Use W.
(mtfsf, mtfsf.): Use XFL_L and W.
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* ppc.h (struct powerpc_operand): Replace "bits" with "bitm".
(num_powerpc_operands): Declare.
(PPC_OPERAND_SIGNED et al): Redefine as hex.
(PPC_OPERAND_PLUS1): Define.
opcodes/
* ppc-dis.c (print_insn_powerpc): Adjust for struct powerpc_operand
change.
* ppc-opc.c (powerpc_operands): Replace bit count with bit mask
in all entries. Add PPC_OPERAND_SIGNED to DE entry. Remove
references to following deleted functions.
(insert_bd, extract_bd, insert_dq, extract_dq): Delete.
(insert_ds, extract_ds, insert_de, extract_de): Delete.
(insert_des, extract_des, insert_li, extract_li): Delete.
(insert_nb, insert_rsq, insert_rtq, insert_ev2, extract_ev2): Delete.
(insert_ev4, extract_ev4, insert_ev8, extract_ev8): Delete.
(num_powerpc_operands): New constant.
(XSPRG_MASK): Remove entire SPRG field.
(powerpc_opcodes <bcctre, bcctrel>): Use XLBB_MASK not XLYBB_MASK.
gas/
* messages.c (as_internal_value_out_of_range): Extend to report
errors for values with invalid low bits set.
* config/tc-ppc.c (ppc_setup_opcodes): Check powerpc_operands bitm
fields. Check that operands and opcode fields are disjoint.
(ppc_insert_operand): Check operands using mask rather than bit
count. Check low bits too. Handle PPC_OPERAND_PLUS1. Adjust
insertion code.
(md_apply_fix): Adjust for struct powerpc_operand change.
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* ppc-dis.c (print_ppc_disassembler_options): Note the -M440 can be used.
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* ppc.h (PPC_OPCODE_POWER6): Define.
Adjust whitespace.
gas/
* config/tc-ppc.c (parse_cpu): Handle "-mpower6".
(md_show_usage): Document it.
(ppc_setup_opcodes): Test power6 opcode flag bits.
* doc/c-ppc.texi (PowerPC-Opts): Document "-mpower6".
opcodes/
* ppc-dis.c (powerpc_dialect): Handle power6 option.
(print_ppc_disassembler_options): Mention power6.
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* elf32-arm.c (elf32_arm_check_relocs): Avoid aliasing warnings from
GCC.
(elf32_arm_size_dynamic_sections): Likewise.
* ecofflink.c (bfd_ecoff_debug_one_external): Likewise.
* elf32-hppa.c (elf32_hppa_check_relocs): Likewise.
* elf32-m32r.c (m32r_elf_check_relocs): Likewise.
* elf32-m68k.c (elf_m68k_check_relocs): Likewise.
* elf32-ppc.c (ppc_elf_check_relocs): Likewise.
* elf32-s390.c (elf_s390_check_relocs): Likewise.
(elf_s390_size_dynamic_sections): Likewise.
* elf32-sh.c (sh_elf_check_relocs): Likewise.
* elf64-ppc.c (ppc64_elf_check_relocs, dec_dynrel_count)
(ppc64_elf_size_dynamic_sections): Likewise.
* elf64-s390.c (elf_s390_check_relocs): Likewise.
(elf_s390_size_dynamic_sections): Likewise.
* elfxx-mips.c (_bfd_mips_elf_finish_dynamic_sections): Likewise.
* elfxx-sparc.c (_bfd_sparc_elf_check_relocs): Likewise.
(_bfd_sparc_elf_size_dynamic_sections): Likewise.
* ieee.c (ieee_slurp_section_data): Likewise.
* oasys.c (oasys_slurp_section_data): Likewise.
opcodes/
* ppc-dis.c (struct dis_private): Remove.
(powerpc_dialect): Avoid aliasing warnings.
(print_insn_big_powerpc, print_insn_little_powerpc): Likewise.
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* config/tc-ppc.c (parse_cpu): Add -me300 support.
(md_show_usage): Likewise.
* doc/c-ppc.texi (PowerPC-Opts): Document it.
include/opcode/
* ppc.h (PPC_OPCODE_E300): Define.
opcodes/
* ppc-dis.c (powerpc_dialect): Handle e300.
(print_ppc_disassembler_options): Likewise.
* ppc-opc.c (PPCE300): Define.
(powerpc_opcodes): Mark icbt as available for the e300.
binutils/
* doc/binutils.texi (objdump): Document -M e300.
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bfd:
* elf32-xtensa.c (vsprint_msg): Add format attribute. Fix
format bugs.
* vms.h (_bfd_vms_debug): Add format attribute.
(_bfd_vms_debug, _bfd_hexdump): Fix typos.
binutils:
* bucomm.h (report): Add format attribute.
* dlltool.c (inform): Likewise.
* dllwrap.c (display, inform, warn): Likewise.
* objdump.c (objdump_sprintf): Likewise.
* readelf.c (error, warn): Likewise. Fix format bugs.
gas:
* config/tc-tic30.c (debug): Add format attribute. Fix format
bugs.
include:
* dis-asm.h (fprintf_ftype): Add format attribute.
opcodes:
* arc-dis.c, arm-dis.c, cris-dis.c, crx-dis.c, d10v-dis.c,
d30v-dis.c, fr30-dis.c, h8300-dis.c, h8500-dis.c, i860-dis.c,
ia64-dis.c, ip2k-dis.c, m10200-dis.c, m10300-dis.c,
m88k-dis.c, mcore-dis.c, mips-dis.c, ms1-dis.c, or32-dis.c,
ppc-dis.c, sh64-dis.c, sparc-dis.c, tic4x-dis.c, tic80-dis.c,
v850-dis.c: Fix format bugs.
* ia64-gen.c (fail, warn): Add format attribute.
* or32-opc.c (debug): Likewise.
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(print_ppc_disassembler_options): Document it.
* ppc-opc.c (SCV_LEV): Define.
(LEV): Allow optional operand.
(POWER5): Define.
(powerpc_opcodes): Extend "sc". Adjust "svc" and "svcl". Add
"hrfid", "popcntb", "fsqrtes", "fsqrtes.", "fre" and "fre.".
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BOOKE.
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* ppc-dis.c (print_insn_powerpc): Don't print tabs. Handle
PPC_OPERANDS_GPR_0.
* ppc-opc.c (RA0): Define.
(RAQ, RAL, RAM, RAS, RSQ, RTQ, RSO): Use PPC_OPERAND_GPR_0.
(RAOPT): Rename from RAO. Update all uses.
(powerpc_opcodes): Use RA0 as appropriate. Add "lsdx", "lsdi",
"stsdx", "stsdi", "lmd" and "stmd" insns.
include/opcode/
* ppc.h (PPC_OPERAND_GPR_0): Define. Bump other operand defines.
gas/testsuite/
Update gas/ppc/.
ld/testsuite/
Update ld-powerpc/.
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(powerpc_dialect): Make static. Accept -Many in addition to existing
options. Save dialect in dis_private.
(print_insn_big_powerpc): Retrieve dialect from dis_private.
(print_insn_little_powerpc): Likewise.
(print_insn_powerpc): Call powpc_dialect here. Remove unnecessary
efs/altivec check. Try harder to disassemble if given -Many.
* ppc-opc.c (insert_fxm): Expand comment.
(PPC, PPCCOM, PPC32, PPC64, PPCVEC): Remove PPC_OPCODE_ANY.
(POWER, POWER2, PPCPWR2, POWER32, COM, COM32, M601, PWRCOM): Likewise.
(POWER4): Remove PPCCOM.
(PPCONLY): Don't define. Update all occurrences to PPC.
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Move duplicate mnemonic entries together. Use RS instead of RT on
all mt*.
* ppc-dis.c: Convert to ISO C.
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extraneous ATTRIBUTE_UNUSED.
* ppc-dis.c (print_insn_powerpc): Always pass a valid address to
operand->extract.
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From matthew green <mrg@redhat.com>
* ppc-dis.c (powerpc_dialect): Support `-m500', `-m500x2' and
`-mefs'. Turn off AltiVec for E500 and efs.
(print_insn_powerpc): Don't print an AltiVec instruction if the
dialect is not efs.
* ppc-opc.c (insert_pmrn, extract_pmrn, insert_ev2, extract_ev2,
insert_ev4, extract_ev4, insert_ev8, extract_ev8): New functions
for extracting pmrn/evld/evstd/etc operands.
(CRB, CRFD, CRFS, DC, RD): New instruction fields.
(CT): Make this equal to RD + 1.
(PMRN): New operand.
(RA): Update.
(EVUIMM, EVUIMM_2, EVUIMM_4, EVUIMM_8): New operands.
(WS): Update.
(EVSEL, EVSEL_MASK): New instruction form and mask for EVSEL.
(ISEL, ISEL_MASK): New instruction form and mask for ISEL.
(XISEL, XISEL_MASK): New instruction form and mask for ISEL.
(CTX, CTX_MASK): New instruction form and mask for context cache
instructions.
(UCTX, UCTX_MASK): New instruction form and mask for user context
cache instructions.
(XC, XC_MASK, XUC, XUC_MASK): New instruction forms.
(CLASSIC): New define.
(PPCESPE): New define.
(PPCISEL, , PPCBRLK, PPCPMR, PPCCHLK, PPCRFMI): New
defines for integer select, cache control, branch
locking, power management, cache locking and machine check
APU instructions, respectively.
(efsabs, efsnabs, efsneg, efsadd, efssub, efsmul,
efsdiv, efscmpgt, efscmplt, efscmpeq, efststgt, efststlt,
efststeq, efscfui, efsctuiz, efscfsi, efscfuf, efscfsf,
efsctui, efsctsi, efsctsiz, efsctuf, efsctsf,
evaddw, evaddiw, evsubfw, evsubifw, evabs, evneg, evextsb,
evextsh, evrndw, evcntlzw, evcntlsw, brinc, evand, evandc, evor,
evorc, evxor, eveqv, evnand, evnor, evrlw, evrlwi, evslw, evslwi,
evsrws, evsrwu, evsrwis, evsrwiu, evsplati, evsplatfi, evmergehi,
evmergelo, evmergehilo, evmergelohi, evcmpgts, evcmpgtu, evcmplts,
evcmpltu, evcmpeq, evsel, evldd, evlddx, evldw, evldwx, evldh,
evldhx, evlwhe, evlwhex, evlwhou, evlwhoux, evlwhos, evlwhosx,
evlwwsplat, evlwwsplatx, evlwhsplat, evlwhsplatx, evlhhesplat,
evlhhesplatx, evlhousplat, evlhousplatx, evlhossplat, evlhossplatx,
evstdd, evstddx, evstdw, evstdwx, evstdh, evstdhx, evstwwe,
evstwwex, evstwwo, evstwwox, evstwhe, evstwhex, evstwho, evstwhox,
evfsabs, evfsnabs, evfsneg, evfsadd, evfssub, evfsmul, evfsdiv,
evfscmpgt, evfscmplt, evfscmpeq, evfststgt, evfststlt, evfststeq,
evfscfui, evfsctuiz, evfscfsi, evfscfuf, evfscfsf, evfsctui,
evfsctsi, evfsctsiz, evfsctuf, evfsctsf, evsabs, evsnabs, evsneg,
evsadd, evssub, evsmul, evsdiv, evscmpgt, evsgmplt, evsgmpeq,
evststgt, evststlt, evststeq, evscfui, evscfsi, evscfuf, evscfsf,
evsctui, evsctuiz, evsctsi, evsctsiz, evsctuf, evsctsf, evmhossf,
evmhossfa, evmhosmf, evmhosmfa, evmhosmi, evmhosmia, evmhoumi,
evmhoumia, evmhessf, evmhessfa, evmhesmf, evmhesmfa, evmhesmi,
evmhesmia, evmheumi, evmheumia, evmhossfaaw, evmhossiaaw,
evmhosmfaaw, evmhosmiaaw, evmhousiaaw, evmhoumiaaw, evmhessfaaw,
evmhessiaaw, evmhesmfaaw, evmhesmiaaw, evmheusiaaw, evmheumiaaw,
evmhossfanw, evmhossianw, evmhosmfanw, evmhosmianw, evmhousianw,
evmhoumianw, evmhessfanw, evmhessianw, evmhesmfanw, evmhesmianw,
evmheusianw, evmheumianw, evmhogsmfaa, evmhogsmiaa, evmhogumiaa,
evmhegsmfaa, evmhegsmiaa, evmhegumiaa, evmhogsmfan, evmhogsmian,
evmhogumian, evmhegsmfan, evmhegsmian, evmhegumian, evmwhssf,
evmwhssfa, evmwhssfaa, evmwhssmaa, evmwhsmfaa, evmwhsmiaa,
evmwhusiaa, evmwhumiaa, evmwhssfan, evmwhssian, evmwhsmfan,
evmwhsmian, evmwhusian, evmwhumian, evmwhgssfaa, evmwhgsmfaa,
evmwhgsmiaa, evmwhgumiaa, evmwhgssfan, evmwhgsmfan, evmwhgsmian,
evmwhgumian, evmwhsmf, evmwhsmfa, evmshsmi, evmshsmia, evmshumi,
evmshumia, evmmlssf, evmmlssfa, evmwlsmf, evmwlsmfa, evmwlumi,
evmwlumia, evmwlssfaaw, evmwlssiaaw, evmwlsmfaaw, evmwlsmiaaw,
evmwlusiaaw, evmwlumiaaw, evmwissfanw, evmwissianw, evmwlsmfanw,
evmwlsmianw, evmwlusianw, evmwlumianw, evmwssf, evmwssfa,
evmwsmf, evmwsmfa, evmwsmi, evmwsmia, evmwumi, evmwumia,
evmwssfaa, evmwsmfaa, evmwsmiaa, evmwumiaa, evmwssfan, evmwsmfan,
evmwsmian, evmwumian, evaddssiaaw, evaddsmiaaw, evaddusiaaw,
evaddumiaaw, evsubfssiaaw, evsubfsmiaaw, evsubfusiaaw,
evsubfumiaaw, evmra, evdivws, evdivws): New e500x2 Core Complex
instructions.
(rfmci): New machine check APU instruction.
(isel): New integer select APU instructino.
(icbtls, icbtlse, icblc, icblce, dcbtls, dcbtlse, dcbtstls,
dcbtstlse, dcblc, dcblce): New cache control APU instructions.
(mtspefscr, mfspefscr): New instructions.
(mfpmr, mtpmr): New performance monitor APU instructions.
(savecontext): New context cache APU instructions.
(bblels, bbelr): New branch locking APU instructions.
(bblels, bbelr): New instructions.
(mftbl, mftbu, mftb): Set as CLASSIC instructions. Add BOOKE alias.
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* ppc-opc.c (insert_bdm): Correct description of "at" branch
hints. Test PPC_OPCODE_POWER4 to determine branch hint flavour.
(extract_bdm, insert_bdp, extract_bdp, valid_bo): Likewise.
(BOFM64, BOFP64, BOTM64, BOFP64): Rename to BOFM4, BOFP4 etc.
(BODNZM64, BODNZP64, BODZM64, BODZP64): Likewise.
(PPCCOM32, PPCCOM64): Delete.
(NOPOWER4, POWER4): Define.
(powerpc_opcodes): Replace occurences of PPCCOM32 with NOPOWER4,
and PPCCOM4 with POWER4 so that "at" style branch hint opcodes
are enabled for power4 rather than ppc64.
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specific.
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* doc/binutils.texi (objdump): Document ppc -M options.
gas/ChangeLog
* config/tc-ppc.c (ppc_insert_operand): Pass (ppc_cpu | ppc_size)
to operand->insert.
(md_assemble): Likewise.
gas/testsuite/ChangeLog
* gas/ppc/booke.d: Modify reloc and target matches for powerpc64.
include/opcode/ChangeLog
* ppc.h (struct powerpc_operand <insert, extract>): Add dialect param.
opcodes/ChangeLog
* ppc-opc.c (PPC64): Revert 2001-10-12. Do include PPC_OPCODE_PPC.
(insert_bat, extract_bat, insert_bba, extract_bba,
insert_bd, extract_bd, insert_bdm, extract_bdm,
insert_bdp, extract_bdp, valid_bo,
insert_bo, extract_bo, insert_boe, extract_boe,
insert_ds, extract_ds, insert_de, extract_de,
insert_des, extract_des, insert_li, extract_li,
insert_mbe, extract_mbe, insert_mb6, extract_mb6,
insert_nb, extract_nb, insert_nsi, extract_nsi,
insert_ral, insert_ram, insert_ras,
insert_rbs, extract_rbs, insert_sh6, extract_sh6,
insert_spr, extract_spr, insert_tbr, extract_tbr): Add dialect param.
(extract_bd, extract_bdm, extract_bdp,
extract_ds, extract_des,
extract_li, extract_nsi): Implement sign extension without conditional.
(insert_bdm, extract_bdm,
insert_bdp, extract_bdp, valid_bo): Handle 64 bit branch hints.
(extract_bdm, extract_bdp): Correct 32 bit validation.
(AT1_MASK, AT2_MASK): Define.
(BBOAT_MASK): Define.
(BBOATCB_MASK, BBOAT2CB_MASK, BBOATBI_MASK): Define.
(BOFM64, BOFP64, BOTM64, BOTP64): Define.
(BODNZM64, BODNZP64, BODZM64, BODZP64): Define.
(PPCCOM32, PPCCOM64): Define.
(powerpc_opcodes): Modify existing 32 bit insns with branch hints
and add new patterns to implement 64 bit branches with hints. Move
booke instructions so they match before ppc64.
* ppc-dis.c (powerpc_dialect): Set PPC_OPCODE_64 in dialect for
64 bit default targets, and parse "32" and "64" in options.
Formatting fixes.
(print_insn_powerpc): Pass dialect to operand->extract.
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* config/tc-ppc.c (md_parse_option): New -m7410, -m7450 and -m7455
flags, equivalent to -m7400. New -maltivec to enable AltiVec
instructions. New -mbook64 and -mbooke/-mbooke32 flags to enable
64-bit and 32-bit BookE support, respectively. Change -m403 and
-m405 to set PPC403 option.
(md_show_usage): Adjust for new options.
* doc/all.texi: Set PPC.
* doc/as.texinfo: Add PPC support and pull in c-ppc.texi.
* doc/c-ppc.texi: New file.
* doc/Makefile.am (CPU_DOCS): Add c-ppc.texi.
* doc/Makefile.in: Regenerate.
[gas/testsuite/ChangeLog]
* gas/ppc/booke.s: New test for Motorola BookE.
* gas/ppc/booke.d: New file.
* gas/ppc/ppc.exp: Test booke.s.
[include/opcode/ChangeLog]
* ppc.h (PPC_OPCODE_BOOKE, PPC_OPCODE_403): New opcode flags for
BookE and PowerPC403 instructions.
[opcodes/ChangeLog]
* ppc-opc.c (insert_de, extract_de, insert_des, extract_des): New
instruction field instruction/extraction functions for new BookE
DE form instructions.
(CT): New macro for CT field in an X form instruction.
(DE, DES, DEO, DE_MASK): New macros for DE/DES fields in DE form
instructions.
(PPC64): Don't include PPC_OPCODE_PPC.
(403): New opcode macro for PPC403 processors.
(BOOKE): New opcode macro for BookE processors.
(bce, bcel, bcea, bcela, bclre, bclrel: New BookE instructions.
(bcctre, bcctrel, be, bel, bea, bela, icbt, icbte, lwzxe): Likewise.
(dcbste, lwzuxe, luxe, dcbfe, lbzxe, lwarxe, lbzuxe): Likewise.
(stwcxe, stwxe, stxe, stwuxe, stuxe, stbxe, dcbtste, stbuxe): Likewise.
(mfapidi, dcbte, lhzxe, lhzuxe, lhaxe, lhauxe, subfe64): Likewise.
(subfeo64, adde64, addeo64, sthxe, sthuxe, subfze64): Likewise.
(subfzeo64, addze64, addzeo64, dcbie, subfme64, subfmeo64): Likewise.
(addme64, addmeo64, stdcxe., mcrxr64, lwbrxe, lfsxe, lfsuxe): Likewise.
(lfdxe, lfduxe, stwbrxe, stfsxe, stfsuxe, stfdxe, dcbae): Likewise.
(stfduxe, tlbivax, tlbivaxe, lhbrxe, ldxe, lduxe, tlbsx): Likewise.
(tlbsxe, sthbrxe, stdxe, stduxe, icbie, stfiwxe, dcbze, lbze): Likewise.
(lbzue, ldue, lhze, lhzue, lhae, lhaue, lwze, lwzue): Likewise.
(stbe, stbue, sthe, sthue, stwe, stwue, lfse, lfsue, lfde): Likewise.
(lfdue, stde, stdue, stfse, stfsue, stfde, stfdue): Likewise.
* ppc-dis.c (print_insn_big_powerpc, print_insn_little_powerpc): Look
for a disassembler option of `booke', `booke32' or `booke64' to enable
BookE support in the disassembler.
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vector unit operands.
(VX, VX_MASK, VXA, VXA_MASK, VXR, VXR_MASK): New macros, for vector
unit instruction formats.
(PPCVEC): New macro, mask for vector instructions.
(powerpc_operands): Add table entries for above operand types.
(powerpc_opcodes): Add table entries for vector instructions.
* ppc-dis.c (print_insn_big_powerpc): Add PPC_OPCODE_ALTIVEC to mask.
(print_insn_little_powerpc): Likewise.
(print_insn_powerpc): Prepend 'v' when printing vector registers.
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