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This includes regenerating a bunch of files in opcodes/ with trunk cgen.
gprof/ChangeLog:
2016-04-20 Trevor Saunders <tbsaunde+binutils@tbsaunde.org>
* basic_blocks.c: Update old style function definitions.
* cg_arcs.c: Likewise.
* cg_print.c: Likewise.
* gen-c-prog.awk: Likewise.
* gmon_io.c: Likewise.
* hertz.c: Likewise.
* hist.c: Likewise.
* sym_ids.c: Likewise.
bfd/ChangeLog:
2016-04-20 Trevor Saunders <tbsaunde+binutils@tbsaunde.org>
* cache.c: Update old style function definitions.
* elf32-m68k.c: Likewise.
* elf64-mmix.c: Likewise.
* stab-syms.c: Likewise.
opcodes/ChangeLog:
2016-04-20 Trevor Saunders <tbsaunde+binutils@tbsaunde.org>
* alpha-dis.c: Regenerate.
* crx-dis.c: Likewise.
* disassemble.c: Likewise.
* epiphany-opc.c: Likewise.
* fr30-opc.c: Likewise.
* frv-opc.c: Likewise.
* ip2k-opc.c: Likewise.
* iq2000-opc.c: Likewise.
* lm32-opc.c: Likewise.
* lm32-opinst.c: Likewise.
* m32c-opc.c: Likewise.
* m32r-opc.c: Likewise.
* m32r-opinst.c: Likewise.
* mep-opc.c: Likewise.
* mt-opc.c: Likewise.
* or1k-opc.c: Likewise.
* or1k-opinst.c: Likewise.
* tic80-opc.c: Likewise.
* xc16x-opc.c: Likewise.
* xstormy16-opc.c: Likewise.
ld/ChangeLog:
2016-04-20 Trevor Saunders <tbsaunde+binutils@tbsaunde.org>
* emultempl/scoreelf.em: Likewise.
binutils/ChangeLog:
2016-04-20 Trevor Saunders <tbsaunde+binutils@tbsaunde.org>
* resres.c: Likewise.
gas/ChangeLog:
2016-04-20 Trevor Saunders <tbsaunde+binutils@tbsaunde.org>
* cgen.c: Likewise.
* config/tc-bfin.c: Likewise.
* config/tc-ia64.c: Likewise.
* config/tc-mep.c: Likewise.
* config/tc-metag.c: Likewise.
* config/tc-nios2.c: Likewise.
* config/tc-rl78.c: Likewise.
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Even though the opcodes were defined for these instructions,
the actual instruction definitions were lacking.
cpu/
* or1korbis.cpu (l-msync, l-psync, l-csync): New instructions.
opcodes/
* or1k-desc.c, * or1k-desc.h, * or1k-opc.c, * or1k-opc.h,
* or1k-opinst.c: Regenerate.
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* or1k.opc: Whitespace fixes.
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This adds support for the load-link/store-conditional
l.lwa/l.swa atomic instructions.
The support is added in such way, that the cpu description not
only describes the mnemonics, but also the functionality.
A couple of fixes to typos in nearby/related code are also snuck
into this.
cpu/
* or1korbis.cpu (h-atomic-reserve): New hardware.
(h-atomic-address): Likewise.
(insn-opcode): Add opcodes for LWA and SWA.
(atomic-reserve): New operand.
(atomic-address): Likewise.
(l-lwa, l-swa): New instructions.
(l-lbs): Fix typo in comment.
(store-insn): Clear atomic reserve on store to atomic-address.
Fix register names in fmt field.
opcodes/
* or1k-desc.c: Regenerated.
* or1k-desc.h: Likewise.
* or1k-opc.c: Likewise.
* or1k-opc.h: Likewise.
* or1k-opinst.c: Likewise.
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with support for the new or1k configuration.
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