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2019-06-13opcodes/or1k: Regenerate opcodesStafford Horne1-12/+222
This picks up changes for: - new orfpx64a32 spec additions - new unordered instructions - symbol and documentation updates opcodes/ChangeLog: * or1k-asm.c: Regenerated. * or1k-desc.c: Regenerated. * or1k-desc.h: Regenerated. * or1k-dis.c: Regenerated. * or1k-ibld.c: Regenerated. * or1k-opc.c: Regenerated. * or1k-opc.h: Regenerated. * or1k-opinst.c: Regenerated.
2019-01-01Update year range in copyright notice of binutils filesAlan Modra1-1/+1
2018-10-05or1k: Add the l.adrp insn and supporting relocationsStafford Horne1-1/+28
This patch adds the new instruction and relocation as per proposal: https://openrisc.io/proposals/ladrp This is to be added to the spec in an upcoming revision. The new instruction l.adrp loads the page offset of the current instruction offset by a 21-bit immediate shifted left 13-bits. This is meant to be used with a 13-bit lower bit page offset. This allows us to free up the got register r16. l.adrp r3, foo l.ori r4, r3, po(foo) l.lbz r5, po(foo)(r3) l.sb po(foo)(r3), r6 The relocations we add are: - BFD_RELOC_OR1K_PLTA26 For PLT jump relocation with PLT entry asm: plta() implemented using l.ardp, meaning no need for r16 (the GOT reg) - BFD_RELOC_OR1K_GOT_PG21 Upper 21-bit Page offset got address asm: got() - BFD_RELOC_OR1K_TLS_GD_PG21 Upper 21-bit Page offset with TLS General asm: tlsgd() Dynamic calculation - BFD_RELOC_OR1K_TLS_LDM_PG21 Upper 21-bit Page offset with TLS local asm: tlsldm() dynamic calculation - BFD_RELOC_OR1K_TLS_IE_PG21 Upper 21-bit Page offset with TLS Initial asm: gottp() Executable calculation - BFD_RELOC_OR1K_PCREL_PG21 Default relocation for disp21 (l.adrp instructions) - BFD_RELOC_OR1K_LO13 low 13-bit page offset relocation asm: po() i.e. mem loads, addi etc - BFD_RELOC_OR1K_SLO13 low 13-bit page offset relocation asm: po() i.e. mem stores, with split immediate - BFD_RELOC_OR1K_GOT_LO13, low 13-bit page offset with GOT calcs asm: gotpo() - BFD_RELOC_OR1K_TLS_GD_LO13 Lower 13-bit offset with TLS GD calcs asm: tlsgdpo() - BFD_RELOC_OR1K_TLS_LDM_LO13 Lower 13-bit offset with TLS LD calcs asm: tlsldmpo() - BFD_RELOC_OR1K_TLS_IE_LO13 Lower 13-bit offset with TLS IE calcs asm: gottppo() bfd/ChangeLog: yyyy-mm-dd Richard Henderson <rth@twiddle.net> * bfd-in2.h: Regenerated. * elf32-or1k.c: (or1k_elf_howto_table): Fix formatting for R_OR1K_PLT26, Add R_OR1K_PCREL_PG21, R_OR1K_GOT_PG21, R_OR1K_TLS_GD_PG21, R_OR1K_TLS_LDM_PG21, R_OR1K_TLS_IE_PG21, R_OR1K_LO13, R_OR1K_GOT_LO13, R_OR1K_TLS_GD_LO13, R_OR1K_TLS_LDM_LO13, R_OR1K_TLS_IE_LO13, R_OR1K_SLO13, R_OR1K_PLTA26. (or1k_reloc_map): Add BFD_RELOC_OR1K_PCREL_PG21, BFD_RELOC_OR1K_GOT_PG21, BFD_RELOC_OR1K_TLS_GD_PG21, BFD_RELOC_OR1K_TLS_LDM_PG21, BFD_RELOC_OR1K_TLS_IE_PG21, BFD_RELOC_OR1K_LO13, BFD_RELOC_OR1K_GOT_LO13, BFD_RELOC_OR1K_TLS_GD_LO13, BFD_RELOC_OR1K_TLS_GD_LO13, BFD_RELOC_OR1K_TLS_LDM_LO13, BFD_RELOC_OR1K_TLS_IE_LO13, BFD_RELOC_OR1K_SLO13, BFD_RELOC_OR1K_PLTA26. (elf_or1k_link_hash_table): Add field saw_plta. (or1k_final_link_relocate): Add value calculations for new relocations. (or1k_elf_relocate_section): Add section relocations for new relocations. (or1k_write_plt_entry): New function. (or1k_elf_finish_dynamic_sections): Add support for PLTA relocations using new l.adrp instruction. Cleanup PLT relocation code generation. * libbfd.h: Regenerated. * reloc.c: Add BFD_RELOC_OR1K_PCREL_PG21, BFD_RELOC_OR1K_LO13, BFD_RELOC_OR1K_SLO13, BFD_RELOC_OR1K_GOT_PG21, BFD_RELOC_OR1K_GOT_LO13, BFD_RELOC_OR1K_PLTA26, BFD_RELOC_OR1K_TLS_GD_PG21, BFD_RELOC_OR1K_TLS_GD_LO13, BFD_RELOC_OR1K_TLS_LDM_PG21, BFD_RELOC_OR1K_TLS_LDM_LO13, BFD_RELOC_OR1K_TLS_IE_PG21, BFD_RELOC_OR1K_TLS_IE_LO13. cpu/ChangeLog: yyyy-mm-dd Richard Henderson <rth@twiddle.net> * or1k.opc (parse_disp26): Add support for plta() relocations. (parse_disp21): New function. (or1k_rclass): New enum. (or1k_rtype): New enum. (or1k_imm16_relocs): Define new PO and SPO relocation mappings. (parse_reloc): Add new po(), gotpo() and gottppo() for LO13 relocations. (parse_imm16): Add support for the new 21bit and 13bit relocations. * or1korbis.cpu (f-disp26): Don't assume SI. (f-disp21): New pc-relative 21-bit 13 shifted to right. (insn-opcode): Add ADRP. (l-adrp): New instruction. gas/ChangeLog: yyyy-mm-dd Richard Henderson <rth@twiddle.net> * config/tc-or1k.c (or1k_apply_fix): Add BFD_RELOC_OR1K_TLS_GD_PG21, BFD_RELOC_OR1K_TLS_GD_LO13, BFD_RELOC_OR1K_TLS_LDM_PG21, BFD_RELOC_OR1K_TLS_LDM_LO13, BFD_RELOC_OR1K_TLS_IE_PG21, BFD_RELOC_OR1K_TLS_IE_LO13. * testsuite/gas/or1k/allinsn.s: Add test for l.adrp. * testsuite/gas/or1k/allinsn.d: Add test results for new instructions. * testsuite/gas/or1k/reloc-1.s: Add tests to generate R_OR1K_PLTA26, R_OR1K_GOT_PG21, R_OR1K_TLS_GD_PG21, R_OR1K_TLS_LDM_PG21, R_OR1K_TLS_IE_PG21, R_OR1K_LO13, R_OR1K_GOT_LO13, R_OR1K_TLS_GD_LO13, R_OR1K_TLD_LDM_LO13, R_OR1K_TLS_IE_LO13, R_OR1K_LO13, R_OR1K_SLO13 relocations. * testsuite/gas/or1k/reloc-1.d: Add relocation results for tests. * testsuite/gas/or1k/reloc-2.s: Add negative tests for store to gotpo(). * testsuite/gas/or1k/reloc-2.l: Add expected error test results. ld/ChangeLog: yyyy-mm-dd Richard Henderson <rth@twiddle.net> * testsuite/ld-or1k/or1k.exp: Add test cases for plt generation. * testsuite/ld-or1k/plt1.dd: New file. * testsuite/ld-or1k/plt1.s: New file. * testsuite/ld-or1k/plt1.x.dd: New file. * testsuite/ld-or1k/plta1.dd: New file. * testsuite/ld-or1k/plta1.s: New file. * testsuite/ld-or1k/pltlib.s: New file. include/ChangeLog: yyyy-mm-dd Richard Henderson <rth@twiddle.net> * elf/or1k.h (elf_or1k_reloc_type): Add R_OR1K_PCREL_PG21, R_OR1K_GOT_PG21, R_OR1K_TLS_GD_PG21, R_OR1K_TLS_LDM_PG21, R_OR1K_TLS_IE_PG21, R_OR1K_LO13, R_OR1K_GOT_LO13, R_OR1K_TLS_GD_LO13, R_OR1K_TLS_LDM_LO13, R_OR1K_TLS_IE_LO13, R_OR1K_SLO13, R_OR1K_PLTA26. opcodes/ChangeLog: yyyy-mm-dd Richard Henderson <rth@twiddle.net> * or1k-asm.c: Regenerated. * or1k-desc.c: Regenerated. * or1k-desc.h: Regenerated. * or1k-dis.c: Regenerated. * or1k-ibld.c: Regenerated. * or1k-opc.c: Regenerated. * or1k-opc.h: Regenerated. * or1k-opinst.c: Regenerated.
2018-03-03opcodes error messagesAlan Modra1-12/+18
Another patch aimed at making binutils comply with the GNU coding standard. The generated files require https://sourceware.org/ml/cgen/2018-q1/msg00004.html cpu/ * frv.opc: Include opintl.h. (add_next_to_vliw): Use opcodes_error_handler to print error. Standardize error message. (fr500_check_insn_major_constraints, frv_vliw_add_insn): Likewise. opcodes/ * sysdep.h (opcodes_error_handler): Define. (_bfd_error_handler): Declare. * Makefile.am: Remove stray #. * opc2c.c (main): Remove bogus -l arg handling. Print "DO NOT EDIT" comment. * aarch64-dis.c, * arc-dis.c, * arm-dis.c, * avr-dis.c, * d30v-dis.c, * h8300-dis.c, * mmix-dis.c, * ppc-dis.c, * riscv-dis.c, * s390-dis.c, * sparc-dis.c, * v850-dis.c: Use opcodes_error_handler to print errors. Standardize error messages. * msp430-decode.opc, * nios2-dis.c, * rl78-decode.opc: Likewise, and include opintl.h. * nds32-asm.c: Likewise, and include sysdep.h and opintl.h. * i386-gen.c: Standardize error messages. * msp430-decode.c, * rl78-decode.c, rx-decode.c: Regenerate. * Makefile.in: Regenerate. * epiphany-asm.c, * epiphany-desc.c, * epiphany-dis.c, * epiphany-ibld.c, * fr30-asm.c, * fr30-desc.c, * fr30-dis.c, * fr30-ibld.c, * frv-asm.c, * frv-desc.c, * frv-dis.c, * frv-ibld.c, * frv-opc.c, * ip2k-asm.c, * ip2k-desc.c, * ip2k-dis.c, * ip2k-ibld.c, * iq2000-asm.c, * iq2000-desc.c, * iq2000-dis.c, * iq2000-ibld.c, * lm32-asm.c, * lm32-desc.c, * lm32-dis.c, * lm32-ibld.c, * m32c-asm.c, * m32c-desc.c, * m32c-dis.c, * m32c-ibld.c, * m32r-asm.c, * m32r-desc.c, * m32r-dis.c, * m32r-ibld.c, * mep-asm.c, * mep-desc.c, * mep-dis.c, * mep-ibld.c, * mt-asm.c, * mt-desc.c, * mt-dis.c, * mt-ibld.c, * or1k-asm.c, * or1k-desc.c, * or1k-dis.c, * or1k-ibld.c, * xc16x-asm.c, * xc16x-desc.c, * xc16x-dis.c, * xc16x-ibld.c, * xstormy16-asm.c, * xstormy16-desc.c, * xstormy16-dis.c, * xstormy16-ibld.c: Regenerate.
2018-01-03Update year range in copyright notice of binutils filesAlan Modra1-1/+1
2017-07-11Mark generated cgen files read-onlyAlan Modra1-0/+1
* cgen.sh: Mark generated files read-only. * epiphany-asm.c: Regenerate. * epiphany-desc.c: Regenerate. * epiphany-desc.h: Regenerate. * epiphany-dis.c: Regenerate. * epiphany-ibld.c: Regenerate. * epiphany-opc.c: Regenerate. * epiphany-opc.h: Regenerate. * fr30-asm.c: Regenerate. * fr30-desc.c: Regenerate. * fr30-desc.h: Regenerate. * fr30-dis.c: Regenerate. * fr30-ibld.c: Regenerate. * fr30-opc.c: Regenerate. * fr30-opc.h: Regenerate. * frv-asm.c: Regenerate. * frv-desc.c: Regenerate. * frv-desc.h: Regenerate. * frv-dis.c: Regenerate. * frv-ibld.c: Regenerate. * frv-opc.c: Regenerate. * frv-opc.h: Regenerate. * ip2k-asm.c: Regenerate. * ip2k-desc.c: Regenerate. * ip2k-desc.h: Regenerate. * ip2k-dis.c: Regenerate. * ip2k-ibld.c: Regenerate. * ip2k-opc.c: Regenerate. * ip2k-opc.h: Regenerate. * iq2000-asm.c: Regenerate. * iq2000-desc.c: Regenerate. * iq2000-desc.h: Regenerate. * iq2000-dis.c: Regenerate. * iq2000-ibld.c: Regenerate. * iq2000-opc.c: Regenerate. * iq2000-opc.h: Regenerate. * lm32-asm.c: Regenerate. * lm32-desc.c: Regenerate. * lm32-desc.h: Regenerate. * lm32-dis.c: Regenerate. * lm32-ibld.c: Regenerate. * lm32-opc.c: Regenerate. * lm32-opc.h: Regenerate. * lm32-opinst.c: Regenerate. * m32c-asm.c: Regenerate. * m32c-desc.c: Regenerate. * m32c-desc.h: Regenerate. * m32c-dis.c: Regenerate. * m32c-ibld.c: Regenerate. * m32c-opc.c: Regenerate. * m32c-opc.h: Regenerate. * m32r-asm.c: Regenerate. * m32r-desc.c: Regenerate. * m32r-desc.h: Regenerate. * m32r-dis.c: Regenerate. * m32r-ibld.c: Regenerate. * m32r-opc.c: Regenerate. * m32r-opc.h: Regenerate. * m32r-opinst.c: Regenerate. * mep-asm.c: Regenerate. * mep-desc.c: Regenerate. * mep-desc.h: Regenerate. * mep-dis.c: Regenerate. * mep-ibld.c: Regenerate. * mep-opc.c: Regenerate. * mep-opc.h: Regenerate. * mt-asm.c: Regenerate. * mt-desc.c: Regenerate. * mt-desc.h: Regenerate. * mt-dis.c: Regenerate. * mt-ibld.c: Regenerate. * mt-opc.c: Regenerate. * mt-opc.h: Regenerate. * or1k-asm.c: Regenerate. * or1k-desc.c: Regenerate. * or1k-desc.h: Regenerate. * or1k-dis.c: Regenerate. * or1k-ibld.c: Regenerate. * or1k-opc.c: Regenerate. * or1k-opc.h: Regenerate. * or1k-opinst.c: Regenerate. * xc16x-asm.c: Regenerate. * xc16x-desc.c: Regenerate. * xc16x-desc.h: Regenerate. * xc16x-dis.c: Regenerate. * xc16x-ibld.c: Regenerate. * xc16x-opc.c: Regenerate. * xc16x-opc.h: Regenerate. * xstormy16-asm.c: Regenerate. * xstormy16-desc.c: Regenerate. * xstormy16-desc.h: Regenerate. * xstormy16-dis.c: Regenerate. * xstormy16-ibld.c: Regenerate. * xstormy16-opc.c: Regenerate. * xstormy16-opc.h: Regenerate.
2017-01-02Update year range in copyright notice of all files.Alan Modra1-1/+1
2016-02-02opcodes/cgen: Rework calculation of shift when inserting fieldsAndrew Burgess1-3/+10
The calculation of the shift amount, used to insert fields into the instruction buffer, is not correct when the following conditions are all true: - CGEN_INT_INSN_P is defined, and true. - CGEN_INSN_LSB0_P is true - Total instruction length is greater than the length of a single instruction word (the instruction is made of multiple words) - The word offset is non-zero (the field is outside the first word) When the above conditions are all true, the calculated shift fails to take account of the total instruction length. After this commit the calculation of the shift amount is split into two parts, first we calculate the shift required to get to BIT0 of the word in which the field lives, then we calculate the shift required to place the field within the instruction word. The change in this commit only effects the CGEN_INT_INSN_P defined true case, but changes the code for both CGEN_INSN_LSB0_P true, and false. In the case of CGEN_INSN_LSB0_P being false, the code used to say: shift = total_length - (word_offset + start + length); Now it says: shift_to_word = total_length - (word_offset + word_length); shift_within_word = word_length - start - length; shift = shift_to_word + shift_within_word; From which we can see that in all cases the computed shift value should be unchanged. In the case of CGEN_INSN_LSB0_P being true, the code used to say: shift = (word_offset + start + 1) - length; Now it says: shift_to_word = total_length - (word_offset + word_length); shift_within_word = start + 1 - length; shift = shift_to_word + shift_within_word; In the case where 'total_length == word_length' AND 'word_offset == 0' (which indicates an instruction of a single word), we see that the computed shift value will be unchanged. However, when the total_length and word_length are different, and the word_offset is non-zero then the computed shift value will be different (and correct). opcodes/ChangeLog: * cgen-ibld.in (insert_normal): Rework calculation of shift. * epiphany-ibld.c: Regenerate. * fr30-ibld.c: Regenerate. * frv-ibld.c: Regenerate. * ip2k-ibld.c: Regenerate. * iq2000-ibld.c: Regenerate. * lm32-ibld.c: Regenerate. * m32c-ibld.c: Regenerate. * m32r-ibld.c: Regenerate. * mep-ibld.c: Regenerate. * mt-ibld.c: Regenerate. * or1k-ibld.c: Regenerate. * xc16x-ibld.c: Regenerate. * xstormy16-ibld.c: Regenerate.
2016-01-01Copyright update for binutilsAlan Modra1-1/+1
2015-08-12Remove trailing spaces in opcodesH.J. Lu1-4/+4
2015-01-02ChangeLog rotatation and copyright year updateAlan Modra1-1/+1
2014-06-12Whitespace fixes for cpu/or1k.opcAlan Modra1-6/+5
* or1k.opc: Whitespace fixes.
2014-04-22Remove support for the (deprecated) openrisc and or32 configurations and replaceChristian Svensson1-0/+1051
with support for the new or1k configuration.
generated by cgit v1.1 at 2024-11-22 04:12:25 +0000